RNM Simulation V3

Mixed Signal Simulation with Real Number Modeling
Rapid Adoption Kit (RAK)

Cadence Design Systems, Inc.
July 2013
Audience: Engineers who want to simulate and debug designs

with Real Number Models in Cadence Mixed Signal Flow
Pre-requisite: Familiarity with either digital or analog simulation,

preferred to having completed Behavioral Modeling RAK
Goals:
Learn the basics of invoking mixed signal verification
in Cadence flows:
Virtuoso GUI based verification flow (AVUM)
Text based Command line verification flow (AIUM)
Real Number Modeling support in both flows
2012 Cadence Design Systems, Inc. All rights reserved.
Agenda
AIUM and AVUM Use Model Introduction
RNM (Real Number Modeling) in Virtuoso (AVUM)
RNM in Command Line (AIUM)
LABs
AMS in ADE and AMS Command Line Use Model

AMS Designer
AMSUltra & AMS Spectre Or AMS-APS
AMS in ADE
AMS-irun
(Virtuoso GUI Based)
(Text Based Command Line)
irun
AMS in ADE
(OSS+irun)
+ amsd block
IUS & IC
IUS only
AVUM and AIUM

AMSD Virtuoso Use Model (AVUM) refers to running
AMSD simulation within Virtuoso platform. AVUM
targets analog-centric designs. To run AMSD in
Virtuoso Environment, you need to install both IUS and
IC releases.
AMSD Incisive Use Model (AIUM) takes the textual

netlist only (including verilog/AMS modules and
HPSICE/Spectre format), which is totally out of Virtuoso
and launched from command-line. Its more for digitalcentric design verification. To run AMSD Incisive Use
Model, you only need to install IUS release.
Build Up AMS Verification Plan with HED in AVUM

HED
ROM
Verilog-D
Application
Specific
Logic
RAM
VHDL-D
uP
SPICE
Test
Verilog-AMS
Complex
RF
USB
VHDL-AMS
PLL
AMS
Custom
DSP
Schematic
Extracted
CONFIG
The hierarchy editor (HED) makes it easy to select the view representation for a
cell. The user creates a configuration with HED.
6
Design Configuration with Hierarchy Editor in AVUM Flow

Hierarchy Editor helps you configure
design blocks easily
HED
Verilog-D
VHDL-D
SPICE
Verilog-AMS
VHDL-AMS
Schematic
Extracted
CONFIG
Cadence 5x library structure allows a cell to own many different
views, including verilog, VHDL, ... In HED, it is easy to select the
view representation for a cell to be used in simulation.
7
AIUM Flow (AMS Incisiv User Model)

Extensions
Basic Application
SystemVerilog
Verilog/AMS + SPICE AMS-Simulation
Digital Verilog + SPICE/Spectre

Verilog on top, SPICE in middle
Simple use model:
VHDL
VHDL-AMS
Matlab
irun + AMS control file
Specman
AMS control file: user-friendly inputs
SystemC
Verilog
Verilog
VHDL
D
A
Verilog
Verilog
SV
A
SPICE
Simple Use Model for AIUM

irun ./source/digital/*.v \ ----- Source file list
./amscf.scs \
----- ams control file
-amsf \
----- fastSpice option
-timescale 1ns/100ps \
-input probe.tcl
----- TCL Command
Source file includes verilog/AMS module,VHDL /AMS module,
Spectre/Spice netlist
amscf.scs contains connect module definition within amsd block
and other include files
amsf option will turn on Ultrasim analog simulator
probe.tcl includes probes and simulation control commands
AMS Control File in AIUM Unified the Design Configuration

Unified design configuration into a single file
Design configuration (analog or digital/real), default is digital.
Include analog spice netlist & device models
Include analog control file (file that tells ultrasim/spectre how
it should work)
Handling A/D Connect Module and Connect Rules
Appropriate
AMS Control File Example
ConnectModule/
include "./models/models.scs
//device model file
Connect rule is
include "./source/analog/PLL.sp
//spice netlist file
picked
include "./top.scs
//analog control file
automatically
amsd {
portmap subckt=pll_top file=pll_top.pb //port map between A and D
config cell=pll_top use=spice
//pll_top is configured as spice
ie vsup=1.8
//use 1.8v as power supply
}
10
Agenda
LABs
11
RNM can be represented in VerilogAMS (wreal), System-Verilog and

VHDL real.
Key features for wreal

Multiple driver support
Discipline association
Resolution functions for
multiple drivers
12
Verilog- AMS
VHDL AMS
Real/
Wreal
FastSpice
Pure
Digital
Spice/APS
Performance
Spice/APS
FastSpice
Accuracy
Model analog block operation

as discrete real data
Signal flow based modeling
approach
Discrete solver only
Very high simulation
performance
Event driven or sampled
data modelling of analog
operation
No analog solver, no
convergence problems!
Effort
Real Number Modeling
Verilog-AMS
VHDL-AMS
Real/
Wreal
Pure
Digital
Performance
The wreal datatype in Verilog-AMS

Wreal datatype declares a
real net that has a real-valued
connection to other modules
A wreal net is discrete in time
(event based, see the @(vin))
It is continuous in value real
13
13
module vco(vin, clk);

input vin; wreal vin;
output clk;
reg clk;
real freq,clk_delay;
always @(vin) begin
freq = center_freq + vco_gain*vin;
clk_delay = 1.0/(2*freq);
end
always #(clk_delay) clk = ~clk;
endmodule
Benefit of RNM in Virtuoso
14
Support Top-Down Mixed-Signal SoC Design Methodology

One design environment shared by both digital and analog designers
Analog schematic based design styles
Digital/RNM text based design supported
Wreal modeling natively supported in Virtuoso environment
Importing ADE L states and ADEXL states
One button simulator start
ViVA results post processing for wreal signals
Highly configurable designs using Hierarchy Editor
Multilingual design and simulation solution
Display partitions for real and Rmixed signals and blocks
ADE Stop time is supported for DMS simulation (wreal, without analog
solvers used)
AMS in Virtuoso ADE Use Model Operation Steps

1. Start Virtuoso, Open Library Manager and Open
Schematic/HED
2. Config Design with HED, and Review Modules from
HED or Schematic
3. Launch ADE L (or ADE XL) from Schematic Editor
4. Set Up ADE L (or load existing ADE State for
previously saved set up)
5. One Button Click (Green Button) to Run Simulation
6. Review Simulation Results from ViVA or SimVision
7. Review AMS/DMS Partition from Schematic Editor
8. Exit Virtuoso
(Detail follows )
15
Start Virtuoso Environment and Open Library Manager
In Unix prompt, type:

virtuoso &
CIW window pops up.
Select Tools -> Library Manager
by double clicking on this item.
16
Open Design from Library Manager
From library manager, select Library, Category, Cell and View to Open.
In pop up window, select both config and schematic views by clicking Yes
ratio buttons.
Note: Make sure Show Category option is checked otherwise category will
not show up.
17
Config Design from HED
In HED, select target cell by highlighting it. Right click on the cell
name, select Set Cell View in pop up menu, and then select
intended view name from the list (i.e. verilogams). Select Open to
view and edit the modules.
18
Review Wreal Behavioral Model in Schematic
In this schematic, block lyc_dac_6bits and lyc_dac_6bits_wreal are equivalent blocks

with the same input logic adc_out<0:5>, the output are electrical signal and wreal
signal, respectively. Both output signals have similar values after simulation. Since the
input side boundaries have different types of signals connected, there will be L2E and
E2R connect modules inserted to convert the signals to compatible disciplines.
19
Review Wreal Behavioral Model in Schematic (cont.)
In Schematic Editor, use ] or [ to zoom in or zoom out to review the

blocks. Select the target block and type key e to open up the Descend
form, and OK to open the behavioral model (i.e. wreal models or other
types of models). You can review/edit models from here or from HED in
previous step.
20
Review Wreal Behavioral Model in Schematic (cont.)
Wreal Signals are

used to replace
original electrical
signals
21
Return to Top Level Schematic after Review
After review, Select Design ->

Return to go back to the previous
level, or Select Return to Top to
top level.
22
Launch ADE (Analog Design Environment)
23
Load Previously Saved ADE State
ADE State is saved set up for future reference and reuse to improve productivity.
To load previously saved state:
1. Session -> Load State
2. Select CellView, find the saved state name (i.e. ams_state1), OK.
24
Review Model File Path
Model file path

is previously
set up
25
Review Simulation Analysis Set Up
Transient Analysis
is previously set up
26
Review Output Set Up
Set up output signals

to be saved or plotted
27
Select Spectre/Ultrasim as Analog Simulator Solver
28
Select Simulation Options
Add more irun

options here
29
Run Simulation and Watch Log File Generation
In ADE window, click Green

RUN Button, AMS Designer
Simulation starts to run.
During the simulation, the log
file will be printed out in a
separate window (see right
side).
The log file is also available
from irun.log file under:
./simulation/top_cell_name/ams
/config/psf/irun.log
30
Review Simulation Results in ViVA
Electrical signal and

wreal signal overlap
31
Review Simulation Results in ViVA (cont.)
Split
Split the 2 overlapped signals

to further investigate
wreal
32
Post Processing Wreal Signals in ViVA
With wreal signal selected, launch Calculator by selecting Tools Calculator from ViVA
Window. The signal will be loaded to Calculator buffer area for further processing.
33
Post Processing Wreal Signals in ViVA (cont.)
From Calculator function panel, select function (i.e. abs), the buffer
area will show the function selected to process the wreal signal.
34
Post Processing Wreal Signals in ViVA (cont.)
The post-processed result can be plotted as any other signals.

ViVA Calculator can post-process wreal signals the same way as it
does to regular electrical signals.
35
Display Analog/Digital/Mixed Signal Net/Instance Partitions in Schematic
Mixed Signal design partition feature allows users to highlight the nets
or instances that belong to analog domain, digital domain, real
domain or mixed domain. To display partitions, select AMS->Display
Partition->Initialize (after elab or ncsim finishes). After initialization,
user can display partitions and/or IE information.
36
Display Analog/Digital/Mixed Signal Net/Instance Partitions in Schematic (cont.)
Wreal Block
Highlighted
After initialization, select Real Only from AMS Partition

menu form. Watch the highlighted wreal block.
37
Display IE Information from AMS Partition Form
IE (Interconnect Element, like L2E, E2L, E2R, R2E, etc.) can be highlighted in schematic for
easy debug. To do so, select AMS -> Display Partition -> IE Information. In pop up AMS CMs
Display window, select interested net name, then click Go to button. The IE details will be
printed out in the window and the nets will be highlighted in the schematic.
38
Agenda
LABs
39
RNM Simulation in Command Line (AIUM Flow)

RNM command line use model example:
irun access +rw test_bench.vams dut.v amscf.scs input probe.tcl

Where:
-clean will clean up the old INCA_libs if it exists to prepare for new compilation.
-access +rw will turn on read/write access to allow accessing all digital objects in
a VerilogAMS design for signal probing and debugging.
- Source files *vams, *v, *scs etc. are included in the command line
- probe.tcl will include tcl command lines and probes for saving signals
- Other commonly used options include +wreal_info, +dr_info to show wreal
declaration/coercion status and the discipline resolution results.
For more information on other irun command line options, use the
following command:
irun helpall | grep option_name
40
RNM Simulation Command Line Option Examples

+wreal_info:
Elaborator option allows viewing which nets in the design are declared or
coerced to wreal
-ieinfo:
Generate ams ie information report in a separate file ams_ieinfo.log.
+DR_INFO
Provide discipline resolution information for the nets.
irun Command Line Example:

irun clean -ieinfo -gui -message -access +rwc +wreal_info coercion.vams
41
ams_ieinfo.log examples
1. Interface Elements at the block <instance> top of <master> top (file : ./test.vams)
List of Ports connected to net top.net : (Total: 5)
Automatically inserted : top.net__digInst4__in
top.digInst1.in (ddiscrete_1_8 input)
Connect Module : E2L_2
Mode :
Split
top.digInst3.in (ddiscrete_2 input)
Net :
top.net (discipline: electrical, nettype: electrical)
Port :
top.digInst4@dig_child<module>.in (discipline:
ddiscrete_1_5,
direction:
input, nettype:
top.anaInst.out
(electrical
output)
wire)
Discipline of Port (Ain): electrical, Analog Port
Discipline of Port (Dout): ddiscrete_1_5, Digital Port
Parameters :
Drivers of Port Dout: No drivers
vsup
:1.5
Loads of Port Dout: No loads
vthi
:1
Sensitivity information:
vtlo
:0.5
No Sensitivity info
vtol
:0.125
IE Report Summary (with disciplines and directions):
tr
:2e-10
E2L_2 ( electrical input; ddiscrete_2 output;) total: 1
txdel
:8e-10
E2L_2 ( electrical input; ddiscrete_1_5
ttol_c :5e-11
output;) total: 1
vtlox
:0.625
E2L_2 ( electrical input; ddiscrete_1_8
vthix
:0.875
output;) total: 1
-------------------------------------------------------------------Effective Number of IE Instances:
Total Number of E2L_2: 3
Total Number of Connect Modules : 3
42
Using Command Line Script Generated from Virtuoso ADE
After Simulation in ADE flow, we will get ready-to-use command line

script that can be reused in regression test or further debug. The irun
script can be generated from ADE L or from ADE XL.
The script runSimulation is located at

./simulation/cell_name/ams/config/netlist
In irun script runSimulation, there is a line as following:

irun f irunArgs
irunArgs is the file including all irun options
User can add one option -gui to irunArgs.

This will help to invoke SimVision during simulation in command line.
43
SimVision Support for RNM
With gui option in irun command line, SimVision will pop up

automatically when running irun command line.
44
SimVision Waveform Display for RNM
Wreal
Signal
When Format -> Trace is

Sample/Hold
Wreal signal matches original electrical signal very well when

using Analog/Sample+Hold to display the output signal.
45
SimVision Waveform Display for RNM (cont.)
When Format -> Trace

is Analog/Linear
Wreal signal will not match original electrical signal very well when
using Analog/Linear to display the output signal in this case.
46
SimVision Waveform Display for RNM (cont.)
Many points from

electrical signal means
longer simulation time
Only few points from wreal

means faster simulation speed
47
The wreal signal difference from different display formats can be explained with symbol
plotting as above. Select Format -> Symbol -> Points Only to plot the simulation points for
detailed debug. This also explains why RNM simulation is much more efficient than pure
analog
design.
2012 Cadence
Design Systems, Inc. All rights reserved.
Examples and Tutorials

<INCISIV_INSTALL>/tools/amsd/samples/aium/Real_modeling_irun
<INCISIV_INSTALL>/tools/amsd/samples/aium/wreal_r2l_demo
<INCISIV_INSTALL>/tools/amsd/samples/aium/wreal_resolution_function
<INCISIV_INSTALL>/tools/amsd/samples/aium/wreal_table_modeling
48
LAB
49
Wreal modeling natively supported in Virtuoso environment.

Display partition for real and Rmixed signals and blocks
ADE Stop time can be used for DMS (wreal) simulation.
Importing ADE state
ViVA results post processing for wreal signals
SimVision support for Wreal/command line use model
50

RNM Simulation V3

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Mixed Signal Simulation with Real Number Modeling

Rapid Adoption Kit (RAK)

Audience: Engineers who want to simulate and debug designs

Pre-requisite: Familiarity with either digital or analog simulation,

2012 Cadence Design Systems, Inc. All rights reserved.

AIUM and AVUM Use Model Introduction

RNM (Real Number Modeling) in Virtuoso (AVUM)

RNM in Command Line (AIUM)

2012 Cadence Design Systems, Inc. All rights reserved.

AMS in ADE and AMS Command Line Use Model

(Virtuoso GUI Based)

(Text Based Command Line)

2012 Cadence Design Systems, Inc. All rights reserved.

AVUM and AIUM

AMSD Incisive Use Model (AIUM) takes the textual

2012 Cadence Design Systems, Inc. All rights reserved.

Build Up AMS Verification Plan with HED in AVUM

2012 Cadence Design Systems, Inc. All rights reserved.

Design Configuration with Hierarchy Editor in AVUM Flow

2012 Cadence Design Systems, Inc. All rights reserved.

AIUM Flow (AMS Incisiv User Model)

Verilog/AMS + SPICE AMS-Simulation

Digital Verilog + SPICE/Spectre

irun + AMS control file

AMS control file: user-friendly inputs

2012 Cadence Design Systems, Inc. All rights reserved.

Simple Use Model for AIUM

2012 Cadence Design Systems, Inc. All rights reserved.

AMS Control File in AIUM Unified the Design Configuration

2012 Cadence Design Systems, Inc. All rights reserved.

AIUM and AVUM Use Model Introduction

RNM (Real Number Modeling) in Virtuoso (AVUM)

RNM in Command Line (AIUM)

2012 Cadence Design Systems, Inc. All rights reserved.

RNM can be represented in VerilogAMS (wreal), System-Verilog and

Key features for wreal

2012 Cadence Design Systems, Inc. All rights reserved.

Model analog block operation

Real Number Modeling

The wreal datatype in Verilog-AMS

2012 Cadence Design Systems, Inc. All rights reserved.

module vco(vin, clk);

Benefit of RNM in Virtuoso

Support Top-Down Mixed-Signal SoC Design Methodology

2012 Cadence Design Systems, Inc. All rights reserved.

AMS in Virtuoso ADE Use Model Operation Steps

2012 Cadence Design Systems, Inc. All rights reserved.

Start Virtuoso Environment and Open Library Manager

In Unix prompt, type:

2012 Cadence Design Systems, Inc. All rights reserved.

Open Design from Library Manager

2012 Cadence Design Systems, Inc. All rights reserved.

Config Design from HED

2012 Cadence Design Systems, Inc. All rights reserved.

Review Wreal Behavioral Model in Schematic

In this schematic, block lyc_dac_6bits and lyc_dac_6bits_wreal are equivalent blocks

2012 Cadence Design Systems, Inc. All rights reserved.

Review Wreal Behavioral Model in Schematic (cont.)

In Schematic Editor, use ] or [ to zoom in or zoom out to review the

2012 Cadence Design Systems, Inc. All rights reserved.

Review Wreal Behavioral Model in Schematic (cont.)

Wreal Signals are

2012 Cadence Design Systems, Inc. All rights reserved.

Return to Top Level Schematic after Review