8230e DELL Vostro 3350 Wistron Nirvana 13

5
Nirvana 13 UMA Schematics Document

D
Sandy Bridge
Intel PCH
2011-01-18
REV : A00
DY :None Installed
10mW: External circuit for 10mW solution installed.
BT: Stand alone BT Module.
GSENSOR_ADI: Stuff for ADI G-Sensor.
VCCSA_PWM: Stuff for VCCSA PWM solution.
VCCSA_LDO: Stuff for VCCSA LDO solution.
P2800A1: Stuff for P2800EA1
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5
Document Number
Cover
Rev
A00
Nirvana 13
Tuesday, January 18, 2011
Sheet
1
of
103
Nirvana 13 UMA Block Diagram

(6 layers)
Project Code: 91.4ID01.001

PCB P/N :10261
Revision : -1
PCB LAYER
UMA
L1:Top
L2:VCC
L3:Signal
L4:Signal
L5:GND
L6:Bottom
CPU DC/DC
42
VT1316+VT1317
INPUTS
OUTPUTS
5V_S5
VCC_CORE
SYSTEM DC/DC
44
VT1316+VT1317
INPUTS
OUTPUTS
5V_S5
VCC_GFXCORE
Intel CPU
SYSTEM DC/DC
DDRIII 1066/1333 Channel A
DDRIII 1066/1333 Channel B
48
TPS51461/APL5916
DDRIII
Slot 1
1066/1333
Sandy Bridge
INPUTS
OUTPUTS
5V_S5
0D85V_S0
SYSTEM DC/DC
DDRIII
Slot 2
1066/1333
46
TPS51216
INPUTS
4,5,6,7,8,9,10,11,12,13
OUTPUTS
1D5V_S3
0D75V_S0
DDR_VREF_S3
DCBATOUT
SYSTEM DC/DC
45
TPS51218
FDIx4x2
C
HDMI
PCIE x 1
Intel
PCH
Cougar Point
LVDS(Single Channel)
49
CRT
(On Daughter Board)
HDMI
51
LCD
DMIx4
RGB CRT
50
Card Reader
RTS5138
32
Bluetooth V3.0
63
PCIE x 1,USB2.0 x 1
INPUTS
USB3.0 Controller
NEC uPD720200F1
USB2.0 x 4
40
BQ24745
OUTPUTS
USB3.0 x 2
DCBATOUT
SYSTEM DC/DC
INPUTS
Mini-Card
PCIE x 1,USB2.0 x 1
LPC I/F
OUTPUTS
DCBATOUT
Mini-Card
802.11a/b/g
26
65
SYSTEM DC/DC
47
TPS51311
USB2.0 x 1
USB 2.0 x 1
USB CHARGE
INPUTS
ESATA/USB
Combo 57
PI5USB14550 57
41
5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5
15V_S5
SIM
SATA ports (6)
ACPI 1.1
Finger Print 64
TI CHARGER
+DC_IN_S5
+PBATT
WWAN
PCIE ports (8)

USB 2.0 x 1
1D05V_VTT
TPS51427
High Definition Audio
USB 2.0 x 1
OUTPUTS
DCBATOUT
RJ45
CONN
Realtek
RTL8111E-VB
14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)
SD/MMC+/MS/
MS Pro/xD/SDXC
(8 in 1) 74
PCIE x 1
10/100/1000 LOM
INPUTS
OUTPUTS
3D3V_S5
1D8V_S0
CAMERA
w/ Digital MIC 49
17,18,19,20,21,22,23,24,25,26
HDA
USB 2.0 x 1
Switches
SATA x 1
INPUTS
36
OUTPUTS
26
1D5V_S0
MIC IN
Flash ROM
4MB 60
IDT
92HD87B1
SATA x 2
SMBus
CODEC
HP
LPC Bus
SPI
1D5V_S3
HDD 56
5V_S5
5V_S0
3D3V_S5
3D3V_S0
ODD 56
Free Fall Sensor

79
KBC
29
ADC
NUVOTON
27
NPCE795PA
DAC
Thermal Sensor
Main:ENEP2800
<Core Design>
28
1CH SPEAKER
Touch
PAD69
Int.
KB69
Wistron Corporation
FAN Controller
Main:ENEP2793
28

Fan 55
Title
Size
A3
25
Date:
5
Block Diagram
Document Number
Rev
A00
Nirvana 13
Sheet
1
of
103
PCH Strapping
Name
Processor Strapping
Huron River Schematic Checklist Rev.1_0

Schematics Notes
SPKR
Reboot option at power-up

Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Enable when Pull-up.
INIT3_3V#
Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".
GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51
GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3 power rail.
Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high
Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K5% pull-up

resistor to PCH VCCPNAND rail and a 4.7K5% series resistor.
Boot BIOS Strap bit 0
SATA1GP
/GPIO19
This Signal has a weak internal pull-up.

Note: This field determines the destination of accesses to the BIOS memory range.
This strap is used in conjunction with Boot BIOS
Destination Selection 1 strap.
Bit11
Bit 10
Boot BIOS Destination
0
1
Reserved
1
0
PCI
1
1
SPI
0
0
LPC
HDA_SDO
Signal has a weak internal pull-down.

Default: the security measures defined in the Flash Descriptor will be in effect.
Pull-up: the Flash Descriptor Security will be overridden.
This strap should only be asserted high via external pull-up in manufacturing
or debug environments ONLY.
On-Die PLL Voltage Regulator Voltage Select

HDA_SYNC
Huron River Schematic Checklist Rev.1_0
Strap Description
Configuration (Default value for each bit is

1 unless specified otherwise)
CFG[2]
PCI-Express Static
Lane Reversal
1:
0:
CFG[6:5]
DMI and FDI Tx/Rx Termination Voltage

DF_TVS
Normal Operation.
Lane Numbers Reversed
TLS Confidentiality
GPIO15
Deep S4/S5 Well On-Die Voltage Regulator Enable

DSWVRMEN
This signal enables the internal Deep Sleep 1.05 V regulators.

This signal must be always pulled-up to VccRTC.
15 -> 0, 14 -> 1, ...
PCI-Express
Port Bifurcation
Straps
CFG[7]
PEG DEFER TRAINING
POWER PLANE
VOLTAGE
5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
11
1: PEG Train immediately following xxRESETB de assertion

1
0: PEG Wait for BIOS for training
Voltage Rails
DESCRIPTION
ACTIVE IN
C
S0
CPU Core Rail
Graphics Core Rail
5V_USBX_S3
1D5V_S3
DDR_VREF_S3
5V
1.5V
0.75V
BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5
6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V
3D3V_LAN_S5
3.3V
WOL_EN
Legacy WOL
3D3V_AUX_KBC
3.3V
DSW, Sx
ON for supporting Deep Sleep states
3D3V_AUX_S5
3.3V
G3, Sx
Powered by Li Coin Cell in G3

and +V3ALW in Sx
S3
AC Brick Mode only

All S states
On-Die PLL Voltage Regulator

This signal has a weak internal pull-up.
The On-Die PLL voltage regulator is enabled when sampled high.
When sampled low the On-Die PLL Voltage Regulator is disabled.
If not used, 8.2-k to 10-k pull-up to +V3.3A power-rail.
GPIO28
Default
Value
Disabled - No Physical Display Port attached to

1: Embedded Display Port.
Enabled - An external Display Port device is
0: connectd to the Embedded Display Port
11 : x16 - Device 1 functions 1 and 2 disabled
10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled
Display Port
Presence strap
This signal has a weak internal pull-down.

On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality
This signal has a weak internal pull-down.
NOTE: A strong pull-up may be needed for GPIO functionality
Pin Name
CFG[4]
Integrated 1.05 V VRM Enable / Disable

INTVRMEN
USB Table
PCIE Routing
LANE1
LANE2
LANE3
A
SATA Table
SATA
X
Pair
LAN (I/O Board)

Mini Card2(WWAN)
LANE4
Mini Card1(WLAN)
LANE5
USB3.0
LANE6
LANE7
LANE8
Pair
Device
Device
ESATA / USB COMBO
Fingerprint
HDD1
BLUETOOTH
N/A
Mini Card2 (WWAN)
N/A
CARD READER
N/A
ODD
ESATA
10
11
Mini Card1 (WLAN)
12
CAMERA
13
SMBus ADDRESSES
I 2 C / SMBus Addresses
Device
EC SMBus 1
Battery
Capacity Board
EC SMBus 2
PCH
MXM
LCD
Thermal Sensor
PCH SMBus
CK505 Clock Generator
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
Ref Des
HURON RIVER ORB

Address
Hex
Bus
KBC_SDA1/KBC_SCL1
KBC_SDA1/KBC_SCL1
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
KBC_SDA2/KBC_SCL2
<Core Design>
A
Wistron Corporation
PCH_SMBDATA/PCH_SMBCLK
Title
Size
A3
Date:
Document Number
Table of Content
Rev
Nirvana 13
W ednesday, December 22, 2010
A00
Sheet
1
of
103
SSID = CPU
Signal Routing Guideline:

PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
1 OF 9
CPU1A
(19) DMI_RXN[3:0]
(19) DMI_RXP[3:0]
(19) FDI_TXN[7:0]

EDP_ICOMPO keep W/S=12/15 mils and routing
length less than 500 mils.
EDP_COMPIO keep W/S=4/15 mils and routing
length less than 500 mils.
NOTE.
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
B28
B26
A24
B23
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
G21
E22
F21
D21
DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
G22
D22
F20
C21
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
(19) FDI_FSYNC0
(19) FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
(19) FDI_INT
H20
FDI_INT
(19) FDI_LSYNC0
(19) FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
A18
A17
B16
EDP_COMPIO
EDP_ICOMPO
EDP_HPD
C15
D15
EDP_AUX
EDP_AUX#
C17
F16
C16
G15
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
C18
E16
D16
F15
EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3
(19) FDI_TXP[7:0]
1D05V_VTT
DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
Note:
Intel FDI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
Note:
Lane reversal does not apply to
FDI sideband signals.
B27
B25
A25
B24
R402 1
2 24D9R2F-L-GP
DP_COMP
PCI EXPRESS* - GRAPHICS
(19) DMI_TXP[3:0]
SANDY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI
(19) DMI_TXN[3:0]
Intel(R) FDI
Note:
Intel DMI supports both Lane
Reversal and polarity inversion
but only at PCH side. This is
enabled via a soft strap.
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_IRCOMP_R
R401 1
2 24D9R2F-L-GP
NOTE.
If PEG is not implemented, the RX&TX pairs can be left as No Connect
SANDY
Stuff to disable internal graphics

function for power saving.
NOTE:
Select a Fast FET similar to 2N7002E whose rise/
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-k pull-Up
resistor on the motherboard.
<Core Design>
Wistron Corporation
Title
Size
CPU 1/7(PEG/DMI/FDI/eDP)
Document Number
Rev
Nirvana 13
Date:
Sheet
A00
4
of
103
SSID = CPU
2
2 OF 9
CPU1B
SKTOCC#_R
TP501
AN34
SKTOCC#
R501
TPAD14-GP
H_CATERR#
TP502
AL33
AN33
H_PECI
(27,40,42) H_PROCHOT#
H_PROCHOT#_R
AL32
PROCHOT#
56R2J-4-GP
Connect EC to PROCHOT# through inverting OD buffer.

(22,36) H_THERMTRIP#
AN32
AM34
(22,36) H_CPUPWRGD
H_CPUPWRGD_R
PM_SYNC
AP33
UNCOREPWRGOOD
0R0402-PAD
1
(19,37) PM_DRAM_PWRGD
R505 2 VDDPWRGOOD
0R2J-2-GP
V8
SM_DRAMPWROK
DY
(37) VDDPWRGOOD
BUF_CPU_RST#
1K5R2F-2-GP
AR33
RESET#
1 R510
(18,27,65,71,82) PLT_RST#
R509
750R2F-GP
DY
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
(20)
(20)
CLK_DP_P_R
CLK_DP_N_R
2
1
3
4
R8
AK1
A5
A4
2
4K99R2F-L-GP
SM_RCOMP_0 R506 1
SM_RCOMP_1 R507 1
SM_RCOMP_2 R508 1
1D05V_VTT
20110104 A00:
merge R512,R514 to RN502 1k array resistor.
20110113 A00:
Swap RN502 base on swap report.
SM_DRAMRST# (37)
2 140R2F-GP
2 25D5R2F-GP
2 200R2F-L-GP

SM_RCOMP keep routing length less than 500 mils.
THERMTRIP#
R504
A16
A15
1R502
H_CPUPWRGD_R
2
10KR2J-3-GP
(19) H_PM_SYNC
CLK_EXP_P
CLK_EXP_N
RN502
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
JTAG & BPM
1R503
PECI
R513
CRB : 47pf
CEKLT:43pf
A28
A27
CATERR#
THERMAL
(22,27)
20100622 V1.2
BCLK
BCLK#
SRN1KJ-7-GP
C502
SC47P50V2JN-3GP
62R2J-GP
H_PROCHOT#
PWR MANAGEMENT
CLOCKS
TPAD14-GP
SNB_IVB#
DDR3
MISC
1D05V_VTT
C26
H_SNB_IVB#
MISC
SANDY
(18)
1
Disabling Guidelines:
If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
through 1K +/- 5% resistorpower (~15 mW) may be
wasted.
PRDY#
PREQ#
AP29
AP27
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCLK
XDP_TMS
XDP_TRST#
AR28
AP26
XDP_TDI
XDP_TDO
DBR#
AL35
XDP_DBRESET#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
TDI
TDO
1D05V_VTT
RN501
XDP_TDI
XDP_TMS
XDP_TDO
XDP_TCLK
1
2
3
4
8
7
6
5
SRN51J-1-GP
XDP_TRST#
R511 1
2 51R2J-2-GP
C501
SC220P50V2KX-3GP
SANDY
3D3V_S0
XDP_DBRESET#
1
2 R516
10KR2J-3-GP
20100722 Modify:
Change R516 10K from 1K
XDP_DBRESET#
XDP_DBRESET# (19)
1D05V_VTT
DY R518
75R2J-1-GP
DY C503
SCD1U10V2KX-5GP
Buffered reset to CPU
2
3
IN A
DY
GND OUT Y
<Core Design>
4
BUFO_CPU_RST#
1
R517
2
DY 43R2J-GP
BUF_CPU_RST#
Wistron Corporation
(18,27,65,71,82) PLT_RST#
VCC
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

74VHC1G09DFT2G-GP
R515
DY0R2J-2-GP
73.01G09.AAH
Title
IN B
U501
1
3D3V_S0
Size
CPU 2/7(THERMAL/CLOCK/PM )
Document Number
Rev
Nirvana 13
Date: Tuesday, January 18, 2011
Sheet
A00
5
of
103
SSID = CPU
3 OF 9
SANDY
D
(14)
(14)
(14)
M_A_BS0
M_A_BS1
M_A_BS2
(14)
(14)
(14)
M_A_CAS#
M_A_RAS#
M_A_W E#
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AE10
AF10
V6
SA_BS0
SA_BS1
SA_BS2
AE8
AD9
AF9
DDR SYSTEM MEMORY A
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ[63:0]
(15) M_B_DQ[63:0]
M_A_DQ[63:0]
(14) M_A_DQ[63:0]
SA_CAS#
SA_RAS#
SA_WE#
4 OF 9
CPU1D
SA_CLK0
SA_CLK#0
SA_CKE0
AB6
AA6
V9
SA_CLK1
SA_CLK#1
SA_CKE1
AA5
AB5
V10
SA_CLK2
SA_CLK#2
SA_CKE2
AB4
AA4
W9
SA_CLK3
SA_CLK#3
SA_CKE3
AB3
AA3
W10
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
AK3
AL3
AG1
AH1
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
AH3
AG3
AG2
AH2
SANDY
M_A_DIM0_CLK_DDR0 (14)
M_A_DIM0_CLK_DDR#0 (14)
M_A_DIM0_CKE0 (14)
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_DIM0_CKE1 (14)
M_A_DIM0_CS#0 (14)
M_A_DIM0_CS#1 (14)
M_A_DIM0_ODT0 (14)
M_A_DIM0_ODT1 (14)
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
C4
G6
J3
M6
AL6
AM8
AR12
AM15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#[7:0] (14)
M_A_DQS[7:0] (14)
M_A_A[15:0] (14)
SANDY
(15)
(15)
(15)
M_B_BS0
M_B_BS1
M_B_BS2
(15)
(15)
(15)
M_B_CAS#
M_B_RAS#
M_B_W E#
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR SYSTEM MEMORY B
CPU1C
SB_CLK0
SB_CLK#0
SB_CKE0
AE2
AD2
R9
SB_CLK1
SB_CLK#1
SB_CKE1
AE1
AD1
R10
SB_CLK2
SB_CLK#2
SB_CKE2
AB2
AA2
T9
SB_CLK3
SB_CLK#3
SB_CKE3
AA1
AB1
T10
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
AD3
AE3
AD6
AE6
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
AE4
AD4
AD5
AE5
M_B_DIM0_CLK_DDR0 (15)
M_B_DIM0_CLK_DDR#0 (15)
M_B_DIM0_CKE0 (15)
M_B_DIM0_CKE1 (15)
M_B_DIM0_CS#0 (15)
M_B_DIM0_CS#1 (15)
M_B_DIM0_ODT0 (15)
M_B_DIM0_ODT1 (15)
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQS#[7:0] (15)
M_B_DQS[7:0] (15)
SB_BS0
SB_BS1
SB_BS2
SB_CAS#
SB_RAS#
SB_WE#
M_B_A[15:0] (15)
SANDY
<Core Design>
Wistron Corporation
Title
Size
Document Number
CPU 3/7(DDR)
Rev
Nirvana 13
Date:
5
Sheet
1
A00
6
of
103
SSID = CPU
CFG2
B4
D1
RSVD#B4
RSVD#D1
D1:VREF_DQ CHB
R711
R712
DY
2 0R2J-2-GP
M_VREF_CA_DIMM1
R706 1
DY
2 0R2J-2-GP
M_VREF_CA_DIMM0
R707 1
1KR2F-3-GP
1KR2F-3-GP
20 mils
R710 1
DY
2 0R2J-2-GP
H_VCCP_SEL
2
CFG4
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD#F25
RSVD#F24
RSVD#F23
RSVD#D24
RSVD#G25
RSVD#G24
RSVD#E23
RSVD#D23
RSVD#C30
RSVD#A31
RSVD#B30
RSVD#B29
RSVD#D30
RSVD#B31
RSVD#A30
RSVD#C29
J20
B18
A19
RSVD#J20
RSVD#B18
RSVD#A19
J15
RSVD#J15
Display Port Presence Strap
RSVD#AR35
RSVD#AT34
RSVD#AT33
RSVD#AP35
RSVD#AR34
AR35
AT34
AT33
AP35
AR34
DY
R704
DY DY
CFG7
AJ32
AK32
DY
RSVD#AH27
AH27
RSVD#AN35
RSVD#AM35
AN35
AM35
0: Enabled; An external Display Port device is

connected to the Embedded Display Port
PCIE Port Bifurcation Straps
CFG6
B34
A33
A34
B35
C35
RSVD#AJ32
RSVD#AK32
1: Disabled; No Physical Display Port

attached to Embedded Display Port
CFG5
R701
RSVD#B34
RSVD#A33
RSVD#A34
RSVD#B35
RSVD#C35
CFG4
T8
J16
H16
G16
RSVD#T8
RSVD#J16
RSVD#H16
RSVD#G16
R703
3K3R2F-2-GP
CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
M_VREF_DQ_DIMM0_C
M_VREF_DQ_DIMM1_C
2
2 0R2J-2-GP
B4:VREF_DQ CHA
0:Lane Reversed
1KR2J-1-GP
DY
RSVD#AJ26
AT26
AM33
AJ27
1: Normal Operation; Lane #

definition matches socket pin map definition
CFG2
1
R709 1
AJ26
RSVD#AT26
RSVD#AM33
RSVD#AJ27
PEG Static Lane Reversal

R702
1KR2J-1-GP
1KR2J-1-GP
M_VREF_DQ_DIMM0
M_VREF_DQ_DIMM1
RSVD#AJ31
RSVD#AH31
RSVD#AJ33
RSVD#AH33
L7
AG7
AE7
AK2
W8
PEG DEFER TRAINING
M3 - Processor Generated
SO-DIMM VREF_DQ
DY
R708
0R2J-2-GP
AJ31
AH31
AJ33
AH33
SANDY
RSVD#L7
RSVD#AG7
RSVD#AE7
RSVD#AK2
RSVD#W8
R705
1KR2J-1-GP
1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training
CFG7
CFG4
CFG5
CFG6
CFG7
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RESERVED
CFG2
D
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
5 OF 9
CPU1E
RSVD#AN35
RSVD#AM35
1
1
TP713
TP714
TPAD14-GP
TPAD14-GP
AT2
AT1
AR1
RSVD#AT2
RSVD#AT1
RSVD#AR1
SANDY
<Core Design>
Wistron Corporation
Title
Size
CPU 4/7(RESERVED)
Document Number
Nirvana 13
Date:
5
Rev
A00
Sheet
1
of
103
SSID = CPU
CPU1F
POWER
6 OF 9
VCCIO Output Decoupling Recommendation:

2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
7 x 22 uF & 2 x 0805 no-stuff at Top
SANDY
VCC_CORE
C841
SC10U6D3V5KX-1GP
1
2
C840
SC10U6D3V5KX-1GP
1
2
C839
SC4D7U6D3V5KX-3GP
1
2
C838
SC10U6D3V5KX-1GP
1
2
C810
SC10U6D3V5KX-1GP
1
2
DY
C809
SC10U6D3V5KX-1GP
DY
2
1
C808
SC10U6D3V3MX-GP
DY
2
1
C807
SC10U6D3V3MX-GP
2
1
C806
SC10U6D3V3MX-GP
2
1
C805
SC10U6D3V3MX-GP
DY
No-stuff sites outside the socket may be removed.

No-stuff sites inside the socket cavity need to remain.
1
2
C845
SC10U6D3V5KX-1GP
1
2
C844
SC10U6D3V5KX-1GP
1
2
C843
SC4D7U6D3V5KX-3GP
1
2
C842
SC10U6D3V5KX-1GP
1
2
C830
SC10U6D3V5KX-1GP
1
2
C829
SC4D7U6D3V5KX-3GP
1D05V_VTT
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
These resistors need to close to power IC.
SVID
1D05V_VTT
CORE SUPPLY
C827
SC22U6D3V5MX-2GP
2
1
2
C828
SC22U6D3V5MX-2GP
C826
SC10U6D3V5KX-1GP
2
1
2
VCCIO
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
R803
2 43R2J-GP
VR_SVID_ALERT#
R805
H_CPU_SVIDCLK
R806
H_CPU_SVIDDAT
R804
2 75R2J-1-GP
DY
2 54D9R2F-L1-GP
2 130R2F-1-GP
VR_SVID_ALERT# (42)
H_CPU_SVIDCLK (42)
H_CPU_SVIDDAT (42)
20101231 A00:
Merge R801,R802 to RN801 100 ohm array resistor.
20110113 A00:
Change RN801 to 100 ohm 1% (66.10156.04L).
20110113 A00:
RN801
2
1
VCC_CORE
SENSE LINES
Output Decoupling Recommendation:

470 uF at Bottom Socket Edge
22 uF at Top Socket Cavity
22 uF at Top Socket Edge
22 uF at Bottom Socket Cavity
C831
SC10U6D3V5KX-1GP
C825
SC22U6D3V5MX-2GP
2
1
2
C832
SC22U6D3V5MX-2GP
1
2
C811
SC22U6D3V5MX-2GP
C815
SC22U6D3V5MX-2GP
C824
SC22U6D3V5MX-2GP
2
1
2
C833
SC10U6D3V5KX-1GP
C804
SC10U6D3V5KX-1GP
2
1
C817
SC22U6D3V5MX-2GP
2
1
2
1
2
C823
SC22U6D3V5MX-2GP
DY
C834
SC10U6D3V5KX-1GP
C803
SC10U6D3V5KX-1GP
2
1
C818
SC10U6D3V5KX-1GP
2
1
2
1
2
C822
SC22U6D3V5MX-2GP
DY
C835
SC10U6D3V5KX-1GP
C802
SC10U6D3V5KX-1GP
2
1
C819
SC22U6D3V5MX-2GP
2
1
2
1
2
C821
SC4D7U6D3V5KX-3GP
VCC
4 x
8 x
8 x
8 x
C836
SC10U6D3V5KX-1GP
1
2
C801
SC10U6D3V5KX-1GP
1
2
1
2
1
2
DY
C837
SC22U6D3V5MX-2GP
DY
C816
SC22U6D3V5MX-2GP
C820
SC22U6D3V5MX-2GP
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
3
4
R1
53A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
R2
PROCESSOR CORE POWER

VCC_CORE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PEG AND DDR
1D05V_VTT
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
SRN100F-1-GP
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
AJ35
AJ34
B10
A10
VCCSENSE (42)
VSSSENSE (42)
VCCIO_SENSE (45)
VSSIO_SENSE (45)
SANDY
A
<Core Design>
Wistron Corporation
Title
Size
CPU 5/7(VCC_CORE)
Document Number
Rev
A00
Nirvana 13
Date:
5
Sheet
1
of
103
VAXG Output Decoupling Recommendation:

2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity
VCC_GFXCORE
CPU1G
1D8V_S0
C924
SC1U10V2KX-1GP
B6
A6
A2
VCCPLL
VCCPLL
VCCPLL
SENSE
LINES
AK35
AK34
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE (42)
VSS_AXG_SENSE (42)
2
1
3
4
VCC_GFXCORE
D
SRN100F-1-GP
Refer to the latest Huron River Mainstream PDG

(Doc# 436735) for more details on S3 power
reduction implementation.
+V_SM_VREF_CNT
SCD1U10V2KX-5GP
C919
1
SCD1U10V2KX-5GP
C925
1
DY
DY
DY
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C918
1
1
2
C914
SC10U6D3V5KX-1GP
TC901
2
1
C913
SC4D7U6D3V5KX-3GP
C912
SC10U6D3V5KX-1GP
1
C911
2
DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
C910
DY
2
DY
SC10U6D3V3MX-GP
PROCESSOR VDDQ: 10A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
1
C909
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR3 -1.5V RAILS
Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT 1D5V_S0
should have 10 mils trace width.
ST330U2VDM-4-GP
C907
1
+V_SM_VREF_CNT (37)
VREF
SM_VREF
AL1
1D5V_S3
79.33719.20L
2nd = 77.C3371.13L
VDDQ Output Decoupling Recommendation:

1 x 330 uF
6 x 10 uF
0D85V_S0
C917
SC10U6D3V5KX-1GP
1
2
C915
SC10U6D3V5KX-1GP
M27
M26
L26
J26
J25
J24
H26
H25
1
2
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
C916
SC10U6D3V5KX-1GP
PROCESSOR VCCSA: 6A
VCCSA Output Decoupling Recommendation:

1 x 330 uF
2 x 10 uF at Bottom Socket Cavity
VCCSA_SENSE
H23
VCCUSA_SENSE
FC_C22
VCCSA_VID1
C22
C24
H_FC_C22
VCCSA_SEL
VCCUSA_SENSE
H_FC_C22
VCCSA_SEL
SANDY
(48)
(48)
(48)
RN901
SRN1KJ-7-GP
3
4
C922
SC1U10V2KX-1GP
PROCESSOR VCCPLL: 1.2A
VAXG_SENSE
VSSAXG_SENSE
2
1
C923
SC10U6D3V5KX-1GP
7 OF 9
+V_SM_VREF_CNT should have 10 mil trace width
SA RAIL
Disabling Guidelines for External Graphics Designs:

Can connect to GND if motherboard only supports external
graphics and if GFX VR is not stuffed.
Can be left floating (Gfx VR keeps VAXG rail from floating)
if the VR is stuffed
SANDY
MISC
Removed DIS_ONLY Disable Resistor.

R904,R905,R901,R903
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
GRAPHICS
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.8V RAIL
SC10U6D3V3MX-GP
C906
SC4D7U6D3V5KX-3GP
1
C921
DY
2
SC10U6D3V3MX-GP
C905
SC22U6D3V5MX-2GP
1
C920
1
2
C903
SC4D7U6D3V5KX-3GP
C904
SC4D7U6D3V5KX-3GP
DY
2
DY
SC10U6D3V3MX-GP
C902
SC4D7U6D3V5KX-3GP
1
C908
1
2
C901
SC10U6D3V5KX-1GP
DY
20101231 A00:
20110113 A00:
Change RN801 to 100 ohm 1% (66.10156.04L).
20110113 A00:
RN902
PROCESSOR VAXG: 33A

D
POWER
R1
SSID = CPU
R2
VCCPLL Output Decoupling Recommendation:

1 x 330 uF
2 x 1 uF
1 x 10 uF
<Core Design>
Wistron Corporation
Title
Size
CPU 6/7(VCC_GFX_CORE)
Document Number
Nirvana 13
Date:
5
Rev
A00
Sheet
1
of
103
SSID = CPU
8 OF 9
CPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 9
CPU1I
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SANDY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
SANDY
<Core Design>
Wistron Corporation
Title
CPU 7/7(VSS)
Size
Document Number
Rev
Nirvana 13
Date:
5
Sheet
1
A00
10
of
103
(Blanking)
Remove the XDP connector for space saving 6/28
<Core Design>
Wistron Corporation
Title
XDP
Size
A3
Date:
5
Document Number
Rev
NIRVANA 13
Sheet
1
A00
11
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
Sheet
1
A00
12
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
13
of
103
SSID = MEMORY
DM1
1
2
DY
C1418
SC10U6D3V5KX-1GP
C1422
SC1U6D3V2KX-GP
DY
M_A_DQS#[7:0]
M_A_DQS[7:0]
(6)
(6)
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
116
120
(6) M_A_DIM0_ODT0
(6) M_A_DIM0_ODT1
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
ODT0
ODT1
126
1
VREF_CA
VREF_DQ
30
(15,37) DDR3_DRAMRST#
0D75V_S0
RESET#
203
204
VTT1
VTT2
H=9.2mm
1
2
4
3
Thermal EVENT
3D3V_S0
TS#_DIMM0_1 (15)
3D3V_S0
C1401
1D5V_S3
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
2
10KR2J-3-GP
C1402
1D5V_S3
SODIMM A DECOUPLING
Layout Note:
Place these Caps near
SO-DIMMA.
PART NUMBER
Height
62.10017.N61
9.2mm
C1410
SC10U6D3V5KX-1GP
DY
2
DY
2
DY
C1409
SC10U6D3V5KX-1GP
C1408
SC10U10V5ZY-1GP
1
2
DY
C1407
SC10U6D3V5KX-1GP
1
2
C1406
SC10U6D3V5KX-1GP
C1405
SC10U10V5ZY-1GP
2
1
79.33719.20L
2nd = 77.C3371.13L
DY
DY
2
DY
C1404
SC10U6D3V5KX-1GP
TC1401
C1417
SC1U6D3V2KX-GP
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
1R1403
DY
77
122
125
TS#_DIMM0_1
SA0_DIM0
SA1_DIM0
197
201
C1416
SC1U6D3V2KX-GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
If SA0 DIM0 = 1, SA1_DIM0 = 0

SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
199
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
PCH_SMBDATA (15,20,65,79,82)
PCH_SMBCLK (15,20,65,79,82)
198
12
29
47
64
137
154
171
188
NC#1
NC#2
NC#/TEST
200
202
C1403
SC10U6D3V5KX-1GP
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SA0
SA1
11
28
46
63
136
153
170
187
10
27
45
62
135
152
169
186
VDDSPD
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SDA
SCL
EVENT#
102
104
RN1401
20101231 A00:
0R4P2R-PAD
Merge R1401,R1402 to RN1401 10k ohm array resistor.
20100104 A00:
Change RN1401 to 0R short pad.
C1415
SC1U6D3V2KX-GP
1
2
1
2
C1421
SC1U6D3V2KX-GP
C1420
SC1U6D3V2KX-GP
DY
2
C1419
SC1U6D3V2KX-GP
C1413
Place these caps

close to VTT1 and
VTT2.
0D75V_S0
C1412
SCD1U10V2KX-5GP
1
2
DY
SC2D2U10V3KX-1GP
1
2
C
SCD1U10V2KX-5GP
C1411
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
(6)
(6)
101
103
M_VREF_DQ_DIMM0
20101224 A00:
0402 0R pad: R1404 R1405.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DIM0_CKE0
M_A_DIM0_CKE1
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SA1_DIM0
R1404
0R0402-PAD
BA0
BA1
73
74
SA0_DIM0
C1414
SC1U6D3V2KX-GP
DDR_VREF_S3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
(6)
(6)
ST330U2VDM-4-GP
109
108
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CK1
CK1#
M_A_DIM0_CS#0
M_A_DIM0_CS#1
(6)
M_A_BS0
(6)
M_A_BS1
(6) M_A_DQ[63:0]
CK0
CK0#
M_A_RAS# (6)
M_A_WE# (6)
M_A_CAS# (6)
114
121
M_A_BS2
CKE0
CKE1
110
113
115
(6)
CS0#
CS1#
NP1
NP2
1
C1424
2
C1425
SCD1U10V2KX-5GP
DY
2
SCD1U10V2KX-5GP
C1423
SC2D2U10V3KX-1GP
M_VREF_CA_DIMM0
NP1
NP2
RAS#
WE#
CAS#
SCD1U10V2KX-5GP
2
2
R1405
0R0402-PAD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
SC2D2U10V3KX-1GP
2
(6)
DDR_VREF_S3
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
RN
M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
TYPE
62.10017.F91
DDR3-204P-42-GP
62.10017.N61
<Core Design>
Wistron Corporation
Title
DDR3-DIMM1 SOCKET1
Size
Document Number
Rev
A00
Nirvana 13
Date:
5
Sheet
1
14
of
103
M_B_DQS#[7:0]
M_B_DQS[7:0]
(6)
(6)
116
120
(6) M_B_DIM0_ODT0
(6) M_B_DIM0_ODT1
126
1
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
30
(14,37) DDR3_DRAMRST#
203
204
0D75V_S0
102
104
1
R1501
10KR2J-3-GP
2
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
1
2
198
3D3V_S0
TS#_DIMM0_1 (14)
199
SA0_DIM1
SA1_DIM1
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
1D5V_S3
PART NUMBER
Height
62.10017.P41
5.2mm
C1510
SC10U6D3V5KX-1GP
DY
2
1
2
DY
C1509
SC10U6D3V5KX-1GP
C1508
SC10U10V5ZY-1GP
1
2
C1507
SC10U6D3V5KX-1GP
1
2
1
Layout Note:
Place these Caps near
SO-DIMMB.
DY
DY
C1506
SC10U6D3V5KX-1GP
SODIMM B DECOUPLING
C1514
SC1U6D3V2KX-GP
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
C1502
DY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1D5V_S3
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
C1501
C1505
SC10U6D3V5KX-1GP
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
77
122
125
197
201
NC#1
NC#2
NC#/TEST
20100104 A00:
Change R1502 to 0R0402 short pad.
PCH_SMBDATA (14,20,65,79,82)
PCH_SMBCLK (14,20,65,79,82)
C1513
SC1U6D3V2KX-GP
SA0
SA1
200
202
EVENT#
VDDSPD
SO-DIMMB is placed farther from

the Processor than SO-DIMMA
R1502
0R0402-PAD
SDA
SCL
SA0_DIM1
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SA1_DIM1
C1504
SC10U10V5ZY-1GP
12
29
47
64
137
154
171
188
101
103
3D3V_S0
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
(6)
(6)
10
27
45
62
135
152
169
186
(6)
(6)
M_B_DIM0_CKE0
M_B_DIM0_CKE1
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
CK1
CK1#
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_B_DIM0_CS#0
M_B_DIM0_CS#1
73
74
C1512
SC1U6D3V2KX-GP
1
2
C1521
SC1U6D3V2KX-GP
C1520
SC1U6D3V2KX-GP
DY
CK0
CK0#
M_B_RAS# (6)
M_B_WE# (6)
M_B_CAS# (6)
114
121
1
1
2
C1518
SC1U6D3V2KX-GP
DY
C1519
SC1U6D3V2KX-GP
Place these caps

close to VTT1 and
VTT2.
0D75V_S0
SCD1U10V2KX-5GP
1
2
C1517
SC2D2U10V3KX-1GP
1
2
SCD1U10V2KX-5GP
DY
C1516
CKE0
CKE1
110
113
115
C1503
SC10U10V5ZY-1GP
M_VREF_DQ_DIMM1
CS0#
CS1#
R1503
0R0402-PAD
C1515
NP1
NP2
20101224 A00:
0402 0R pad: R1503 R1504.
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
NP1
NP2
RAS#
WE#
CAS#
C1511
SCD1U10V2KX-5GP
1
2
SCD1U10V2KX-5GP
1
2
SCD1U10V2KX-5GP
C1522
SC2D2U10V3KX-1GP
M_VREF_CA_DIMM1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
2
R1504
0R0402-PAD
DDR_VREF_S3
SC2D2U10V3KX-1GP
109
108
DDR_VREF_S3
C1524
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
M_B_BS2
(6)
M_B_BS0
(6)
M_B_BS1
(6) M_B_DQ[63:0]
DY
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
(6)
(6)
SCD1U10V2KX-5GP
2
M_B_A[15:0]
C1523
DM2
SSID = MEMORY
TYPE
H=5.2mm
DDR3-204P-48-GP
62.10017.P41
<Core Design>
Wistron Corporation
Title
DDR3-DIMM2 SOCKET2
Size
Document Number
Rev
A00
Nirvana 13
Date:
5
Sheet
1
15
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
16
of
103
4 OF 10
PCH1D
(27) L_BKLT_EN
(49) LVDS_VDD_EN
RN1702
1
2
L_BKLT_EN
LVDS_VDD_EN
4
3
(49) L_BKLT_CTRL
L_DDC_DATA(PAGE17):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
used for the local flat panel display
L_BKLTEN
L_VDD_EN
P45
L_BKLTCTL
LVDS_DDC_CLK_R
T40
LVDS_DDC_DATA_R K47
(49,97) LVDS_DDC_CLK_R
(49,97) LVDS_DDC_DATA_R
L_CTRL_CLK
L_CTRL_DATA
20101224 A00:
Change RN1704 to 0402 0 ohm pad.
T45
P39
Cougar
Point
L_DDC_CLK
L_DDC_DATA
LVDS_IBG
LVDS_VBG
AF37
AF36
LVD_IBG
LVD_VBG
4
3
LVDS_VREFH
LVDS_VREFL
AE48
AE47
LVD_VREFH
LVD_VREFL
(49) LVDSA_CLK#
(49) LVDSA_CLK
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
(49) LVDSA_DATA0#
(49) LVDSA_DATA1#
(49) LVDSA_DATA2#
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
(49) LVDSA_DATA0
(49) LVDSA_DATA1
(49) LVDSA_DATA2
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
1
R1701
2K37R2F-GP
TP1701
RN1704
1
2
1
2
3
4
8
7
6
5
PCH_HDMI_DATA
PCH_HDMI_CLK
L_CTRL_DATA
L_CTRL_CLK
Impedance:90 ohm
SRN2K2J-2-GP
C
20100104 A00:
Merge RN1701,RN1706 to RN1703 2.2k array resistor.
Close to PCH side
5
6
7
8
CRT_GREEN
CRT_BLUE
CRT_RED
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
(50) CRT_DDC_CLK
(50) CRT_DDC_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
(50) CRT_HSYNC
(50) CRT_VSYNC
M47
M49
CRT_HSYNC
CRT_VSYNC
T43
T42
DAC_IREF
CRT_IRTN
4
3
2
1
RN1705
SRN150F-1-GP
(50) CRT_BLUE
(50) CRT_GREEN
(50) CRT_RED
DAC_IREF_R
SDVO_STALLN
SDVO_STALLP
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
DDI Port B Detect:(SDVO_CTRL_ DATA)

1: Port B detected
0: Port B not detected
LVDS
P38
M39
PCH_HDMI_CLK (51)
PCH_HDMI_DATA (51)
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
HDMI_PCH_DET
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
HDMI_DATA2_R# (51)
HDMI_DATA2_R (51)
HDMI_DATA1_R# (51)
HDMI_DATA1_R (51)
HDMI_DATA0_R# (51)
HDMI_DATA0_R (51)
HDMI_CLK_R# (51)
HDMI_CLK_R (51)
DDPC_CTRLCLK
DDPC_CTRLDATA
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
(51)
Impedance:100 ohm
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
COUGAR-GP-U2-NF
Notes:
1K 0.5% 0402.
R1702
1KR2D-1-GP
Digital Display Interface
RN1703
CRT
3D3V_S0
AP43
AP45
SDVO_CTRLCLK
SDVO_CTRLDATA
0R4P2R-PAD
Place near PCH
SDVO_TVCLKINN
SDVO_TVCLKINP
L_CTRL_CLK
L_CTRL_DATA
TPAD14-GP
RN
SRN100KJ-6-GP
J47
M45
<Core Design>
Wistron Corporation
Title
PCH 1/9(LVDS/CRT/DDI)
Size
Document Number
Rev
Nirvana 13
Date:
5
A00
Sheet
1
17
of
103
1D8V_S0
5 OF 10
R1801
DY
1 4K7R2J-2-GP PCI_GNT3#
A16 swap override Strap/Top-Block

Swap Override jumper
PCI_GNT#3
Low = A16 swap

override/Top-Block
Swap Override enabled
High = Default
1
2
4
3
SRN10KJ-5-GP
DY
DY
2R1802
1KR2J-1-GP
2R1803
1KR2J-1-GP
BBS_BIT1
BBS_BIT0
BBS_BIT0 (21)
BOOT BIOS Strap
LPC
Reserved
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
R1814
8K2R2J-3-GP
BOOT BIOS Location

1
GNT1#/GPIO51 SATA1GP/GPIO19
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
3D3V_S0
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
RN1803
DGPU_HOLD_RST#
DGPU_PW R_EN#
B21
M20
AY16
BG46
TPAD14-GP
TP1807
DGPU_HOLD_RST#
DGPU_SELECT#
DGPU_PW R_EN#
Reserved
BBS_BIT1
SPI(Default)
1DGPU_PW M_SELECT#
TPAD14-GP TP1801
TPAD14-GP TP1806
1
1
1
1
(79) HDD_FALL_INT1
(56) SATA_ODD_DA#
(82) USB30_SMI#
(69) KB_LED_BL_DET
R1812
R1813
R1815
R1817
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
PCI_GNT3#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
K40
K38
H38
G38
PIRQA#
PIRQB#
PIRQC#
PIRQD#
C46
C44
E40
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
D47
E42
F46
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
G42
G40
C42
D44
AT10
BC8
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD
DF_TVS
AV5
AY1
NV_ALE
NV_CLE
RSVD
AV10
NV_RCOMP
RSVD
AT8
RSVD
RSVD
AY5
BA2
RSVD
RSVD
AT12
BF3
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
20101231 A00:
20110113 A00:
2
1
3
4
TPAD14-GP
TP1802
PCI_PME#
PCI_PLTRST#
K10
C6
SRN22-3-GP
(65,71) CLK_PCI_LPC
R1805
1 22R2J-2-GP
2
CLK_PCI_LPC_R
CLK_PCI_FB_R
CLK_PCI_KBC_R
(20) CLK_PCI_FB
(27) CLK_PCI_KBC
H49
H43
J48
K42
H40
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(5,27,65,71,82) PLT_RST#
0R0402-PAD
PCI_PLTRST#
DY
SC4D7P50V2CN-1GP
R1807
SC4D7P50V2CN-1GP
DY
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
USBRBIAS
B33
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
Set to Vss when LOW
1D8V_S0
TP1803
Danbury Technology:
Disabled when Low.
Enable when High.
TPAD14-GP
R1810
1KR2J-1-GP
NV_ALE
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
USB_PN11
USB_PP11
USB_PN12
USB_PP12
USB_RBIAS
(57)
(57)
(64)
(64)
(63)
(63)
(82)
(82)
(32)
(32)
USB Table
(65)
(65)
(49)
(49)
Pair
1
2
R1811
22D6R2F-L1-GP
USB_OC#0_1
USB_OC#2_3
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
USB_OC#0_1 (61)
FFS_INT2_R (79)
KBC CLK EMI

OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
Device
B
E-SATA / USB Combo
Fingerprint
BLUETOOTH
Mini Card2 (WWAN)
CARD READER
10
11
Mini Card1 (WLAN)
12
CAMERA
13
<Core Design>
Wistron Corporation
R1818
DY
2
100KR2J-1-GP
DY
USB Ext. port 1 (HS)

External debug port use on Huron river platform
10KR2J-3-GP
FFS_INT2_R
USB_OC#2_3
C1801
SC220P50V2KX-3GP

RN1802
1
2
3
4
5
USB_OC#6_7
USB_OC#0_1
3D3V_S5
10
9
8
7
6
USB_OC#12_13
USB_OC#8_9
USB_OC#10_11
USB_OC#4_5
3D3V_S5
Title
PCH 2/9(PCI/USB/NVRAM)
Size
Document Number
Rev
Nirvana 13
SRN8K2J-2-GP-U
5
(5)
Set to Vcc when HIGH
COUGAR-GP-U2-NF
R1816
DY
H_SNB_IVB#
NV_CLE
EC1801 EC1802
20101224 A00:
0402 0R pad: R1807.
2
1KR2J-1-GP
DMI & FDI Termination Voltage
PME#
PLTRST#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
RN1804
R1809
NV_CLE
SRN8K2J-2-GP-U
RSVD
RSVD
INT_PIRQD#
INT_PIRQE#
INT_PIRQC#
INT_PIRQG#
AY7
AV7
AU3
BG4
NVRAM
3D3V_S0
3D3V_S0
USB
INT_PIRQB#
INT_PIRQF#
INT_PIRQA#
10
9
8
7
6
PCI
1
2
3
4
5
R1808
2K2R2J-2-GP
RSVD
RSVD
RSVD
RSVD
RSVD
RN1801
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
Cougar
Point
PCH1E
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
SSID = PCH
Date:
2
A00
Sheet
1
18
of
103
SSID = PCH
(4) DMI_RXN[3:0]
(4) DMI_RXP[3:0]
FDI_TXN[7:0] (4)
FDI_TXP[7:0] (4)
(4) DMI_TXN[3:0]
(4) DMI_TXP[3:0]
3 OF 10
PCH1C
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
(4)
(4)
(4)
(4)
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
(4)
(4)
(4)
(4)
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
(4)
(4)
(4)
(4)
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BJ24
DMI_ZCOMP
FDI_FSYNC0
1D05V_VTT
1 DY
2 R1926
10KR2J-3-GP
1
2 R1904
100KR2J-1-GP
FDI
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
FDI_INT
AW16
FDI_INT
AV12
FDI_FSYNC0
(4)
BG25
DMI_IRCOMP
FDI_FSYNC1
BC10
FDI_FSYNC1
(4)
R1902
2 750R2F-GP
BH21
DMI2RBIAS
FDI_LSYNC0
AV14
FDI_LSYNC0
(4)
FDI_LSYNC1
BB10
FDI_LSYNC1
(4)
DSWVRMEN
A18
DPWROK
E22
RBIAS_CPY
(4)
2 49D9R2F-GP DMI_COMP_R
For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
2.DPWROK and RSMRST# will rise at the same time (connected on board)
3.SLP_SUS# and SUSACK# are left as no connect
4.SUSWARN# used as SUSPWRDNACK/GPIO30
SYS_PW ROK
PW ROK
1
R1903
1
R1924
2
0R0402-PAD
SUSACK#
2
0R0402-PAD
C12
SYS_RESET#
2
K3
0R0402-PAD
2 R1905
10KR2J-3-GP
P12
1R1923
2
0R2J-2-GP
DY
PW ROK
L22
1
R1925
1
3D3V_S0
SYS_PW ROK
DY
1 R1907
(45,46,47) RUNPW ROK
DY
1 R1906
2
0R2J-2-GP
2 0R0402-PAD
MEPW ROK
L10
B13
(5,37) PM_DRAM_PW RGD
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

PM_RSMRST#
(27) SUS_PW R_ACK

(27) PM_PW RBTN#
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
(5) XDP_DBRESET#
(27,36) S0_PW R_GOOD
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
R1901
SUS_PW R_ACK
(36)
Cougar
Point
DMI

DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
(27) AC_PRESENT
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
System Power Management
(4)
(4)
(4)
(4)
B9
CLKRUN#/GPIO32
N3
SUS_STAT#/GPIO61
G8
PM_SUS_STAT#
SUSCLK/GPIO62
N14
SUS_CLK
SLP_S5#/GPIO63
D10
PM_SLP_S5#
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
PWRBTN#
H20
ACPRESENT/GPIO31
BATLOW #
E10
PM_RI#
A10
BATLOW#/GPIO72
RI#
PCH_DPW ROK
WAKE#
C21
E20
DSW ODVREN
SLP_S4#
H4
SLP_S3#
F4
2 0R0402-PAD PM_RSMRST#
2 10KR2J-3-GP
RTC_AUX_S5
PCH_W AKE# (27)
PM_CLKRUN# (27)
TP1901 TPAD14-GP
1 R1913
1
2 0R0402-PAD
PCH_SUSCLK_KBC
(27)
DSWODVREN - On Die DSW VR Enable
TP1902 TPAD14-GP
PM_SLP_S4# (27,46)
HIGH
Enabled (DEFAULT)
LOW
Disabled
PM_SLP_S3# (27,36,37,47)
SLP_A#
G10
PM_SLP_A#
SLP_SUS#
G16
PM_SLP_SUS#
PMSYNCH
AP14
H_PM_SYNC
K14
PM_SLP_LAN#
SLP_LAN#/GPIO29
1 R1910
R1911
DY1
1
1
TP1903TPAD14-GP
TP1904TPAD14-GP
H_PM_SYNC
RTC_AUX_S5
DSW ODVREN
R1917
R1918
2 330KR2J-L1-GP
DY
2 330KR2J-L1-GP
(5)
TP1905TPAD14-GP
COUGAR-GP-U2-NF
3D3V_S0
PM_RSMRST# 1 R1912 2
0R0402-PAD
RSMRST#_KBC (27)
PM_CLKRUN#
3D3V_S5
R1919
2 8K2R2J-3-GP
RN1901
BATLOW #
PM_RI#
PCH_W AKE#
SUS_PW R_ACK
PCH_SUSCLK_KBC
1
2
3
4
EC1901
SRN10KJ-6-GP
DY
R1921
2
1
100KR2J-1-GP
2 R1922
2 R1920
AC_PRESENT
110KR2J-3-GP PM_PW RBTN#

110KR2J-3-GP PM_SLP_LAN#
DY
DY
SC4D7P50V2CN-1GP
8
7
6
5
<Core Design>
Wistron Corporation
2 R1908 1
10KR2J-3-GP
PM_RSMRST#
Title
PCH 3/9(DM I/FDI/PM)

Size
Document Number
Rev
Nirvana 13
Date:
5
A00
Sheet
1
19
of
103
3D3V_S5
3D3V_S5
SSID = PCH
R2004
10KR2J-3-GP
PCIE_TXN2_C
PCIE_TXP2_C
BE34
BF34
BB32
AY32
PERN2
PERP2
PETN2
PETP2
PCIE_TXN3_C
PCIE_TXP3_C
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
USB3.0
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
Intel GBE LAN
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
LAN CLK(82)
USB3.0 CLK
CLK_PCH_SRC3_N
CLK_PCH_SRC3_P
1 RN2013 4
2
3
0R4P2R-PAD
(82) CLK_PCIE_USB3#
(82) CLK_PCIE_USB3
CLK_PCH_SRC4_N
CLK_PCH_SRC4_P
(82) USB3_PEGB_CLKREQ#
PCIE_CLK_REQ5#
RN2018
PCIE_CLK_RQ2#
CLK_PCIE_W LAN_REQ#
4
3
PEG_B_CLKRQ#
SRN10KJ-5-GP
PCIECLKRQ1# and PCIECLKRQ2#

Support S0 power only
PCIE_CLK_REQ6#
Y37
Y36
TP2005
TP2006
Dock
NEW CARD
SMBUS
2
1
1
1
ITPXDP_N
ITPXDP_P
M16
SML1_DATA
2nd = 84.DM601.03F
84.2N702.A3F
2N7002KDW -GP
SML1_CLK (27)
M7
CL_CLK
CL_DATA1
T11
CL_DATA 1
CL_RST1#
P10
CL_RST# 1
SMB_DATA
SML1_DATA (27)
PCH_SMBDATA (14,15,65,79,82)
3
Q2001
TP2001 TPAD14-GP
PCH_SMBCLK (14,15,65,79,82)
TP2002 TPAD14-GP
SMB_CLK
C
TP2003 TPAD14-GP
20110112 A00:
Change C2007,C2008 to 15pF from 12pF base on vendor's report.
M10
PEG_CLKREQ#_R
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
AB37
AB38
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
BF18
BE18
CLKIN_DMI_N
CLKIN_DMI_P
SC15P50V2JN-2-GP
TP2007 TPAD14-GP
1
1
TP2008 TPAD14-GP
TP2009 TPAD14-GP
2 RN2010 3
1
4
0R4P2R-PAD
PCIECLKRQ4#/GPIO26
V45
V46
CLKOUT_PCIE5N
CLKOUT_PCIE5P
L14
PCIECLKRQ5#/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_OUT
CLK_EXP_N (5)
CLK_EXP_P (5)
G24
E24
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLKIN_SATA_N
CLKIN_SATA_P
AK7
AK5
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
REFCLK14IN
K45
CLK_BUF_REF14
XCLK_RCOMP
V40
V42
CLKOUT_PCIE6N
CLKOUT_PCIE6P
T13
PCIECLKRQ6#/GPIO45
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
C2007
2
1
XTAL-25MHZ-155-GP
SC15P50V2JN-2-GP
2nd = 82.30020.G71
3rd = 82.30020.G61
2
1
R2012
3
4
SRN10KJ-5-GP
PL 10K FOR Integrated CLOCK GEN mode.

RN2020
CLK_BUF_DOT96_N 1
CLK_BUF_DOT96_P 2
SRN10KJ-5-GP
4
3
CLK_PCI_FB
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
R2007
XCLK_RCOMP
1
2
90D9R2F-1-GP
CLK_PCI_FB
CLK_BUF_CKSSCD_N 2
(18) CLK_BUF_CKSSCD_P 1
CLK_BUF_EXP_N
CLK_BUF_EXP_P
3
4
UMA_DISCRETE#
UMA: 1 1
DIS :0 1
SG(PX) : 0 0
ATI(Muxless) : 1 0
R2013
R2010
DY
RN2021
H45
PEG_B_CLKRQ#/GPIO56
R2006
1M1R2J-GP
2
82.30020.D41
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLKIN_DOT_96N
CLKIN_DOT_96P
XTAL25_IN
XTAL25_OUT
3D3V_S0 3D3V_S0
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
CLKIN_PCILOOPBACK
20101224 A00:
BJ30
BG30
CLKIN_GND1_N
CLKIN_GND1_P
UMA_DIS#
DGPU_PRSNT#
3D3V_S5
1
2
3
4
R2008
need very close to PCH

K43
CLKOUTFLEX1/GPIO65
F47
CLKOUTFLEX2/GPIO66
H47
CLKOUTFLEX3/GPIO67
K49 DGPU_PRSNT#
CLK_48_USB30
1 R2016 2
22R2J-2-GP
CLK_PCH_48M (32,97)
RN2001
1
2
3
4
SRN10KJ-5-GP
RN2019
SRN10KJ-5-GP
1
4
2
3
+VCCDIFFCLKN
CLK_BUF_REF14
UMA_DIS# (22)
R2011
DY
10KR2J-3-GP
CLKOUTFLEX0/GPIO64
C2008
1
X2001
CLKOUT_PCIE4N
CLKOUT_PCIE4P
AK14
AK13
3
4
XTAL25_IN
L12
E6
4 RN2006
3 SRN10KJ-5-GP
2
E14
SML1DATA/GPIO75
PCIECLKRQ3#/GPIO25
Y43
Y45
1
2
DRAMRST_CNTRL_PCH 1 R2009 2
1KR2J-1-GP
3D3V_S0
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLK_PCIE_NEW _REQ# K12

TPAD14-GP
TPAD14-GP
SML1CLK/GPIO58
SML1_CLK
CL_CLK1
PCIECLKRQ2#/GPIO20
AB42
AB40
3D3V_S0
1
2
PCH_GPIO74
CLKOUT_PCIE2N
CLKOUT_PCIE2P
A8
RN
(82) PCIE_CLK_LAN_REQ#
(37)
RN2008
1 RN2014 4
2
3
0R4P2R-PAD
(82) CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_CLK_REQ6#
PCH_GPIO74
RN2007
C13
SML1ALERT#/PCHHOT#/GPIO74
PCIECLKRQ1#/GPIO18
V10
3 RN2005
4 SRN2K2J-1-GP
RN
RN
PCIE_CLK_RQ2#
WLAN
CLKOUT_PCIE1N
CLKOUT_PCIE1P
AA48
AA47
2
1
SRN2K2J-1-GP
PCIECLKRQ0#/GPIO73
M1
(65) CLK_PCIE_W LAN_REQ#
SML0DATA
DRAMRST_CNTRL_PCH
WLAN CLK
SML0CLK
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLK_PCH_SRC1_N AB49
CLK_PCH_SRC1_P AB47
2 RN2004
1 SRN2K2J-1-GP
10KR2J-3-GP
1 RN2012 4
2
3
0R4P2R-PAD
(65) CLK_PCIE_W LAN#

(65) CLK_PCIE_W LAN
Card Reader
PEG_A_CLKRQ#/GPIO47
Y40
Y39
J2
RN
RN
(82) CLK_PCIE_W W AN_REQ#
CLK_PCH_SRC0_N
CLK_PCH_SRC0_P
SML0_DATA
3
4
SML1_CLK
SML1_DATA
2 RN2011 3
1
4
0R4P2R-PAD
(82) CLK_PCIE_W W AN#

CLK_PCIE_W W AN
WWAN CLK(82)
SML0_CLK
G12
SML0_DATA
SML0_CLK
20101224 A00:
Change RN2011~RN2014 to 0402 0 ohm pad.
C8
1 RN2003
2 SRN2K2J-1-GP
DRAMRST_CNTRL_PCH
R2005
10KR2J-3-GP
2
10KR2J-3-GP
PCIE_TXN5_C
PCIE_TXP5_C
A12
DY
4
3
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
SMB_DATA
10KR2J-3-GP
2
1
1
SMB_CLK
C9
2
10KR2J-3-GP
PCIE_TXN4_C
PCIE_TXP4_C
H14
C2009
C2010
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
SMBCLK
EC_SW I# (27)
(82) PCIE_RXN5
(82) PCIE_RXP5
(82) PCIE_TXN5
(82) PCIE_TXP5
1
1
PERN3
PERP3
PETN3
PETP3
Link
C2005
C2006
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
EC_SW I#
SML0ALERT#/GPIO60
FLEX CLOCKS
(65) PCIE_RXN4
(65) PCIE_RXP4
(65) PCIE_TXN4
(65) PCIE_TXP4
1
1
LAN
Controller
C2011
C2012
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
E12
SMBDATA
CLOCKS
(82) PCIE_RXN3
(82) PCIE_RXP3
(82) PCIE_TXN3
(82) PCIE_TXP3
1
1
SMBALERT#/GPIO11
PERN1
PERP1
PETN1
PETP1
PCI-E*
C2001
C2002
PEG_CLKREQ#_R
BG34
BJ34
AV32
AU32
D
(82) PCIE_RXN2
(82) PCIE_RXP2
(82) PCIE_TXN2
(82) PCIE_TXP2
Cougar
Point
W-WAN
2 OF 10
PCH1B
SMB_CLK
SMB_DATA
8
7
6
5
CLK_PCIE_W W AN_REQ#
PCIE_CLK_LAN_REQ#
USB3_PEGB_CLKREQ#
SRN10KJ-6-GP
RN2002
8 EC_SW I#
7 PCIE_CLK_REQ5#
6 CLK_PCIE_NEW _REQ#
5 PEG_B_CLKRQ#
SRN10KJ-6-GP
<Core Design>
For RTS5138
Wistron Corporation
COUGAR-GP-U2-NF
Title
Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3

Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
if more than 2 PCI clocks + PCI loopback are routed.
PCH 4/9(PCI-E/SMBUS/CLOCK/CL)
Size
Rev
Nirvana 13
Date:
Document Number
A00
Sheet
1
20
of
103
SSID = PCH
20110110 A00:
Merge R2115,R2116 to RN2101.
RTC_AUX_S5
RN2101
2
1
SRN20KJ-1-GP
RTC_X2
2
10MR2J-L-GP
X-32D768KHZ-67-GP
A20
RTCX1
RTC_X2
C20
RTCX2
RTC_RST#
D20
82.30001.A81
2nd = 82.30001.691
C2104
SC1U6D3V2KX-GP
RTCRST#
1M1R2J-GP
R2104
2
1
SRTC_RST#
G22
SRTCRST#
SM_INTRUDER#
K22
INTRUDER#
PCH_INTVRMEN
C17
INTVRMEN
HDA_BITCLK
N34
HDA_BCLK
HDA_SYNC
L34
HDA_SYNC
T10
SPKR
HDA_RST#
K34
HDA_RST#
GAP-OPEN
RTC_AUX_S5
3rd = 82.30001.861
G2101
Cougar
Point
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
C38
A38
B37
C37
FWH4/LFRAME#
D36
LDRQ0#
LDRQ1#/GPIO23
E36
K36
LPC
C2102
SC15P50V2JN-2-GP
RTC_X1
C2101
SC15P50V2JN-2-GP
2
1
SERIRQ
(29) HDA_SPKR
RN2102
1
2
(29) HDA_CODEC_RST#
(29) HDA_CODEC_BITCLK
HDA_RST#
HDA_BITCLK
4
3
SRN33J-5-GP-U
(29) HDA_SDIN0
Notes:
ME_UNLOCK (HDA_SDO) connect to EC.
Make sure EC drive this pin "low" all the time.
Flash Descriptor Security Overide

HDA_SDOUT
+3VS_+1.5VS_HDA_IO
21KR2J-1-GP
(49)
CE
20100721 Modify:
Remove TP2105 and change PCH_GPIO33 to CE.
No Reboot Strap
DY1
R2106
21KR2J-1-GP HDA_SPKR
Low = Default
HDA_SPKR High = No Reboot
+3VS_+1.5VS_HDA_IO
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN#/GPIO33
N32
HDA_DOCK_RST#/GPIO13
2 1KR2J-1-GP
HDA_SYNC
This signal has a weak internal pull down.

On Die PLL VR is supplied by 1.5V when
sampled high, 1.8 V when sampled low.
Needs to be pulled High for Huron River platform.
co-operate with R2310
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4
(56)
(56)
(56)
(56)
ODD
Y3
Y1
AB3
AB1
SATA_RXN5
SATA_RXP5
SATA_TXN5
SATA_TXP5
(57)
(57)
(57)
(57)
ESATA
J3
JTAG_TCK
TPAD14-GP
TP2102
PCH_JTAG_TMS
H7
JTAG_TMS
SATAICOMPO
Y11
TPAD14-GP
TP2103
PCH_JTAG_TDI
K5
JTAG_TDI
SATAICOMPI
Y10
TPAD14-GP
TP2104
PCH_JTAG_TDO
H1
JTAG_TDO
1
R2110
(27,60) SPI_SI_R
T3
2 PCH_SPI_SI
33R2J-2-GP
(27,60) SPI_SO_R
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
(56)
(56)
(56)
(56)
HDD1
HDD2
1D05V_VTT
SATA_COMP
R2112
2 37D4R2F-GP
1D05V_VTT
SPI_CLK
SPI_CS0#
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
PCH_JTAG_TCK_BUF
Y14
(27)
AM3
AM1
AP7
AP5
2 PCH_SPI_CLK
33R2J-2-GP
2 PCH_SPI_CS0#
33R2J-2-GP
KB_DET# (69)
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
TP2101
1
R2108
1
R2109
(27,65,71)
LPC_FRAME# (27,65,71)
INT_SERIRQ
TPAD14-GP
(27,60) SPI_CS0#_R
LPC_AD[0..3]
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
V5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
(27,60) SPI_CLK_R
1 R2103
C34
HDA_SDOUT
NO REBOOT STRAP
3D3V_S0
HDA_SDIN1
JTAG
1 R2102
CE
HDA_SDIN0
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3_COMP R2113
2 49D9R2F-GP
SATA3RBIAS
AH1
RBIAS_SATA3 R2114
2 750R2F-GP
B
SPI
DY
HDA_SDOUT
2 1KR2J-1-GP
1 R2107
(27) ME_UNLOCK
Low = Default
High = Enable
E34
G34
SATA
1R2122 HDA_SYNC
1R2123 HDA_SDOUT
DY
IHDA
33R2J-2-GP2
33R2J-2-GP2
SATA 6G
R2105
330KR2F-L-GP
(29) HDA_CODEC_SYNC
(29) HDA_CODEC_SDOUT
LPC_AD[0..3]
1 OF 10
PCH1A
X2101
RTC
C2103
SC1U6D3V2KX-GP
R2101
INTVRMEN- Integrated SUS

1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs
3
4
1
RTC_X1
SATALED#
P3
SATA_LED# (68)
SATA0GP/GPIO21
V14
SATA_DET#0
SATA1GP/GPIO19
P1
BBS_BIT0
BBS_BIT0 (18)
COUGAR-GP-U2-NF
PLL ODVR VOLTAGE
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.
Low = 1.8V (Default)

HDA_SYNC High = 1.5V
3D3V_S0
RUN_ENABLE
2N7002K-2-GP
RN2103
R2124
HDA_SYNC_R 2
1 HDA_SYNC
(22)
33R2J-2-GP
HDA_CODEC_BITCLK
HDA_CODEC_SDOUT
S_GPIO
SPI_CS0#_R
1
2
3
4
(22)
(22)
EC2101
DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
EC2103
DY
SC4D7P50V2CN-1GP
2
EC2102
DY
1
Q2101
R2117
84.2N702.J31
100KR2J-1-GP
2ND = 84.2N702.031
HDA_CODEC_SYNCS
A
SATA_DET#0
INT_SERIRQ
FP_DET#
PSW _CLR#
4
3
8
7
6
5
SRN10KJ-6-GP
RN2104
1
2
<Core Design>
Wistron Corporation
SRN10KJ-5-GP
Title
PCH 5/9(SPI/RTC/LPC/SATA/IHDA)
Size
Document Number
Rev
Nirvana 13
Date:
A00
Sheet
1
21
of
103
SSID = PCH
3D3V_S0
R2202
SATA_ODD_PRSNT#
GSENSOR_ADI
Note:
For PCH debug with XDP, need to NO STUFF R2218
6 OF 10
PCH1F
100KR2J-1-GP
RTC_DET#
3D3V_S0
PCH_TEMP_ALERT#1
R2223
TACH3/GPIO7
TACH7/GPIO71
A40 VRAM_SIZE2
TP2205 TPAD14-GP
C10
GPIO8
C4
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
U2
3G_EN
3G_EN
E8
GPIO24/MEM_LED
TP2203
PCH_GPIO27
PSW _CLR#
(21)
G2201
GPIO28
K1
STP_PCI#/GPIO34
SATA2GP/GPIO36
FDI_OVRVLTG
M5
SATA3GP/GPIO37
MFG_MODE
N2
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
SDATAOUT1/GPIO48
PCH_TEMP_ALERT#
PCH_GPIO57
RCIN#
UMA_DIS# (20)
SATA5GP/GPIO49
D6
GPIO57
A4
NCTF_VSS#A4
A44
NCTF_VSS#A44
A45
NCTF_VSS#A45
A46
NCTF_VSS#A46
A5
NCTF_VSS#A5
A6
NCTF_VSS#A6
B3
NCTF_VSS#B3
B47
NCTF_VSS#B47
BD1
NCTF_VSS#BD1
H_PECI_R
P5
H_RCIN#
AY11
AY10
PCH_THERMTRIP_R
INIT3_3V#
T14
INIT3_3V#
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
BG2
NCTF_VSS#BG48
BG48
NCTF_VSS#BH3
BH3
NCTF_VSS#BH47
BH47
NCTF_VSS#BJ4
BJ4
NCTF_VSS#BJ44
BJ44
NCTF_VSS#BJ45
BJ45
NCTF_VSS#BJ46
BJ46
NCTF_VSS#BJ5
BJ5
NCTF_VSS#BJ6
BJ6
NCTF_VSS#C2
C2
2
10KR2J-3-GP
NCTF_VSS#C48
C48
NCTF_VSS#D1
D1
BD49
NCTF_VSS#D49
D49
NCTF_VSS#BD49
TPAD14-GP
TP2207
PCH_NCTF_2
BE1
NCTF_VSS#BE1
TPAD14-GP
TP2208
PCH_NCTF_3
BE49
NCTF_VSS#BE49
BF1
NCTF_VSS#BF1
TPAD14-GP
TP2209
PCH_NCTF_4
BF49
NCTF_VSS#BF49
COUGAR-GP-U2-NF
2
0R2J-2-GP
H_PECI
(5,27)
GSENSOR_DET
GSENSOR_ADI
(27)
(5,36)
2 390R2J-1-GP
R2206
100KR2J-1-GP
H_THERMTRIP# (5,36)
TP2201 TPAD14-GP
2
0R0402-PAD
TS Signal Disable Guideline:

TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
should not float on the motherboard. They should
be tied to GND directly.
C
3D3V_S0
FDI TERMINATION VOLTAGE OVERRIDE

R2207
10KR2J-3-GP
DY
GPIO37
(FDI_OVRVLTG)
LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)
FDI_OVRVLTG
R2208
10KR2J-3-GP
DMI TERMINATION VOLTAGE OVERRIDE
3D3V_S0
GPIO36
(DMI_OVRVLTG)
LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)
3G_EN
B
R2204
AK10 TS_VSS 1
R2219
P37
NCTF_VSS#BG2
R2203
H_CPUPW RGD
R2209
10KR2J-3-GP
DY
NCTF_VSS#E1
E1
NCTF_VSS#E49
E49
R2221
DY1
DMI_OVRVLTG
2
1KR2J-1-GP
NCTF_VSS#F1
F1
NCTF_VSS#F49
F49
Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock
enable.
R2210
10KR2J-3-GP
Integrated Clock Chip Enable

2
1 R2201
NCTF
PCH_GPIO15
D1,D49,E1,E49,F1,F49
1
2
SRN10KJ-5-GP
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
4
3
NCTF TEST PIN:
RTC_DET#
PCH_GPIO57
3D3V_S0
H_A20GATE (27)
AU16
THRMTRIP#
NC_1
V3
P4
PROCPWRGD
TS_VSS4
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
RN2204
DY
SATA_ODD_PW RGT (56)
PCH_NCTF_1
PECI
GPIO35
V8
PCH_GPIO48
TP2206
GPIO27
P8
DMI_OVRVLTG
GSENSOR_DET
TPAD14-GP
E16
K4
FP_DET#
SRN10KJ-6-GP
R2214
10KR2J-3-GP
1
DY 2
3D3V_S5
TACH0/GPIO17
(82)
8
7
6
5
SATA4GP/GPIO16
SCLOCK/GPIO22
10KR2J-3-GP
A20GATE
T5
TPAD14-GP
10K
R2205
GSENSOR_ST 10KR2J-3-GP
DBC_EN
GAP-OPEN
DBC_EN
TP2204 TPAD14-GP
E38
DBC_EN
(21) PSW _CLR#
RN2201
EC_SMI#
G2
10KR2J-3-GP
1
2
3
4
C41 VRAM_SIZE1
(49)
R2222
EC_SCI#
DGPU_HPD_INTR#
TACH6/GPIO70
PCH_GPIO15
PLL_ODVR_EN
TACH2/GPIO6
D40
1R2220
2 PCH_GPIO48
10KR2J-3-GP
MFG_MODE
B41 UMA_DIS#
RTC_DET#
2 PCH_GPIO16
0R0402-PAD
1
R2213
(56) SATA_ODD_PRSNT#
3D3V_S0
ICC_EN#
TACH5/GPIO69
100K
(60)
EC_SCI#
C40
R2206
GSENSOR_ST
SRN10KJ-5-GP
GPIO27 has a weak[20K] internal pull up.

To enable on-die PLL Voltage regurator,
should not place external pull down.
TACH1/GPIO1
H36
TACH4/GPIO68
Cougar
Point
BMBUSY#/GPIO0
DY
(27) EC_SCI#
A42
DGPU_HPD_INTR#
T7
H_A20GATE
H_RCIN#
4
3
GPIO0
2
100R2J-2-GP
EC_SMI#
CPU/MISC
1 R2218
(27) EC_SMI#
RN2203
1
2
S_GPIO
S_GPIO
GPIO
(21)
3D3V_S0
R2205
ICC_EN#
HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)-
ICC_EN#1 R2211
2
1KR2J-1-GP
ENABLED
GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock
enable.
[VRAM_SIZE1:VRAM_SIZE2]
LL=512M / HL=1G / LH=2G
<Core Design>
PLL ON DIE VR ENABLE
Wistron Corporation
NOTE:This signal has a weak internal pull-up 20K

ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)

Title
PLL_ODVR_EN
PCH 6/9(GPIO/CPU)
DY 1 R2212 2
1KR2J-1-GP
Size
Document Number
Rev
Nirvana 13
Date:
5
A00
Sheet
1
22
of
103
6A
AN17
VCCIO
AN27
VCCIO
AP21
VCCIO
AP23
VCCIO
AP24
VCCIO
AP26
VCCIO
AT24
VCCIO
VCC3_3
V33
VCC3_3
V34
VCCIO
AN34
VCCIO
BH29
VCC3_3
C2310
SCD1U10V2KX-5GP
AT16
VCCDMI
AT20
VCCCLKDMI
VCCFDIPLL
BG6
VCCAFDIPLL
1
2
1
1
2
C2318
(0.01uF x2)
(22uF x1)
SC10U6D3V5KX-1GP
20101224 A00:
0402 0R pad: R2301,R2306,R2307,R2308.
AB36
VccDFTERM
AG16
VccDFTERM
AG17
VccDFTERM
AJ16
VccDFTERM
AJ17
1D5V_S0
R2308
1
1D05V_VTT
0R0402-PAD
(1uF x1)
0R0402-PAD
C2320
SC1U6D3V2KX-GP
0.02A
1D05V_VTT
R2307
0R0402-PAD
C2321
SC1U6D3V2KX-GP
(1uFx1)
(10uFx1)
1D8V_S0
0.19A
0.19A
C2322
SCD1U10V2KX-5GP
(0.1uFx1)
TP2302
1 R2305 2
0R0805-PAD
2
R2306
+1.05VS_VCC_DMI
0.02A
+1.05VS_VCC_DMI
AP17
VCCIO
AU20
VCCDMI
0.042A (Totally current of VCCDMI)
VCCSPI
V1
3D3V_S5
0.02A
0.02A
1
1D05V_VTT
FDI
TPAD14-GP
VCCVRM
0.042A
VCCVRM
1 R2304 2
0R0603-PAD
1
VCCVRM
2
AP16
1D5V_S0
VCCVRM(Internal PLL and VRMs):

A.1.5V for Mobile
B.1.8 V for Desktop
C2319
SCD1U10V2KX-5GP
0.16A
0.159A(Totally current of VCCVRM)

B
3D3V_S0
0.001A
3D3V_S0
NAND / SPI
(0.1uF x1)
3rd = 68.00335.081
AN33
3D3V_S0
68.00214.051
2nd = 68.00206.041
(0.1uFx1)
0.266A
+1.05VS_VCC_DMI_CCI
0.266A (Totally VCC3_3 current)
AP37
0.06A
AP36
VCCTX_LVDS
SCD1U10V2KX-5GP
VCCTX_LVDS
C2315
1D8V_S0
0.06A
+1.8VS_VCCTX_LVDS
AM38
CRT
2
AM37
VCCTX_LVDS
VCCIO
VCCTX_LVDS
L2301
DY 2
HCB1608KF-181-GP
SC10U6D3V5KX-1GP
VCCIO
AN26
AK37
C2314
C2316
SCD01U16V2KX-3GP
VCCAPLLEXP
VCCIO
VSSALVDS
+3VS_VCCA_LVDS
3D3V_S0
BJ22
AN16
AN21
AK36
R2301
0R0402-PAD
1
2
C2309
SC1U6D3V2KX-GP
C2308
SC1U6D3V2KX-GP
1
2
C2307
SC1U6D3V2KX-GP
C2306
SC1U6D3V2KX-GP
1
2
C2305
SC10U6D3V5KX-1GP
(1uF x4)
C
VCCALVDS
VCCAPLLEXP
(10uF x1)
HVCMOS
VSSADAC
U47
+VCCA_DAC_1_2
C2313
DMI
TP2301
2.925A(Total current of VCCIO)
U48
0.001A
VCCIO
TPAD14-GP
1D05V_VTT
VCCIO
VCCADAC
Cougar
Point
1D05V_VTT
AN19
(0.1uF/0.01uF x1)
(10uF x1_0603)
0.001A
LVDS
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCC CORE
1
2
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
C2304
SC1U6D3V2KX-GP
C2303
SC1U6D3V2KX-GP
1
2
C2302
SC1U6D3V2KX-GP
1
2
C2301
SC10U6D3V5KX-1GP
1.3A
7 OF 10
SCD01U16V2KX-3GP
POWER
PCH1G
1D05V_VTT
(1uFx3)
(10uFx1_0603)
3D3V_DAC_S0
20101228 A00:
0402 0R pad: R2301.
C2317
SCD01U16V2KX-3GP
SSID = PCH
COUGAR-GP-U2-NF
(1uFx1)
C2323
SC1U6D3V2KX-GP
3.3V CRT LDO

5V_S5
3D3V_DAC_S0
3D3V_S0
U2301
VOUT
NC#4
74.09091.J3F
2nd = 74.09198.G7F
3rd = 74.07716.A7F
<Core Design>
C2312
G9091-330T11U-GP
SC1U10V2KX-1GP
C2311
SC1U6D3V2KX-GP
Current Limit=360mA
VIN
GND
EN
1
2
3
Wistron Corporation
Title
PCH 7/9(POWER1)
Size
Document Number
Rev
Nirvana 13
Date:
5
A00
Sheet
1
23
of
103
AA19
C2412
SC1U6D3V2KX-GP
1D05V_VTT
1
2
C2408
SC1U6D3V2KX-GP
C2407
SC1U6D3V2KX-GP
AA26
VCCASW
AA27
VCCASW
AA29
VCCASW
AA31
VCCASW
AC26
VCCASW
AC27
VCCASW
AC29
VCCASW
AC31
VCCASW
AD29
VCCASW
AD31
VCCASW
W21
VCCASW
W23
VCCASW
W24
VCCASW
W26
VCCASW
W29
VCCASW
W31
VCCASW
W33
VCCASW
M26
+5VA_PCH_VCC5REFSUS
DCPSUS
AN23
+VCCA_USBSUS
VCCSUS3_3
AN24
V5REF_SUS
1D05V_VTT
C2414
SC1U6D3V2KX-GP
AF17
AF33
AF34
AG34
0.095A
+V1.05S_SSCVCC
SCD1U10V2KX-5GP(1uFx1)
C2415
2
1 +VCCSST
VCCVRM
VCCADPLLA
VCCADPLLB
VCCIO
VCCDIFFCLKN
VCCDIFFCLKN
VCCDIFFCLKN
VCCSSC
V16
DCPSST
TP2403
V5REF
P34
VCCSUS3_3
N20
VCCSUS3_3
N22
VCCSUS3_3
P20
T17
V19
DCPSUS
DCPSUS
2
4
2
1
D2402
CH751H-40PT-GP
VCCSUS3_3
P22
VCC3_3
AA16
VCC3_3
W16
VCC3_3
T34
VCC3_3
AJ2
83.R0304.A8F
2nd = 83.R2004.B8F
0.001A
+5VS_PCH_VCC5REF
R2407
1
3D3V_S5
(1uFx1)
(1uFx1)
10R2J-2-GP
C2427
SC1U10V2KX-1GP
3D3V_S0
C2430
SCD1U10V2KX-5GP
VCCIO
AF13
VCCIO
AH13
VCCIO
AH14
VCCIO
AF14
C2429
SCD1U10V2KX-5GP
(0.1uFx2)
C2431
SCD1U10V2KX-5GP
(0.1uFx1)
1D05V_VTT
VCCAPLLSATA
C2432
SC1U6D3V2KX-GP
CPU
1D05V_VTT
R2411
+V1.05S_VCCAPLL_SATA3
VCCVRM
AF11
VCCIO
AC16
VCCIO
AC17
VCCIO
AD17
VCCASW
T21
VCCASW
V21
VCCASW
T19
VCCSUSHDA
P32
(1uFx1)
AK1
1D5V_S0
C2435
SC1U6D3V2KX-GP
C2434
DY
DY
(10uFx1)
0R3J-0-U-GP
1D05V_VTT
(1uFx1)
+3VS_+1.5VS_HDA_IO
1 R2409 2
0R0603-PAD
+3VS_+1.5VS_HDA_IO
C2433
SCD1U10V2KX-5GP
3D3V_S5
<Core Design>
0.01A
1
VCCRTC
RTC
V_PROC_IO
COUGAR-GP-U2-NF
(0.1uFx2)
(1uFx1)
A22
6uA
BJ8
DYC2437
SC1U10V2KX-1GP
C2428
SC1U6D3V2KX-GP
5V_S0
TPAD14-GP
(0.1uFx1)
Wistron Corporation
DCPSUS
MISC
C2422
SCD1U10V2KX-5GP
RTC_AUX_S5
TP2406
C2418
SCD1U10V2KX-5GP
C2417
SC4D7U6D3V3KX-GP
(0.1uFx2)
(4.7uFx1_0603)
20101224 A00:
0402 0R pad: R2404,R2405.
0.001A
1
3D3V_S5
1D05V_VTT
HDA
TPAD14-GP
(0.1uFx1)
C2426
SCD1U10V2KX-5GP
3D3V_S0
DCPRTC
AG33
10R2J-2-GP
3D3V_S0
1D05V_VTT
C2421
SCD1U10V2KX-5GP
(1uFx1)
C2413
SC1U6D3V2KX-GP
(0.1uFx1)
BF47
R2408
C2425
SCD1U10V2KX-5GP
1 R2406 2
0R0603-PAD
BD47
+1.05VS_VCCA_B_DPL
+VCCDIFFCLK
0.001A
A
T26
3D3V_S5
+V1.05S_SSCVCC
R2405 1
VCCASW
+1.05VS_VCCA_A_DPL
(1uFx1)
0.055A
(0.1uFx1)
0R0402-PAD
VCCIO
2nd = 83.R2004.B8F 83.R0304.A8F

1
(1uFx1)
P24
(0.1uFx1)
C2424
SCD1U10V2KX-5GP
+VCCDIFFCLK
R2404 1
0R0402-PAD
+VCCDIFFCLKN
1D05V_VTT
1D05V_VTT
VCCASW
Y49
VCCSUS3_3
VCCASW
AA24
N16
1D5V_S0
DCPSUS
AA21
0.16A (Totally current of VCCVRM

(0.1uFx1)
VCCSUS3_3
V24
1
2
+VCCRTCEXT
C2411
SCD1U10V2KX-5GP
C2406
SC1U6D3V2KX-GP
1
2
1
1
C2410
SC1U6D3V2KX-GP
C2444
68.10050.10Y
2nd = 68.10090.10B
DY
1
2
IND-10UH-218-GP
(1uFx1)
(220uFx1)
0.08A+1.05VS_VCCA_B_DPL
1
L2403
C2409
SC1U6D3V2KX-GP
VCCSUS3_3
V23
C2443
68.10050.10Y
2nd = 68.10090.10B
DY
1
2
IND-10UH-218-GP
0.08A+1.05VS_VCCA_A_DPL
SC10U6D3V3MX-GP SC10U6D3V3MX-GP
L2402
T24
SC10U6D3V5KX-1GP
(1uFx1)
(220uFx1)
DY
C2404
SC10U6D3V5KX-1GP
C2403
SC10U6D3V5KX-1GP
(22uFx2_0603)
(1uFx3)
1.01A (Total current of VCCASW)
VCCSUS3_3
D2401
CH751H-40PT-GP
AL24
1D05V_VTT
1D05V_VTT
VCCIO
+VCCSUS1
VCCAPLLDMI2
AL29
TP2402
BH23
5V_S5
D
0.097A (Totally current of VCCSUS3_3)
TPAD14-GP
VCCSUS3_3
T23
3D3V_S5
3D3V_S5
+VCCAPLL_CPY_PCH
1D05V_VTT (10uFx1)
T29
VCC3_3
TP2404
C2402
SC1U10V2KX-1GP
T27
VCCIO
TPAD14-GP
1
2
68.10050.10Y
2nd = 68.10090.10B
SC10U6D3V5KX-1GP
+V3.3S_VCC_CLKF33
C2401
P28
VCCIO
L2401
1
2
IND-10UH-218-GP
T38
VCCIO
(1uFx1)
C2423
SC1U6D3V2KX-GP
+V3.3S_VCC_CLKF33
P26
DCPSUSBYP
SATA
DCPSUSBYP
USB
PCI/GPIO/LPC
TP2405
Clock and Miscellaneous
TPAD14-GP
VCCIO
V12
(0.1uFx1)
(10uFx1)
(1uFx1)
N26
VCCDSW3_3
VCCIO
T16
1D05V_VTT
10 OF 10
Cougar
Point
+VCCPDSW
POWER
VCCACLK
1 R2403 2
0R0603-PAD
AD49
0.002A
3D3V_S5
3D3V_S0
VCCACLK
TP2401
PCH1J
TPAD14-GP
SSID = PCH
Title
Size
Document Number
PCH 8/9(POWER2)
Rev
Nirvana 13
Date:
3
Friday, December 24, 2010
A00
Sheet
1
24
of
103
SSID = PCH
8 OF 10
PCH1H
H5
VSS
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
COUGAR-GP-U2-NF
A
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9 OF 10
PCH1I
Cougar
Point
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
<Core Design>
Wistron Corporation
Title
COUGAR-GP-U2-NF
PCH 9/9(VSS)
Size
Document Number
Rev
Nirvana 13
Date:
5
Sheet
1
A00
25
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
26
of
103
MEDIA_BTN2#
(19) SUS_PWR_ACK
(57) USBCHARGER_CB0
(62,82) USB3_PWR_ON
(28) SYS_THRM
USB3_PWR_ON
PSL_IN2
MODEL_ID_DET
(68) BATT_WHITE_LED#
ECSMI#_KBC
(69)
CAP_LED
(36) S5_ENABLE
(82) MEDIA_BTN3#
(39)
BAT_IN#
(70) LID_CLOSE#
(19) RSMRST#_KBC
(19,46) PM_SLP_S4#
(21) ME_UNLOCK
(38)
RCID
PSL_IN1
PSL_OUT
EC_GPIO72
(65) WIFI_RF_EN
(63,65) BLUETOOTH_EN
(19,36) S0_PWR_GOOD
(68) TP_LOCK_LED#
(61) USB_PWR_EN#
(19) AC_PRESENT
(36,42) IMVP_PWRGD
KBC_VCORF
USB_PWR_EN#
AC_PRESENT
E51_TxD
44
102
4
VDD
AVCC
GPIO2
GPIO3/AD6
GPIO4/AD5
GPIO5/AD4
PSL_IN2#_GPIO6
GPIO7/AD7
GPIO16
GPIO24
GPIO30
GPIO34/CIRRXL
GPIO36
GPIO41
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO46/CIRRXM/TRST#
GPIO51
PSL_IN1_GPIO70
PSL_OUT_GPIO71
VBKUP
GPIO75
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST#
GPIO84/IOX_SCLK/XORTR#
GPIO97
GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4
100.0K
47.0K
2.24V
LPC_AD[0..3]
HDMI_IN#
ECSWI#_KBC
64.9K
100.0K
76.8
1.87V
100.0K
100.0K
1.65V
F_CS0#
F_SCK
F_SDI/F_SDIO1
F_SDIO/F_SDIO0
Reserved
100.0K
143.0K
1.358V
Reserved
100.0K
174.0K
1.204V
MEDIA_BTN1#
TPDATA
TPCLK
(21,65,71)
100.0K
(69)
(69)
ECRST#
2 R2736
2 R2719
2 R2737
2 R2722
1 33R2J-2-GP
1 33R2J-2-GP
1 0R0402-PAD
1 33R2J-2-GP
SPI_CS0#_R (21,60)
SPI_CLK_R (21,60)
SPI_SO_R (21,60)
SPI_SI_R (21,60)
(5,22)
1D05V_VTT
NOTE:
Locate resistors R2719 and R2722 close
to the NPCE791L.
2 OF 2
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
GPIO15/A_PWM
KBSOUT5/TDO
GPIO21/B_PWM
KBSOUT6/RDY#
GPIO13/C_PWM
KBSOUT7
GPIO32/D_PWM
KBSOUT8
GPIO66/G_PWM
KBSOUT9/SDP_VIS#
GPIO33/H_PWM
KBSOUT10/P80_CLK
GPIO45/E_PWM
KBSOUT11/P80_DAT
GPIO40/F_PWM
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
VCC_POR#
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO87/CIRRXM/SIN_CR
GPIO83/SOUT_CR/TRIST#
KBSIN0
KBSIN1
GPIO55/CLKOUT/IOX_DIN_DIO
KBSIN2
GPIO00/EXTCLK
KBSIN3
KBSIN4
KBSIN5
PECI
KBSIN6
VTT
KBSIN7
85
E51_RxD
E51_TxD
113
111
(29) AMP_MUTE#
(19) PCH_SUSCLK_KBC
30
77
R2721
1
1
R2720
H_PECI
2 43R2J-GP PECI13
EC_VTT12
2
0R0402-PAD
C2716
Need very close to EC

1
EC_SPI_DI_C
R2773
100KR2J-1-GP
DY
(17)
L_BKLT_EN
1
R2761
PROCHOT_EC
83.00016.K11
2ND = 83.00016.F11
1
EC_SCI#
(22)
DY
ECSCI#_KBC
3
BAS16-6-GP
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
USB_DET#
54
55
56
57
58
59
60
61
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
83.00016.K11
2ND = 83.00016.F11
(22)
2
0R0402-PAD
H_PROCHOT#
BAT54CPT-GP
EC_GPIO72
330KR2J-L1-GP
DY
3D3V_AUX_S5
174.0K
1.204V
DQ15_Ventura
100.0K
215.0K
1.048V
KCOL[0..16]
(69)
KROW[0..7]
(69)
D2705
R2760 1
0R0402-PAD
2
0R0402-PAD
EC_GPIO72
3D3V_AUX_KBC
1 R2734
DY
BAT_SCL
BAT_SDA
3
4
EC_GPIO72
0R2J-2-GP
MEDIA_BTN3#
PCIE_WAKE#
RN2701
VBACKUP
R2756
1
1
R2772
1
R2770
1
R2774
1
R2775
1
R2776
MEDIA_BTN1#
MEDIA_BTN2#
10mW SOLUTION
3D3V_AUX_KBC
2
1
KBC_ON#_R
KBC_ON#_GATE
Q2703
DMP2130L-7-GP
G
G
SRN10KJ-5-GP
DY
4
3
INSTANT_ON#
(82) INSTANT_ON#
PSL_IN1
3D3V_AUX_KBC
DY
3D3V_AUX_KBC
1 R2767
D
KBC_ON#_R
EC_ENABLE#_1
0R2J-2-GP
Q2705
PSL_OUT
S5_ENABLE
KBC_ON#
S
2N7002K-2-GP
Q2706
1 R2766 2
0R0402-PAD
FAN_TACH1
1
R2712
KBC_ON#_R
BAT54CPT-GP
1MEDIA_BTN2#
2
10KR2J-3-GP
(82) DATA_RECOVERY#
E51_RxD
DY
R2708
DATA_RECOVERY# 3
83.R2003.E81
2ND = 83.00054.Q81
2
2
10KR2J-3-GP
KBC_ON#_R
D2708
KBC_ON#_R
<Core Design>
20101228 A00:
Change R2756,R2763,R2766 to 0R short pad.
BLUETOOTH_EN
DY
R2709
Wistron Corporation
2
10KR2J-3-GP

Title
Size
A2
Date:
USB_DET#
83.R2003.E81
2ND = 83.00054.Q81
3D3V_S0
FAN_TACH1
NOTES:
Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.
4
USBDET_CON#
D2707
(28)
2ND = 84.2N702.031
2ND = 84.2N702.031
1
(57) USBDET_CON#
SRN10KJ-6-GP
KBC_ON#
10mW
2ND = 84.2N702.031
84.2N702.J31
84.2N702.J31
BAT54CPT-GP
1
2
3
4
84.2N702.J31
DY
D
KBC_ON#_R
D2706
2N7002K-2-GP
8
7
6
5
MEDIA_BTN1#
83.R2003.E81
2ND = 83.00054.Q81
1
2
RN2705
S5_ENABLE
ECRST#
PSL_OUT
Q2704
2N7002K-2-GP
2
100KR2J-1-GP
2
100KR2J-1-GP
2
100KR2J-1-GP
2
100KR2J-1-GP
2
100KR2J-1-GP
BAT54CPT-GP
2ND = 84.03413.A31
BAT54CPT-GP
AC_IN#_KBC
ECSMI#_KBC
ECSMI#_KBC
SRN100KJ-6-GP
EC_ENABLE#_1
84.02130.031
2ND = 83.00054.Q81 1
83.R2003.E81
A
PSL_IN1
2
0R0402-PAD
R2769
100KR2J-1-GP
1
(40)
DY
AC_IN#_KBC 1
AC_IN#
C2713
SCD1U10V2KX-5GP
D2703
2
PSL_IN1
DY
0R2J-2-GP
1
2
1
SRN4K7J-8-GP
BAT_IN#
AC_IN#_KBC
AC_OK 1 R2768
AC_OK
SCD1U10V2KX-5GP
RN2706
EC_SMI#
R2763
4
3
USB_DET#
KBC_ON#
100.0K
RTC_AUX_S5
(40)
C2722
1
2
10mW
1.358V
DN13_ATI
3D3V_AUX_KBC
3D3V_AUX_S5
2
D2702
143.0K
MEDIA BUTTON CONTROL
RN2703
83.R2003.E81
2ND = 83.00054.Q81
100.0K
C2715
MMBT3906-4-GP
2N7002K-2-GP
KBC_PWRBTN#
1.65V
DN13_UMA
84.2N702.J31
(68)
1.87V
100.0K
2ND = 84.2N702.031
R2704
2.0V
76.8K
100.0K
84.T3906.A11
2nd = 84.03906.F11
(5,40,42)
R2759 1ECSCI#_KBC
0R0402-PAD
EC_SCI#
64.9K(64.64925.6DL)
100.0K
Reserved
1
E
H_PROCHOT#_EC
1
R2733
PSL SOLUTION
R2758 1ECSWI#_KBC
0R0402-PAD
EC_SWI#
100.0K
Reserved
2.48V
20101224 A00:
0402 0R pad: R2760.
EC GPIO standard PH/PL
20101224 A00:
0402 0R pad: R2758,R2759.
(20)
DN15_ATI
EC_SMI#
PSL_IN2
2.24V
ECRST#
Q2701
D
R2732
D2704
B
47.0K(64.47025.6DL)
83.00016.K11
2ND = 83.00016.F11
2 PANEL_BLEN
0R0402-PAD
100.0K
BAS16-6-GP
(28,36) PURE_HW_SHUTDOWN#
Q2702
ECSWI#_KBC
3
BAS16-6-GP
DN15_UMA
33.0K
EC_SWI#
EC_AGND
100.0K
DY
(20)
DY
2.75V
DQ15_NVIDIA
EC_GPIO47 High Active
3.0V
20.0K(64.20025.6DL)
(22)
DY
D2701
SYS_THRM
10.0K(64.10025.6DL)
100.0K
R2705
10KR2J-3-GP
SCD1U10V2KX-5GP
1
SCD1U10V2KX-5GP
1
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
NPCE795PA0DX-GP-U
2
C2721
VOLTAGE
100.0K
DQ15_ATI
3D3V_AUX_S5
2
0R0402-PAD
100KR2J-1-GP
CPU_THRM
EC_AGND
GPIO56/TA1
GPIO20/TA2
GPIO14/TB1
GPIO01/TB2
LCD_TST_EN (49)
(65)
(65)
PULL-HIGH RESISTOR
DQ15_UMA
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
32
118
62
65
81
66
22
16
(68) CHG_AMBER_LED#
(29) KBC_BEEP
(82) MEDIA_LED1#
(69)
KB_BL_CTRL
(40) AD_IA_HW
(82) MEDIA_LED3#
(82) MEDIA_LED2#
(68)
PWRLED#
<------ TP
EC_AGND
C2719
DY
U2701B
BAT_SCL (39,40)
BAT_SDA (39,40)
SML1_CLK (20)
SML1_DATA (20)
PM_LAN_ENABLE (82)
EC_ENABLE#_1
PROCHOT_EC
AGND
1
R2711
1.048V
31
117
63
64
(28) FAN_TACH1
(19) PM_PWRBTN#
(82) PCIE_WAKE#
(19,36,37,47) PM_SLP_S3#
NOTE:
Connect GND and AGND planes via either
0R resistor or one point layout connection.
EC_AGND
ROSA Multi GPIO setting
215.0K
R2739
100KR2F-L1-GP
(51)
<------ BATTERY / CHARGER

<------PCH / eDP
EC_SPI_CS#_C
EC_SPI_CLK_C
EC_SPI_DI_C
EC_SPI_DO_C
C2718
NOTES:
The NPCE795P GPIO/PWM outputs that are connected
to LEDs have high drive buffers (20mA) and can be
connected directly to the LEDs.
BLON_OUT (49)
AD_IA_HW2 (40)
PCH_WAKE# (19)
AD_IA_HW2
90
92
86
87
2.0V
100.0K
Reserved
H_A20GATE (22)
H_RCIN# (22)
70
69
67
68
119
120
24
28
MODEL_ID_DET
Reserved
Reserved
INT_SERIRQ (21)
PM_CLKRUN# (19)
PANEL_BLEN
ECSCI#_KBC
27
25
11
10
71
72
A00
2.48V
20101224 A00:
0402 0R pad: R2737,R2735.
GND
GND
GND
GND
GND
GND
NPCE795PA0DX-GP-U
33.0K
2
1
PLT_RST# (5,18,65,71,82)
CLK_PCI_KBC (18)
LPC_FRAME# (21,65,71)
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
100.0K
PULL-LOW RESISTOR
MODEL_ID_DET(GPIO07)
R2710
143KR2F-GP
PLT_RST#_EC
R2735 1
2
0R0402-PAD
X02
Reserved
VCORF
C2712
SC1U10V3ZY-6GP
1
1
1
GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
7
2
3
1
128
127
126
125
8
9
29
124
123
121
122
AFTP2701
AFTP2702
AFTP2703
79
95
96
108
93
94
114
6
109
14
15
80
17
20
21
23
26
73
74
75
82
83
84
91
110
112
107
LRESET#
LCLK
LFRAME#
LAD3
LAD2
LAD1
LAD0
SERIRQ
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO67/PWUREQ#
GPIO85/GA20
KBRST#/GPIO86
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
2.75V
EC_AGND
DY
103
101
105
106
VREF
18
45
78
89
116
5
20101228 A00:
VGA_THRM change to USB_PWR_EN.
20101229 A00:
Rename USB_PWR_EN to USB3_PWR_ON.
PSID_EC
CPU_THRM
FAN1_DAC
LCD_TST
97
98
99
100
DY
C2711
1
2
SC220P50V2KX-3GP
1 OF 2
R2726
100KR2F-L1-GP
3.0V
20.0K
SC1U6D3V2KX-GP
(38)
(28)
C2717
SCD1U10V2KX-5GP
VOLTAGE
10.0K
100.0K
PCB_VER_AD
(28)
(49)
C2703
SC2D2U10V3KX-1GP
PULL-HIGH RESISTOR
100.0K
X01
104
2 SCD1U10V2KX-5GP
19
46
76
88
115
U2701A
AD_IA
C2714
EC_AGND
DY
EC_AGND
VCC
VCC
VCC
VCC
VCC
1
2
(40)
C2708
SCD1U10V2KX-5GP
C2707
SCD1U10V2KX-5GP
DY
C2706
SCD1U10V2KX-5GP
2
1
C2705
SCD1U10V2KX-5GP
2
1
1
2
C2704
SCD1U10V2KX-5GP
1
1
SC2D2U10V3KX-1GP
C2702
SCD1U10V2KX-5GP
PCB_VER_AD
3D3V_AUX_KBC_VCC
C2701
VBAT
PULL-LOW RESISTOR
X00
PCB VERSION A/D(PIN98)
R2724
47KR2F-GP
3D3V_S0
R2771
2D2R3-1-U-GP
C2710
SCD1U10V2KX-5GP
1 R2702 2
0R0603-PAD
C2709
SC2D2U10V3KX-1GP
2
1
3D3V_AUX_KBC
3D3V_AUX_KBC
SSID = KBC
SCD1U10V2KX-5GP
3D3V_AUX_KBC
20101224 A00 Modify:
Change R2724 to 47K from 33K.
SCD1U16V2KX-3GP
2
KBC Nuvoton NPCE785P
Document Number
Rev
Nirvana 13
Sheet
1
A00
27
of
103
Fan controller
Thermal sensor P2800
U2802
*Layout* 10 mil
C2802
74.00991.031
87.1 Degree
3rd = 74.05606.A71
C2805
1
R2807
FAN_TACH1_C
2
0R0402-PAD
3
2
*Layout* 15 mil
SYS_THRM (27)
CPU_THRM (27)
FAN_VCC
1
4
DY
74.02800.A71
AFTP2801
1FAN_TACH1_C
AFTP2802
1FAN_VCC
ACES-CON3-11-GP
C2808
D2802
C2810
CH551H-30PT-GP
DY
C2809
U2801
1.H/W T8 Shutdown
ADJ
TDR
TDL
GND
ADJ
FAN_TACH1
SC4D7U6D3V3KX-GP
3rd = 84.03904.T11
2.System Sensor, Put on palm rest
R2808
NTC-100K-8-GP
VCC
DXP
DXN
OTZ
(27)
4
3
2
1
5
C2807
6
SC2200P50V2KX-2GP
7
THERM_SYS_SHDN#_OTZ
8
C2803 C2804
FAN1
SCD1U16V2KX-3GP
2
1
2
P2800_DXN
20101224 A00 Modify:

If stuff P2800EA1 then must stuff R2803,R2804
C2805 but if stuff P28003B0 should be un-stuff.
P2800EA1-GP
1
1
3
2
PMBS3904-1-GP
84.03904.L06
2nd = 84.03904.P11
C2806
SC470P50V3JN-2GP
P2800A1
P2800A1
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
R2804
226KR2F-GP
P2800_DXP
DY
2nd = 74.02793.A31
ADJ
Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.
Q2801
5V_S0
G991P11U-GP
3D3V_DAC_S0
8
7
6
5
GND
GND
GND
GND
For linear FAN
R2803
P2800A1107KR2F-GP
FON#
VIN
VO
VSET
FAN1_DAC
(27)
FAN_VCC
1
2
3
4
3D3V_DAC_S0
0R2J-2-GP
FON#
SCD1U10V2KX-5GP
DY
R2802
1
5V_S0
83.R5003.C8F
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
2nd = 20.F1841.003
3D3V_S0
R2805
2
1
THERM_SYS_SHDN#_OTZ
20.F0772.003
SC2200P50V2KX-2GP
SSID = Thermal
SC4D7U6D3V3KX-GP
0R2J-2-GP
R2809
100KR2J-1-GP
THERM_SYS_SHDN#
Q2802
(27,36) PURE_HW _SHUTDOW N#
G
C2811
SCD1U10V2KX-5GP
DY
B
3D3V_S0
0629 Modify
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
20101228 A00 Modify:

Un-stuff U2805 G709T1UF related circuit
and R2812 then stuff R2805 at X-Build.
RSET = 0.0012T 2 0.9308T + 96.147

T=87 ; RSET=24.25ohm
R2806
24K3R2F-1-GP
U2805_1
2U2805_3
DY 0R2J-2-GP
1
2
3
SET
GND
OUT# DY
VCC
HYST
DY
U2805_5
2
1
150R2F-1-GP
C2817
DY
1
R2812
DY
2
1
THERM_SYS_SHDN#
3D3V_DAC_S0
R2801
U2805
G709T1UF-GP
74.00709.A7F
SCD1U10V2KX-5GP
R2810 3D3V_S0
U2805_4 2 DY
1
R2811
0R2J-2-GP
2
1
DY
0R2J-2-GP
Hysterisis is 10C for HYST = VCC, 2C for HYST = GND.

<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
THERMAL P2800 / Fan control
Document Number
Rev
Nirvana 13
A00
Sheet
1
28
of
103
AUD_SPK_LAUD_SPK_L+
1R2901
33R2J-2-GP
HDA_CODEC_SYNC
HDA_CODEC_RST#
AUD_PC_BEEP
(21) HDA_CODEC_SYNC
(21) HDA_CODEC_RST#
1
2
2
1
C2906
SC1U10V2KX-1GP
2
1
C2910
SC10U6D3V5MX-3GP
PUMP_CAPP
CAP+
CAPVAVSS2
PORTB_R
PORTB_L
AVSS2
PORTA_R
PORTA_L
AVDD1
30
29
28
27
26
25
24
23
22
21
PUMP_CAPN
AUD_V_B
AUD_HP1_JACK_R
AUD_HP1_JACK_L
C2914
SC2D2U10V3KX-1GP
R2906
R2905
AUD_EXT_MIC_R
AUD_EXT_MIC_L
2 60D4R2F-GP
2 60D4R2F-GP
1
1
C2922
C2921
AUD_HP1_JACK_R2
AUD_HP1_JACK_L2
1 SC1U10V3KX-3GP
1 SC1U10V3KX-3GP
2
2
(58)
(58)
MIC_IN_R (58)
MIC_IN_L (58)
+AVDD
SENSE_A
SENSE_B
PORTF_L
PORTF_R
PORTC_L
PORTC_R
VREFFILT
CAP2
VREFOUT_A
VREFOUT_C
Put C2921 and C2922 close to codec
11
12
13
14
15
16
17
18
19
20
C2902
SCD1U10V2KX-5GP
2
1
C2904
SCD1U10V2KX-5GP
C2903
SC1U6D3V2KX-GP
Close to codec
DVDD_LV
DMIC_CLK/GPIO_1
DMIC_0/GPIO_2
SDATA_OUT
BITCLK
SDATA_IN
DVDD
SYNC
92HD87B1A5NDGXTBX8-GP
RESET#
71.92H87.A03
PCBEEP
1 R2904 2
0R0603-PAD
2
(49,97) AUD_DMIC_CLK
(49,97) AUD_DMIC_IN0
(21) HDA_CODEC_SDOUT
(21) HDA_CODEC_BITCLK
(21) HDA_SDIN0
3D3V_S0
1
2
3
4
5
6
7
8
9
10
AUD_DMIC_CLK
AUD_DMIC_IN0
HDA_CODEC_SDOUT
HDA_CODEC_BITCLK
2HDA_CODEC_SDIN0
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVSS
PORTD_-L
PORTD_+L
PVDD
AVDD2
VREG/+2_5V
U2901
C2901
SC10U6D3V5MX-3GP
AUD_DVDDCORE
41
40
39
38
37
36
35
34
33
32
31
Close to codec
5V_S0
1 R2903 2
0R0603-PAD
1 R2902 2
0R0603-PAD
+AVDD
C2905
SCD1U10V2KX-5GP
+PVDD
+PVDD
AUD_SPK_L- (58)
AUD_SPK_L+ (58)
AUD_VREG
AMP_MUTE#
(27) AMP_MUTE#
5V_S0
C2909
SC1U10V2KX-1GP
SSID = AUDIO
+AVDD
C2908
SCD1U10V2KX-5GP
AUD_VREFFLT
AUD_CAP2
AUD_VREFOUT_B
3D3V_S0
AUD_PC_BEEP
AUD_SENSE_A
AUD_SENSE_B
AUD_CAP2
AUD_VREFFLT
R2908
10KR2J-3-GP
AUD_V_B
1 SCD1U10V2KX-5GP SB_SPKR_R
C2913
1 SCD1U10V2KX-5GP KBC_BEEP_R 1
C2907
SC4D7P50V2CN-1GP
DY
2
C2923
SC1U10V2KX-1GP
47R2J-2-GP
AUD_PC_BEEP
Trace width>15 mils
R2910
470KR2J-2-GP
G2901
DUMMY-C2
From PCH
HDA_SPKR (21)
1
2
120KR2J-L-GP
R2909
1
2
C2912
C2916
SC1U6D3V2KX-GP
AUD_PC_BEEP
HDA_CODEC_BITCLK
C2915
SC10U6D3V5MX-3GP
DY 2
R2907
C2918
SC10U6D3V5MX-3GP
AUD_VREFOUT_B
HDA_CODEC_BITCLK_1 1
AMP_MUTE#
C2917
SC4D7U6D3V3KX-GP
AUD_VREG
KBC_BEEP (27)
From EC
Close to codec
B
2
1
AUD_VREFOUT_B
RN2901
SRN4K7J-8-GP
Azalia I/F EMI

1
3
4
HDA_CODEC_SDOUT
R2912
47R2J-2-GP
+AVDD
+AVDD
R2913
(58)
(58)
MIC_IN_L
MIC_IN_R
R2916
2K49R2F-GP
20KR2F-L-GP
AUD_SENSE_B
<Core Design>

2
C2920
SCD1U10V2KX-5GP
Wistron Corporation
R2919
EXT_MIC_JD# (58)
Title
39K2R2F-L-GP
Close to Pin13
Size
A3
Close to Pin14
Date:
5
R2918
20KR2F-L-GP
C2919
SC1000P50V3JN-GP-U
1
2
DY
(58)
AUD_SENSE_A
AUD_HP1_JD#
R2915
2K49R2F-GP
PCH_AZ_CODEC_SDOUT1
DY
Audio Codec 92HD87B1

Document Number
Rev
A00
Nirvana 13
Sheet
1
29
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
30
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
Nirvana 13
A00
Sheet
1
31
of
103
SSID = SDIO
48MHz clock input trace of characteristic impedance (Zo) must be 50 15%.
3D3V_CARD_S0
3D3V_CARD_S0
XD_D7
SP14
SP13
SP12
SP11
3D3V_S0
1 R3201 2
6K2R2F-GP
USB_PN5_R
USB_PP5_R
V18
C3202
SC1U10V2KX-1GP
25
RREF
DM
DP
3V3_IN
CARD_3V3
V18
GND
XD_D7
SP14
SP13
SP12
SP11
(74)
(74)
(74)
(74)
(74)
1
C3206
SCD1U10V2KX-4GP
C3207
SC4D7U6D3V5KX-3GP
Close to chip
U3201
RTS5138-GR-GP
SP10
GPIO0
SP9
SP8
SP7
SP6
18
17
16
15
14
13
SP10
SP10
(74)
SP9
SP8
SP7
SP6
SP9
SP8
SP7
SP6
(74)
(74)
(74)
(74)
7
8
9
10
11
12
C3204
SC4D7U6D3V3KX-GP
DY
2
C3203
SCD1U10V2KX-4GP
3D3V_CARD_S0
1
2
3
4
5
6
CLK_IN
XD_D7
SP14
SP13
SP12
SP11
SC100P50V2JN-3GP
MAX 0.4A
RREF
24
23
22
21
20
19
DY2
XD_CD#
SP1
SP2
SP3
SP4
SP5
C3201
1
PCH GPIO67(48M) confirm with SW
(20,97) CLK_PCH_48M
71.05138.003
SP5
SP4
SP3
SP2
SP1
XD_CD#
SP5
SP4
SP3
SP2
SP1
XD_CD#
(74)
(74)
(74)
(74)
(74)
(74)
The maximum range of the PMOS output current

1. xD-Picture Card: 250mA
2. SD/MMC Card: 250mA
3. MS/MSPRO/Duo-HG: 250mA
The pin2 / pin3 (DM/DP) of RTS5138 chip trace layout

with differential characteristic impedance (Zdiff) is 90 10%
POWER TRACE
1.RTS5138: pin 4 (3V3_IN) trace fixed width is 30 mils (minimum).
2.RTS5138: pin 5 (CARD_3V3) trace fixed width is 30 mils (minimum).
3.RTS5138: pin 6 (V18) trace fixed width is 12 mils (minimum).
Keep the trace routing lengths as short as possible.
4.RTS5138: pin 1(RREF) trace fixed width is 12 mils (minimum).
5.RTS5138: pin 1(RREF) trace must far away 48MHz clock trace.
6.De-coupling and Bulk capacitor should place near to RT5138 chip and Combo Socket.
7.It is recommended that use of ferrites bead on power trace.
8.Via size: Pad>=32 mils, Finished hole>=16 mils.
(18)
1 R3211
USB_PP5
USB_PP5_R
0R0402-PAD
(18)
USB_PN5
1 R3210
USB_PN5_R
0R0402-PAD
20101227 A00:
Change R3210,R3211 to 0R 0402 pad.
20100104 A00:
Remove TR3201.
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Card Reader RTS5138

Document Number
Rev
Nirvana 13
A00
Sheet
1
32
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
33
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
34
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
Nirvana 13
A00
Sheet
1
35
of
103
20100723 Default stuff R3622 PH Resistor to fix Annie demo board SLP_S3 abnormal issue from Annie team updated.
20101224 A00:
0402 0R pad: R3614.
2
1
56R2J-4-GP
1D05V_VTT
(5,22)
1 R3601
(5,22) H_CPUPWRGD
DY
2 H_PWRGD_R
1KR2J-1-GP
DY Q3601
C3602
DY
SCD1U10V2KX-5GP
CHT2222APT-GP
DY
C3612
SCD01U50V2KX-1GP
Q3603
PS_S3CNTRL
H_THERMTRIP#
SYS_PWROK
R3614 1
0R0402-PAD
SSID = Reset.Suspend
(27,42) IMVP_PWRGD
R3622
Power Sequence
D
S
2ND = 83.00016.F11
83.00016.K11
2N7002K-2-GP
BAS16-6-GP
2
2
3
3
(41)
3V_5V_EN
(19)
1
SYS_PWROK
D3602
BAS16-6-GP
83.00016.K11
2ND = 83.00016.F11
PURE_HW_SHUTDOWN#
(27,28)
DY
R3602
200KR2J-L1-GP
(19,27) S0_PWR_GOOD
D3601
1
R3603
2
1KR2J-1-GP
S5_ENABLE (27)
0621 Modify:
Change R3603 to 1K from 2K 0402.
SSID = Reset.Suspend
AO4468 MAX 9A
Rds(on) = 18.5mOhm
2nd = 84.08882.037
15V_S5
+5V_RUN
84.04468.037
5V_S5
5V_S0
AO4468-GP
+5V_RUN Comsumption
Peak current 7.73A
4
3
2
1
1
5
6
7
8
D
D
D
D
R3604
100KR2J-1-GP
S
S
S
G
Run Power
U3601
5V_RUN_ENABLE
2
10KR2J-3-GP
1
1 R3605
3D3V_AUX_S5
PS_S3CNTRL (37)
1 R3606
C3603
SC10U10V5ZY-1GP
C3608
SCD01U50V2KX-1GP
PS_S3CNTRL
2
100KR2J-1-GP
84.04468.037
PM_SLP_S3#
+3.3V_RUN Comsumption
Peak current 8.14A
U3602
1 R3607
3.3V_RUN_ENABLE
2
10KR2J-3-GP
C3604
SC10U6D3V5KX-1GP
RUN_ENABLE
4
3
2
1
(19,27,37,47)
5
6
7
8
+3.3V_RUN
3D3V_S0
AO4468-GP
S G D
3D3V_S5
84.2N702.A3F
2nd = 84.DM601.03F
D
D
D
D
Rds(on) = 18.5mOhm
AO4468 MAX 11.6A
2nd = 84.08882.037
Q3602
2N7002KDW-GP
S
S
S
G
D G S
C3605
SCD01U50V2KX-1GP
+1.5V_RUN_CPU Comsumption
Peak current 10A
1D5V_S3
+1.5V_RUN for Mini-Card Comsumption

Peak current 1A
1D5V_S0
D
D
D
D
U3606
S
S
S
G
1
2
3
4
TPCA8062-H-GP
1.5V_RUN_ENABLE
2
10KR2J-3-GP
2nd = 84.00460.037
2
C3610
SCD01U50V2KX-1GP
Total= 11.39A
C3609
SC10U6D3V5KX-1GP
84.08062.037
1 R3630
8
7
6
5
1D5V_S0
MAX Current ? mA
Design Current ? mA
TPCA8062-H-GP MAX 28A

Rds(on) = 4.1~5.4m OHM
3rd = 84.00312.037
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
Power Plane Enable
Document Number
Sheet
1
Rev
A00
Nirvana 13
36
of
103
Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK
2
S
R3705
100KR2J-1-GP
Q3702
2N7002K-2-GP
Q3701
2N7002K-2-GP
DY
84.2N702.J31
2N7002K-2-GP
RUN_ENABLE
2ND = 84.2N702.031
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
84.2N702.J31
R3704
220R2J-L2-GP
+V_SM_VREF_CNT (9)
+V_SM_VREF
2
0R0402-PAD
DY
Q3701_D
Q3708
1
R3708
Q3702_D2
R3703
22R2J-2-GP
R3707
0R2J-2-GP
1
DY 2
M_VREF_DQ_DIMM0
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
D
1D5V_S0
0D75V_S0
PS_S3CNTRL
(36) PS_S3CNTRL
Close to CPU
S3 Power Reduction
1D5V_S3
2N7002K-2-GP
G
D
R3706
1KR2J-1-GP
0D75V_EN
1.05VTT_PW RGD (45,48)
DY1
84.2N702.J31
R3710
0R0402-PAD
2ND = 84.2N702.031
R3709
2
0R2J-2-GP
2ND = 84.2N702.031 S3 Power Reduction Circuit
Q3704
(36) PS_S3CNTRL
84.2N702.J31
20101224 A00:
0402 0R pad: R3710.
Q3703
SM_DRAMRST#
(5) SM_DRAMRST#
2
DY 22R2J-2-GP
0D75V_EN (46)
1
R3716
2N7002K-2-GP
(14,15)
C3702
SC100P50V2JN-3GP
C3705
SCD1U10V2KX-5GP
DRAMRST_CNTRL_PCH
(20)
DY
DDR3_DRAMRST#
D
(19,27,36,47) PM_SLP_S3#
SM_DRAMRST#_D
1 R3718 2
1KR2J-1-GP
Close to CPU
C3703
1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
3D3V_S0
3D3V_S0
DY
5
2
4
R3719
0D75V_EN
R3702
200R2F-L-GP
VDDPW RGOOD_R
3
TC7SZ08FU-2-GP
U3701
1D5V_S0
CEKLT V1.0: PCH to 1K,CUP to 200R
R3713
200R2F-L-GP
R3721
39R2J-L-GP
VDDPW RGOOD (5)
DY
2
73.7SZ08.EAH
2ND = 73.01G08.L04
2
910R2F-GP
Q3707_D
R3720
750R2F-GP
DY Q3707
2N7002K-2-GP
Wistron Corporation
2ND = 84.2N702.031

VDDPW RGOOD_R
1
DY 2
0R2J-2-GP
<Core Design>
84.2N702.J31
R3717
3rd = 73.7SZ08.DAH
Title
SM_DRAMPWROK must have a maximum of 15ns rise or fall time

over VDDQ * 0.55 200mV and the edge must be monotonic
PS_S3CNTRL
Size
A3
Date:
S3 Power Reduction
Document Number
Nirvana 13
Rev
A00
Sheet
1
37
of
103
5V_S5
D
PS_ID_R
PD3803
BAV99-5-GP-U
2nd = 83.00099.K11
PS_ID
PR3806
2K2R2J-2-GP
83.00099.T11
PR3807
PS_ID_1
(82)
PQ3801
FDV301N-NL-GP
PSID_DISABLE#_R
1
PR3804
PS_ID_R
3D3V_S5
2nd = 84.03904.P11
3rd = 84.03904.T11
PR3803
100KR2J-1-GP
3D3V_S5
PR3802
10KR2J-3-GP
84.03904.L06
PQ3802
PMBS3904-1-GP
PQ3802_1 1
PR3801
15KR2J-1-GP
3rd = 83.BAV99.D11
PSID_EC (27)
33R2J-2-GP
0R0402-PAD
2N7002K-2-GP
DY
RCID
33R2J-2-GP
PR3812
100KR2J-1-GP
DY
DY
S
C
PQ3803
(27)
PR3808
PD3804
DY B240A-13-GP
84.2N702.J31
2ND = 84.2N702.031
This cap should be used

only as last resort for
EMI suppression.
1
2
1
2
DY
PC3806
SC10U25V6KX-1GP
Id=-12A
Qg=-25nC
Rdson=10~38mohm
DY
PC3803
SCD01U50V2KX-1GP
AO4407A-GP
8
7
6
5
D
D
D
D
PR3810
240KR3-GP
PU3801
S
S
S
G
PC3802
SCD01U50V2KX-1GP
2ND = 83.P6SBM.AAG
PU3801_G
1
PC3801
SCD1U50V3KX-GP
DY
83.22R03.03G
PC3804
SC1U25V5KX-1GP
1
PD3801
1SMB22AT3G-GP-U
Place close to BTB connector
1
2
3
4
PC3805
SCD01U50V2KX-1GP
AD+
280mils or Copper Shape

K
+DC_IN
AFTP3801
AFTP3802
AFTP3803
1
1
1
PR3811
47KR3J-L-GP
PS_ID_R
+DC_IN
+DC_IN
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
DCIN Jack
Rev
Nirvana 13
Sheet
1
A00
38
of
103
C3902
SCD1U50V3KX-GP
K
2
(40) BATT_SENSE
C3901
SC2200P50V2KX-2GP
BATT1
10
1
D
PN3901
4
3
2
1
(27,40) BAT_SCL
(27,40) BAT_SDA
(27)
BAT_IN#
Batt Connecter
DY
A
GAP-CLOSE-PW R-3-GP
G3901
PD3902
1SMA18AT3G-GP

BT+
2
3
4
5
6
7
8
9
11
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
5
6
7
8
AFTP3901
BAT_ALERT
SRN33J-7-GP
20101224 A00:
Rename PRN3901 to PN3901.
DY
2
1
SC10P50V2JN-4GP
2
1
SC10P50V2JN-4GP
EC3901 EC3902
TCN-CON9-3-GP
DY
AFTP3902
AFTP3903
AFTP3904
AFTP3905
20.81327.009
1
1
1
1
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
BT+
For actual location, need to be swap all pin

Placement: Close to Batt Connector
BAT_SCL
BAT_SDA
BAT_IN#
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
D3901
BAV99-5-GP-U
D3903
BAV99-5-GP-U
D3902
BAV99-5-GP-U
83.00099.T11
2nd = 83.00099.K11
3rd = 83.BAV99.D11
3D3V_AUX_KBC
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
BATT CONN
Rev
Nirvana 13
A00
Sheet
1
39
of
103
SSID = Charger
CHG_AGND
1 PR4023 2
0R0402-PAD
VFB
15
GND
16
PWR_CHG_VFB 1 PR4028 2
0R0402-PAD
29
PC4023
SCD1U50V3KX-GP
CHG_AGND
CHG_AGND
1
2
EC4002
SCD1U25V2ZY-1GP
EC4001
SC2200P50V2KX-2GP
PC4009
SCD1U50V3KX-GP
DY
1
PR4030
1K8R6J-GP
DY
PR4024
0R0402-PAD
BATT_SENSE (39)
1
1 PR4029 2
0R0402-PAD
PWR_CHG_CSOP_1
NC#16
BQ24745RHDR-GP
DYPC4030
2
FBO
EAI
EAO
VREF
CE
GND
PL4001
Id=7.5A
DCR=23mohm(Max)
Size=10*10
PU4005
Id=16A
Qg=7.3nC
Rdson=13.5~16.5mohm
VICM
SCD1U10V2KX-5GP
PC4028
SCD01U50V2KX-1GP
PC4029
2
DY
2
PWR_CHG_CSON
BT+
PR4019
1
2
D01R2512F-4-GP
DY
1 PR4020 2
0R0402-PAD
CHG_AGND
CHG_AGND
CHG_AGND
1
PQ4004_D
AC_IN#
PR4037
76K8R2F-GP
2
PQ4004
2N7002K-2-GP
3D3V_AUX_S5
2ND = 84.2N702.031
84.2N702.J31
ICREF
PR4040
10KR2J-3-GP
AC_OK
AC_OK
(27)
(27)
AD_IA_HW2
DY2ND = 84.2N702.031
PQ4002
2N7002K-2-GP
84.2N702.J31
DY
2
PC4033
SCD1U10V2KX-5GP
(27)
PC4025
1
2
SC56P50V2JN-2GP
DYPC4027
SCD01U50V2KX-1GP
2
1PWR_CHG_FBO1
2
SCD1U50V3KX-GP
2
This Resistor
must be 1%
tolerance.
6
PWR_CHG_EAI
5
PWR_CHG_EAO
4
PWR_CHG_REF
3
PWR_CHG_CE 7
1 PR4027 2
12
0R0402-PAD
PC4022
PR4026
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
2
1PR4526_01
2
1
PC4021
SC150P50V2JN-3GP
DY
PC4026
PWR_CHG_CSOP
17
PR4022
200KR2F-L-GP
1
2
SC1U6D3V2KX-GP
PC4024
SC220P50V2JN-3GP
1
2
PR4025
8K45R2F-2-GP
1
2
18
S
S
S
G
DY
PR4021
4K7R2J-2-GP
CSON
4
3
2
1
CSOP
CHG_AGND
PWR_CHG_VICM
PWR_CHG_FBO
PC4020
SCD1U50V3KX-GP
1
2
20KR2J-L2-GP
19
AD_IA
PGND
PC4032
SCD1U25V2ZY-1GP
(27)
NC#14
PC4008
SC10U25V6KX-1GP
2
1
1
D
D
D
D
14
PR4001
PC4007
SC10U25V6KX-1GP
2
1
5
6
7
8
84.00412.037
DY
1
2
PC4014
SC220P50V2JN-3GP
PWR_CHG_LGATE
IND-5D6UH-48-GP-U1
PC4034
SC10U25V6KX-1GP
DY
Charger Current=1.4~3.6A
BT+_R
PL4001
PC4019
SCD1U50V3KX-GP
2
1
LGATE
20
PWR_CHG_PHASE 1 PR4018 2
0R0603-PAD
PC4013
SC3300P50V3KX-1GP
PWR_CHG_LX1
PC4018
SC10U25V6KX-1GP
2
1
1
2
PC4012
SCD1U50V3KX-GP
PC4017
SC10U25V6KX-1GP
2
1
SDA
23
GAP-CLOSE-PWR-3-GP
PG4005
1
83.1R504.A8F
2nd = 83.1R504.B8F
PU4004
SIS412DN-T1-GE3-GP
PWR_CHG_UGATE
DY
PC4016
SC10U25V6KX-1GP
2
1
24
2
1
PC4015
SC10U25V6KX-1GP
2
1
UGATE
SCL
DY
PG4009
GAP-CLOSE-PWR-3-GP
2PG4009_1
1
2
2
PG4008
PWR_CHG_SDA
1
GAP-CLOSE-PWR-3-GP
10
CHG_AGND
1
2
PC4011
SCD1U50V3KX-GP
PU4004
Id=12A
Qg=3.8nC
Rdson=24~30mohm
PG4010
GAP-CLOSE-PWR-3-GP
1
2
PWR_CHG_SCL
1
GAP-CLOSE-PWR-3-GP
PWR_CHG_BOOT 1 PR4017 2PWR_CHG_BST1

K
A
PWR_CHG_VDDP 0R0603-PAD
SD103AWS-1-GP
PU4005
SIS412DN-T1-GE3-GP
2
PG4007
25
21
BOOT
VDDP
ACOK
GAP-CLOSE-PWR-3-GP
PG4004
1
DY
4
3
2
1
DY
CHG_AGND
Id=-12A
Qg=-25nC
Rdson=10~38mohm
PWR_DCBATOUT_CHG
PWR_DCBATOUT_CHG
13
2nd = 84.P1403.B37
0R0402-PAD
PD4001
PWR_CHG_ACOK
1 PR4012 2
0R0402-PAD
GAP-CLOSE-PWR-3-GP
2
PG4001
1
GAP-CLOSE-PWR-3-GP
PG4006
1
SCD1U50V3KX-GP
PWR_CHG_CSSN
PWR_CHG_ICOUT
5
6
7
8
(27,39) BAT_SDA
27
26
84.04407.F37
PR4006
470KR2J-2-GP
PR4032
PC4006
SC1U6D3V2KX-GP
CSSN
ICOUT
VDDSMB
PC4005
PWR_CHG_CSSP 1
2
PC4004
SCD1U50V3KX-GP
ACIN
(5,27,42) H_PROCHOT#
28
D 8
D 7
D 6
D 5
ICREF
CSSP
PHASE
CHG_AGND
PR4010
0R0402-PAD20101222 A00
Power/Brian: Change PR4032 to 0 ohm pad.
1
2
PC4002
SCD1U50V3KX-GP
CHG_AGND
AC_OK
(27,39) BAT_SCL
PR4008
0R0402-PAD
PC4001
SCD1U10V2KX-5GP
CHG_AGND
1
2
2
2
11
DCIN
PR4007
0R2J-2-GP
PR4013
33R3J-2-GP
2
1
1
2
1
2
PWR_CHG_ACIN
PC4003
SCD47U50V5KX-1GP
3D3V_AUX_KBC
22
S
S
S
G
PC4010
SCD01U50V2KX-1GP
PR4016
10KR2F-2-GP
2
1
PWR_CHG_DCIN
DY
D
D
D
D
49K9R2F-L-GP
1
PR4031
150KR2F-L-GP
PWR_CHG_REF
PR4034
0R0402-PAD
20101222 A00
CHG_AGND
Stuff PQ4003.
CHG_AGND
PU4001
2N7002KDW-GP
PR4033
20R5F-1GP 1
2PQ4003_G
AD_IA_HW
(27)
ICREF
PR4047
174KR2F-GP
84.2N702.J31
2ND = 84.2N702.031
G
DC_IN_D
PR4009
316KR3F-2-GP
1
2
1
AD+_G_1
PQ4001
PR4005
10KR2F-2-GP
2
PR4004
10KR2J-3-GP
2nd = 84.DM601.03F
PQ4003
2N7002K-2-GP
PU4003
S
S
S
G
AO4407A-GP
PG4003
GAP-CLOSE-PWR-3-GP
PR4524_03
84.2N702.A3F
PG4002
PR4035
GAP-CLOSE-PWR-3-GP
300KR2F-L-GP
1
2
3
4
AD+
2nd = 84.P1403.B37 AD+_G_2
PWR_CHG_ACOK
BT+
D01R2512F-4-GP
PWR_CHG_REF
PQ4003_D
84.04407.F37
AD+
DCBATOUT
1PR4533_02
AO4407A-GP
PR4014
2
20101222 A00
Power/Brian: Change PR4047 to 174k ohm from 121k ohm.
Change PR4035 to 300k from 49.9k.
Change PR4031 to 150k from 0 ohm.
PR4003
100KR2J-1-GP
Id=-12A
Qg=-25nC
Rdson=10~38mohm
AD+_TO_SYS
PR4002
1
2
3
4
PC4031
SCD1U50V3KX-GP

PU4002
S
S
S
G
8 D
7 D
6 D
5 D
AD+
2PQ4004_G
1
PR4036
0R0402-PAD
CHG_AGND
20101222 A00
Stuff PQ4004.
Change PR4037 to 76.8k ohm from 49.9k ohm.
<Core Design>
Wistron Corporation
Title
Size
Document Number
CHARGER BQ24745
Sheet
1
Rev
A00
Nirvana 13
Date:
40
of
103
20110110 A00:
Change PG4102~PG4109,PG4111,PG4113 to ZZ.CLOSE.001.
3D3V_AUX_S5
DCBATOUT
5V_AUX_S5
5V_AUX_S5
PU4105
GAP-CLOSE-PWR-3-GP
2
PR4119
0R0402-PAD
PG4142
1
20101230 A00:
GAP-CLOSE-PWR-3-GP Change PR4119 to 0R short pad.
2
PWR_5V3D3_AGND
PG4143
1
PR4119_2
1
2
CLOSE TO PIN 30
PC4123
SCD1U25V3KX-GP
20110110 A00:
Change PG4139,PG4141 to ZZ.CLOSE.001.
1
2
1
2
PC4111
SCD1U50V3KX-GP
1
2
PG4127
1
GAP-CLOSE-PWR-3-GP
PG4130
1
GAP-CLOSE-PWR-3-GP
PG4132
1
GAP-CLOSE-PWR-3-GP
PG4134
1
GAP-CLOSE-PWR-3-GP
DY PR4118
0R2J-2-GP
2
2KR2J-1-GP
3V_5V_EN
(36)
PR4123
100KR2J-1-GP
2
3V/5V_POK
PC4128
SCD1U25V2ZY-1GP
PG4101
1
GAP-CLOSE-PWR-3-GP
20101230 A00:
Change PR4114 to 0R short pad.
PR4127
39KR2J-GP
2
PG4141
1
PG4123
1
GAP-CLOSE-PWR-3-GP
1
215V_C_1
PR4125
200KR2J-L1-GP
GAP-CLOSE-PWR-3-GP
2
Connect REFIN2 to V5FILT for fixed 3.3V operation
PD4101
BAT54-7-F-GP
1
15V_C
1
PR4124
24D9R3F-GP
PG4139
1
PG4120
1
GAP-CLOSE-PWR-3-GP
3D3V_S5
BAT54SW-2-GP
GAP-CLOSE-PWR-3-GP
2
15V_PWR
5V_C_2 1
2
PC4127
SCD1U25V2ZY-1GP
77.22271.27L
3D3V_S5 20110110 A00:

Change PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134 to ZZ.CLOSE.001.
PG4118
1
GAP-CLOSE-PWR-3-GP
V_REFIN2=VREF2*PR4109/(PR4109+PR4105)
Vout(3.3V)=V_REFIN2*(1+R1/R2)
PR4122
200KR2J-L1-GP
2
3
2
15V_S5
1
PR4120
1
2
Connect VFB1to GND for fixe 5V opteration
2
1
PR4114
0R0402-PAD
PWR_5V3D3_AGND
5V_C_1 1
2
PC4125
SCD1U25V2ZY-1GP
BAT54SW-2-GP
PD4103
2PG4121_2 2
4
3
2
1
DY PR4112
2D2R6J-3-GP
GAP-CLOSE-PWR-3-GP
68.2R210.20B
PG4121
PC4118
SC680P50V2KX-2GP
PWR_3D3V_SNUB
DY
PWR_5V3D3_AGND
PWR_5V3D3V_EN
1
3
10V_C
PC4126
SCD1U25V2ZY-1GP
PC4101
SC1U25V3KX-1-GP
PC4110
SC1KP50V2KX-1GP
1
2
1
2
PC4108
SC10U25V6KX-1GP
PC4107
SC10U25V6KX-1GP
PC4109
SCD1U50V3KX-GP
3D3V_PWR
5V_AUX_S5
PC4132
SC1U10V3KX-3GP
1
2
5
6
7
8
PWR_5V3D3_AGND
PG4113
1
4
3
2
1
5
6
7
8
GAP-CLOSE-PWR-3-GP
2
20110110 A00:
Change PG4143 to ZZ.CLOSE.001.
PG4111
1
GAP-CLOSE-PWR-3-GP
2
PR4117
0R2J-2-GPDY
PD4102
PR4106
0R0603-PAD
1
2
8
7
6
5
4
3
2
1
VBST1
DRVL1
V5DRV
NC#20
GND
PGND
DRVL2
VBST2
PWR_5V__DRVL1
PG4109
1
GAP-CLOSE-PWR-3-GP
2
2
IND-2D2UH-46-GP-U
84.07702.037
17
18
19
20
21
22
23
24
1
2
SIR172DP-T1-GE3-GP
79.10712.L02
8
7
6
5
D
D
D
D
PU4102
S
S
S
G
2nd = 79.10712.6JL
PC4121
SCD1U25V3KX-GP
2PWR_5V__VBST1
2D2R3-1-U-GP
PG4106
1
PG4108
1
PT4103
ST220U6D3VDM-20GP
PG4140
1
PWR_5V__VBST1_1 1
GAP-CLOSE-PWR-3-GP
2
GAP-CLOSE-PWR-3-GP
2
PC4124
SCD1U10V2KX-4GP
GAP-CLOSE-PWR-3-GP
2
PR4115
PG4105
1
PG4107
1
PL4101
20101230 A00:
Change PR4116 to 0R0603 short pad.
PR4116
PWR_3D3V_VBST21
2PWR_3D3V_VBST2_1
0R0603-PAD
PWR_3D3V_DRVL2
GAP-CLOSE-PWR-3-GP
2
Design Current = 7.4A

11.6A<OCP< 13.7A
PU4107
AON7702-GP
GAP-CLOSE-PWR-3-GP
2
PG4104
1
GAP-CLOSE-PWR-3-GP
2
84.07410.A37
PG4138
1
PC4122
SCD1U25V3KX-GP
PG4103
1
GAP-CLOSE-PWR-3-GP
2
GAP-CLOSE-PWR-3-GP
2
PWR_5V3D3V_REFIN2
PWR_3D3V_TRIP21 PR4101 2 187KR2F-GP
PWR_3D3V_VOUT2
PWR_5V3D3V_SKIPSEL
1
2
DY
3V/5V_POK
PR4110
PWR_5V3D3V_EN
0R2J-2-GP
PWR_3D3V_DVRH2
PWR_3D3V_LL2
PG4137
1
32
31
30
29
28
27
26
25
REFIN2
VSW
TRIP2
VOUT1 TPS51427RHBR-GP VOUT2
VFB1
SKIPSEL
TRIP1
PGOOD2
PGOOD1
EN2
EN1
DVRH2
DRVH1
LL2
LL1
GAP-CLOSE-PWR-3-GP
2
GND
PG4136
1
2PWR_5V_TRIP1
PR4111 3V/5V_POK
200KR2F-L-GP PWR_5V3D3V_EN
PWR_5V_DRVH1
PWR_5V_LL1
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
20101224 A00:
2
Rename PTC4101~PTC4103 to PT4101~PT4103.
9
10
11
12
13
14
15
16
8
7
6
5
D
D
D
D
PU4108
1 S
2 S
3 S
4 G
PC4120
1
2
SC680P50V2KX-2GP
GAP-CLOSE-PWR-3-GP
PR4113
2D2R6J-3-GP
2
1
DY
PG4135
1
1
PC4117
SCD1U25V3KX-GP
PU4104
AON7410-GP
PWR_5V3D3_AGND
LDOREFIN
LDO
VIN
VREF3
EN_LDO
V5FILT
TONSEL
VREF2
PC4116
SC10U25V6KX-1GP
1
2
PWR_5V_SNUB
PG4125
1PWR_5V_VOUT1 2
PC4119
SCD1U10V2KX-4GP
DY
PT4101
ST220U6D3VDM-20GP
2
1
GAP-CLOSE-PWR-3-GP
2
PG4133
1
1
2
IND-1D5UH-34-GP
68.1R510.10J
33
2
PWR_5V3D3_AGND
DY
S
S
S
G
GAP-CLOSE-PWR-3-GP
2
PL4102
CLOSE TO PIN 10
PWR_DCBATOUT_5V3D3V
D
D
D
D
GAP-CLOSE-PWR-3-GP
2
PG4131
1
84.00172.037
1
2
3
4
GAP-CLOSE-PWR-3-GP
2
PG4129
1
PC4129
SC10U25V6KX-1GP
2
1
PC4115
SC10U25V6KX-1GP
1
2
PC4114
SC10U25V6KX-1GP
Design Current = 16A

25.1A<OCP< 29.3A
PT4102
ST220U6D3VDM-20GP
PG4126
1
GAP-CLOSE-PWR-3-GP
2
5V_PWR
PC4113
SCD1U50V3KX-GP
1
2
PG4124
1
PT4105
SE100U25VM-L1-GP
2PC4106
SC1U25V3KX-1-GP
20101230 A00:
Change PR4106 to 0R0603 short pad.
S
S
S
G
GAP-CLOSE-PWR-3-GP
2
PU4103
DY
GAP-CLOSE-PWR-3-GP
2
GAP-CLOSE-PWR-3-GP
2
3rd = 74.07716.A7F
D
D
D
D
PG4122
1
PC4112
SC1KP50V2KX-1GP
GAP-CLOSE-PWR-3-GP
2
PG4119
1
GAP-CLOSE-PWR-3-GP
2
PG4117
1
2
DY0R2J-2-GP
1
PR4108
PR4105
0R2J-2-GP
PWR_5V3D3_AGND
PWR_DCBATOUT_5V3D3V
PR4107
0R2J-2-GP
DY
PWR_5V3D3V_VIN
20110118 A00:
Remove PU4101,PU4106 and add PT4105 100uF at PWR_DCBATOUT_5V3D3V.
Vout(5V)=VFB1*(1+R1/R2)
NC#4
74.09091.J3F
GAP-CLOSE-PWR-3-GP
2
VOUT
+5V_VCC1
PG4116
1
PC4104
SCD1U25V3KX-GP
VIN
GND
EN
PG4102
1
5
G9091-330T11U-GP
PR4109
0R2J-2-GP
GAP-CLOSE-PWR-3-GP
2
SC1U25V3KX-1-GP
PG4115
1
1
2
3
2nd = 74.09198.G7F
PC4103
1
2
GAP-CLOSE-PWR-3-GP
2
+5V_VCC1
PC4105
SC1U25V3KX-1-GP
PG4114
1
SC1U10V3KX-3GP
PC4131
1
20101230 A00:
Change PR4103,PR4104 to 0R0805 short pad.
GAP-CLOSE-PWR-3-GP
2
PWR_5V3D3V_VREF3
PG4112
1
PWR_5V3D3V_VREF2
DCBATOUT
PWR_5V3D3V_TONSEL
2
PG4110
1
5V_PWR
GAP-CLOSE-PWR-3-GP
2
2
1
PR4103
0R0805-PAD
2
1
PR4104
0R0805-PAD
5V_S5
PC4102
SC4D7U10V5KX-1GP
2
10R3J-3-GP
20110110 A00:
Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142 to ZZ.CLOSE.001.
PWR_DCBATOUT_5V3D3V
+5V_VCC1
1
PR4102
SKIPSEL
Mode
GND
Auto Skip
TONSEL
Ch1
Ch2
GND
400 kHz
500 kHz
FLOAT/VREF2
OOA.
20110110 A00:
Add PT4104 47uF.
20110112 A00:
Change PT4104 to 100uF.
DCBATOUT
V5IN
PWM Only
PWR_5V3D3_AGND
VREF2 or Float
400 kHz
300 kHz
V5FILT
200 kHz
300 kHz
PT4104
SE100U25VM-L1-GP
79.10712.L02
2nd = 79.10712.6JL
1A= 40mils
0.5A= 20mils
0.375A= 15mils
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
TPS51427_5V/3D3V
Document Number
Rev
A00
Nirvana 13
Sheet
1
41
of
103
SSID = CPU.Regulator
3D3V_PW R
5V_S5
1
2
1 PR4208
1 PR4210
4
3
PW R_VCORE_R_OSC
PW R_VCORE_R_REF1
PW R_VCORE_R_REF2
41
22
26
R_OSC
R_REF1
R_REF2
2
2
2
2
2
2
2
PW R_VCORE_R_SEL0
PW R_VCORE_R_SEL1
PW R_VCORE_R_SEL2
PW R_VCORE_R_SEL3
PW R_VCORE_R_SEL4
PW R_VCORE_R_SEL5
PW R_VCORE_R_SEL6
2
1
48
47
46
45
44
R_SEL0
R_SEL1
R_SEL2
R_SEL3
R_SEL4
R_SEL5
R_SEL6
VCLK
VDIO
VR_ENABLE
VR_TT#
VR1_READY
VR2_READY
ALERT#
PW R_VCORE_SPHASE_0 (43)
PW R_VCORE_SPHASE_1 (43)
PR4255
61K9R2F-GP
SPHASE_GFX (44)
H_CPU_SVIDCLK (8)
H_CPU_SVIDDAT (8)
6
10
8
9
D85V_PW RGD (48)

H_PROCHOT# (5,27,40)
IMVP_PW RGD (27,36)
PW R_VCORE_VR2_DELAY
NC#17
NC#20
17
20
GND
GND
GND
49
11
3
20101223 A00:
Power/Brian:
Change PU4201 to 74.01316.F33.
1
2H_PROCHOT#
PR4224 100KR2F-L1-GP
C
PR4256
NTC-220K-2-GP
NTCG104QH224HT
VR_SVID_ALERT# (8)
PR4233
H_PROCHOT#
2PW R_VCORE_TEMP_SENSE1_R
1
2
PR4223 100KR2F-L1-GP
5K76R2F-2-GP
74.01316.F33
NTCG104QH224HT
PR4239
NTC-220K-2-GP
1D05V_PW R
1D05V_PW R
PW R_VCORE_DB1
DB1_GFX
B
20101012
GND_1316
TEMP_SENSE_GFX_R
5
4
VT1316MAFQX-041-GP
GND_1316
1PR4254
2
0R0402-PAD
PW R_VCORE_SPHASE_0
PW R_VCORE_SPHASE_1
TEMP_SENSE_GFX
20101227 A00:
Change PR4217~PR4220,PR4254 to 0R 0402 pad.
SPHASE1_0
SPHASE1_1
SPHASE1_2
SPHASE2
40
39
38
34
VSSSENSE (8)
VCCSENSE (8)
VSS_AXG_SENSE (9)
VCC_AXG_SENSE (9)
PW R_VCORE_TEMP_SENSE1
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
2
2
2
2
PR4245
158KR2F-GP
PR4244
221KR2F-GP
PR4243
48K7R3F-1-GP
5V_S5
2
2
2
29
30
1
1
1
1
PR4246
475KR3F-GP
IDES1_N
IDES1_P
IDES2_N
IDES2_P
TEMP_SENSE1
TEMP_SENSE2
PR4217
PR4218
PR4219
PR4220
24
23
27
28
PW R_VCORE_SENSE1PW R_VCORE_SENSE1+
PW R_VCORE_SENSE2PW R_VCORE_SENSE2+
DB10
DB11
DB12
DB20
DB21
DB22
14
13
15
16
IMON1
IMON2
37
36
35
33
32
31
SENSE1SENSE1+
SENSE2SENSE2+
21
25
18
19
PW R_VCORE_IMON1
PW R_VCORE_IMON2
PW R_VCORE_DCMDRP1
PW R_VCORE_DCMDRP2
DCMDRP1
DCMDRP2
VDD3
VDD3
PR4238
43K2R2F-L-GP
2
23K7R2F-GP
39K2R2F-L-GP
39K2R2F-L-GP
32K4R2F-1-GP
27K4R2F-GP
39K2R2F-L-GP
3K74R2F-GP
130R2F-1-GP
43
42
PW R_VCORE_IDES1_N
PW R_VCORE_IDES1_P
1
PR4225 1
PR4226 1
PR4229
1
PR4231
1
PR4232
1
PR4234
1
PR4235
1
PR4236
1
PR4237
1
PR4201
54D9R2F-L1-GP
VDD5
PW R_VCORE_VDD3
PW R_VCORE_VDD3
SCD047U25V2KX-GP
2
1
PC4219
130KR2F-GP
44K2R2D-GP
44K2R2D-GP
GND_1316
12
SCD047U25V2KX-GP
2
1
PC4218
1
2
(43) PW R_VCORE_IDES1_N
(43) PW R_VCORE_IDES1_P
(44) IDES_N_GFX
(44) IDES_P_GFX
1
2
PG4203
GAP-CLOSE-PW R
PU4201
PW R_VCORE_VDD5
(43) PW R_VCORE_DB0
(43) PW R_VCORE_DB1
(43) PW R_VCORE_DB2
(44)
DB0_GFX
(44)
DB1_GFX
(44)
DB2_GFX
PR4222
8K87R2F-2-GP
GND_1316
PC4201
SCD1U25V3KX-GP
2
1
2
PC4231
SCD022U16V2KX-3GP
2
1
PC4214
SCD022U16V2KX-3GP
2
1
1
2
PR4221
6K98R2-GP
20101231 A00:
Change PR4209,PR4212 to PN4201 10k array resistor.
20110113 A00:
PN4201
SRN10KJ-5-GP
GND_1316
DYPR4216
100R2F-L1-GP-U
DYPR4215
100R2F-L1-GP-U
GND_1316
1D05V_PW R
PC4213
SCD1U25V3KX-GP
2
1
PR4205
1R2F-GP
PR4204
1R2F-GP
3D3V_S0
1D05V_VTT
PW R_VCORE_DCMDRP2
PW R_VCORE_DCMDRP1
5V_S5
PR4250
5K11R2F-L1-GP
PC4229
SC2200P50V2KX-2GP
DY
20101012
PC4228
SC2200P50V2KX-2GP
DY 1KR2F-3-GP
PR4249
1K54R2F-GP
PR4253
DY
1KR2F-3-GP
PQ4203
AO7401-GP
PQ4203_G G
PQ4202_D
PR4207
DY100R2F-L1-GP-U
PR4251
PW R_VCORE_IDES1_P
PQ4201_D
DY
GND_1316
GND_1316
PW R_VCORE_DB1 (43)
PQ4201
PC4428
DYSC4700P50V2KX-1GP
DMN601K-7-GP
PQ4202
DY
PQ4201_G 2
DY
2
DY
Wistron Corporation
D85V_PW RGD (48)

0R2J-2-GP
PC4211
SC220P50V2JN-3GP
Title
Size
A3
Date:
<Core Design>
PR4240
DMN601K-7-GP
VT1316+1317_CPU_CORE(1/3)
Document Number
Rev
Nirvana 13
A00
Sheet
1
42
of
103
PR4203
PC4203
SC4700P50V2KX-1GP
PW R_VCORE0_IDES_P_1
PC4207
SCD1U25V3KX-GP
2
1
2PW R_VCORE_IDES1_N_2
SC1KP50V2KX-1GP
1
PC4202
PC4210
SC1U10V2KX-1GP
2
1
PC4208
SC10U6D3V3MX-GP
2
1
11K3R2F-2-GP
6K19R2F-GP
5V_S5
2
PC4206
SC1U10V2KX-1GP
2
1
PC4209
SC10U6D3V3MX-GP
2
1
PC4205
SC10U6D3V3MX-GP
2
1
PR4202
PC4204
SC10U6D3V3MX-GP
2
1
C6
C5
C4
E4
E5
E6
G4
G5
G6
J4
J5
J6
PR4206
3K09R2F-1-GP
11K3R2F-2-GP
PC4212
1
2PW R_VCORE_IDES0_P_1
(42) PW R_VCORE_DB0
(42) PW R_VCORE_DB1
(42) PW R_VCORE_DB2
SC1KP50V2KX-1GP
(42) PW R_VCORE_SPHASE_0
PR4211
1
PC4215
SCD1U25V3KX-GP
74.01317.B3Z
VCC_CORE
20101231 A00:
Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.
VT1317SFCX-001-GP
GAP-CLOSE-PW R
PC4217
SC4700P50V2KX-1GP
PL4201
IND-240NH-GP
2
PC4226
SCD1U25V3KX-GP
2
1
68.2415N.101
PR4248
1
2
6K19R2F-GP
PW R_VCORE1_IDES_N
PW R_VCORE1_IDES_P
11K3R2F-2-GP
PC4227 1
SC1KP50V2KX-1GP
2PW R_VCORE_IDES1_P_1
(42) PW R_VCORE_DB0
(42) PW R_VCORE_DB1
(42) PW R_VCORE_DB2
(42) PW R_VCORE_SPHASE_1
A5
A4
IDES_N
IDES_P
A6
A1
B1
DB0
DB1
DB2
B6
SPHASE
A3
B3
B4
B5
AVDD
AGND
AGND
AGND
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PU4203
PR4247
C6
C5
C4
E4
E5
E6
G4
G5
G6
J4
J5
J6
PR4241
3K09R2F-1-GP
PC4225
SC1U10V2KX-1GP
2
1
PC4224
SC1U10V2KX-1GP
2
1
PW R_VCORE1_IDES_P_1
PC4223
SC10U6D3V3MX-GP
2
1
PC4220
SC10U6D3V3MX-GP
2
1
5V_S5
GND_1317S_1
PW R_VCORE_IDES1_P
PG4201
1
2
11K3R2F-2-GP
2PW R_VCORE_IDES1_N_1
SC1KP50V2KX-1GP
1
PC4216
AVDD
AGND
AGND
AGND
PW R_VCORE_VX0
PC4222
SC10U6D3V3MX-GP
2
1
1
(42) PW R_VCORE_IDES1_P
PW R_VCORE_IDES1_N
SPHASE
A3
B3
B4
B5
H1
H2
H3
H4
H5
H6
D1
D2
D3
D4
D5
D6
F6
F5
F4
F3
F2
F1
PR4227
2
6K19R2F-GP
(42) PW R_VCORE_IDES1_N
B6
VX#H1
VX#H2
VX#H3
VX#H4
VX#H5
VX#H6
VX#D1
VX#D2
VX#D3
VX#D4
VX#D5
VX#D6
VX#F6
VX#F5
VX#F4
VX#F3
VX#F2
VX#F1
PC4221
SC10U6D3V3MX-GP
2
1
PR4230
DB0
DB1
DB2
A2
B2
10R2J-2-GP
A6
A1
B1
AGND
AGND
1PU4202_AVDD
IDES_N
IDES_P
5V_S5
A5
A4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
6K19R2F-GP
PW R_VCORE0_IDES_N
PW R_VCORE0_IDES_P
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
PR4214
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PU4202
PR4213
1PU4203_AVDD
74.01317.B3Z
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10R2J-2-GP
H1
H2
H3
H4
H5
H6
D1
D2
D3
D4
D5
D6
F6
F5
F4
F3
F2
F1
PW R_VCORE_VX1
VT1317SFCX-001-GP
<Core Design>
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
A2
B2
5V_S5
AGND
AGND
PR4242
VX#H1
VX#H2
VX#H3
VX#H4
VX#H5
VX#H6
VX#D1
VX#D2
VX#D3
VX#D4
VX#D5
VX#D6
VX#F6
VX#F5
VX#F4
VX#F3
VX#F2
VX#F1
PC4230
SCD1U25V3KX-GP
Wistron Corporation
PG4202
1
2
Title
GAP-CLOSE-PW R
Size
A3
GND_1317S_2
Date:
5
VT1316+1317_CPU_CORE(2/3)
Document Number
Rev
Nirvana 13
A00
Sheet
1
43
of
103
PR4402
PR4403
2
11KR2F-L-GP
3K24R2F-GP
IDES_N_GFX_1
PC4414
C6
C5
C4
E4
E5
E6
G4
G5
G6
J4
J5
J6
PC4421
SCD1U25V3KX-GP
2
1
PC4419
SC1U10V2KX-1GP
2
1
PC4418
SC10U6D3V3MX-GP
2
1
PC4420
SC1U10V2KX-1GP
2
1
PC4426
SC22U6D3V5MX-2GP
2
1
PC4412
SC22U6D3V5MX-2GP
2
1
PC4411
SC22U6D3V5MX-2GP
2
1
DY
PC4410
SC22U6D3V5MX-2GP
2
1
1
2
PG4401
GAP-CLOSE-PW R
PC4417
SC10U6D3V3MX-GP
2
1
DY
PC4409
SC22U6D3V5MX-2GP
2
1
VT1317SFCX-001-GP

PC4408
SC22U6D3V5MX-2GP
2
1
74.01317.B3Z
68.R1010.10T
PC4407
SC22U6D3V5MX-2GP
2
1
AVDD
AGND
AGND
AGND
PW R_AXG_VX
1
2
IND-D1UH-26-GP
PC4425
SC22U6D3V5MX-2GP
2
1
SPHASE
A3
B3
B4
B5
H1
H2
H3
H4
H5
H6
D1
D2
D3
D4
D5
D6
F6
F5
F4
F3
F2
F1
PC4406
SC22U6D3V5MX-2GP
2
1
B6
PC4416
SC10U6D3V3MX-GP
2
1
PC4415
SC10U6D3V3MX-GP
2
1
PC4427
SCD1U25V3KX-GP
DB0
DB1
DB2
1PWR_AXG_AVDD
(42) SPHASE_GFX
A6
A1
B1
VX#H1
VX#H2
VX#H3
VX#H4
VX#H5
VX#H6
VX#D1
VX#D2
VX#D3
VX#D4
VX#D5
VX#D6
VX#F6
VX#F5
VX#F4
VX#F3
VX#F2
VX#F1
PC4424
SC22U6D3V5MX-2GP
2
1
11KR2F-L-GP
(42) DB0_GFX
(42) DB1_GFX
(42) DB2_GFX
IDES_N
IDES_P
0.12UH~0.15UH
PC4401
SC22U6D3V5MX-2GP
2
1
PW R_AXG_IDES_N A5
PW R_AXG_IDES_P A4
PL4401
PC4405
SC22U6D3V5MX-2GP
2
1
2
3K24R2F-GP
PU4401
PC4423
SC22U6D3V5MX-2GP
2
1
20101012
VCC_GFXCORE
PC4404
SC22U6D3V5MX-2GP
2
1
(42) IDES_P_GFX
PR4405
PC4403
SC22U6D3V5MX-2GP
2
1
PC4402
SC22U6D3V5MX-2GP
2
1
PR4406
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
SC2700P50V2KX-1-GP
PR4401
10R2J-2-GP
IDES_P_GFX_1
5V_S5
PR4404
3K09R2F-1-GP
2
1
PW R_AXG_IDES_P_1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SC2700P50V2KX-1-GP
PC4422 1
5V_S5
SC4700P50V2KX-1GP
AGND
AGND
PC4413 1
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
A2
B2
20101012
(42) IDES_N_GFX
GND_1317S_3
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
VT1316+1317_AXG_CORE(3/3)
Document Number
Rev
Nirvana 13
A00
Sheet
1
44
of
103
DCBATOUT
PG4520
1
GAP-CLOSE-PW R
2
PG4512
1
GAP-CLOSE-PW R
2
PG4524
1
GAP-CLOSE-PW R
2
PG4526
1
GAP-CLOSE-PW R
2
PW R_1D05V_DCBATOUT
1
2
1
2
1
2
1
2
5
6
7
8
4
3
2
1
1
PR4523
9K76R2F-1-GP
PT4509
DY
2
1
2
PT4502
ST330U2VDM-4-GP
2
2
79.33719.20L
2nd = 77.C3371.13L
PW R_1D05V_VFB
PC4530
SC560P50V-GP
DY
VTT_SENSE_L
PC4528
PR4513
20KR2F-L-GP
PG4517
1
GAP-CLOSE-PW R
2
PG4516
1
GAP-CLOSE-PW R
2
PG4513
1
GAP-CLOSE-PW R
2
PG4514
1
GAP-CLOSE-PW R
2
PG4515
1
GAP-CLOSE-PW R
2
PG4518
1
GAP-CLOSE-PW R
2
PG4519
1
GAP-CLOSE-PW R
2
PG4521
1
GAP-CLOSE-PW R
2
PG4522
1
GAP-CLOSE-PW R
2
PG4523
1
GAP-CLOSE-PW R
2
PG4525
1
GAP-CLOSE-PW R
2
PG4527
1
GAP-CLOSE-PW R
2
VSS_SENSE_L
20101224 A00:
Rename PTC4502,PTC4509 to PT4502~PT4509.
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
1PWR_1D05V_SNUB 2
SIR460DP-T1-GE3-GP
84.00460.037
1D05V_VTT
1
PR4516
100R2F-L1-GP-U
PR4522
2D2R5F-2-GP
DY
IND-D56UH-27-GP
1
5
6
7
8
PU4504
4
3
2
1
1
2
1
PC4527
S
S
S
G
PL4502
5V_S5
PW R_1D05V_DRVL
1D05V_PW R
SCD1U25V3KX-GP
PC4523
DY
PC4525
SCD1U25V3KX-GP
1

15.6A<OCP< 18.3A
SCD1U10V2KX-4GP
TPS51218DSCR-GP-U1
PW R_1D05V_VBST 1 PR4518 2PW R_1D05V_VBST_R

2
PW R_1D05V_DRVH 2D2R3-1-U-GP
PW R_1D05V_SW
SC1U10V2KX-1GP
SC1KP50V2KX-1GP
Mag. 0.56uH 10*10*4

DCR=1.6~1.8mohm
Idc=25A, Isat=40A
84.00172.037
D
D
D
D
PR4520
470KR2F-GP
11
10
9
8
7
6
SCD1U25V3KX-GP
20101224 A00 Modify:

Change PR4514 to 0ohm short pad from 0402
and un-stuff PC4523 at X-Build stage.
GND
VBST
DRVH
SW
V5IN
DRVL
1D05V_PW R
PC4531
SIR172DP-T1-GE3-GP
PU4503
PGOOD
TRIP
EN
VFB
CCM
PC4506
SC4D7U25V5KX-GP
PR4514 1
1
PW R_1D05V_TRIP 2
1
2
2 0R0402-PAD PW R_1D05V_EN
3
PW R_1D05V_VFB 4
75KR2F-GP
PW R_1D05V_CCM 5
PC4529
SC4D7U25V5KX-GP
10KR2J-3-GP
(37,48) 1.05VTT_PW RGD
PR4501
PC4526
SC4D7U25V5KX-GP
Id=14.3A
Qg=9.2~14nC
Rdson=11~14mohm
S
S
S
G
D
D
D
D
PU4502
PR4519
TPS51218 for 1D05V_VTT
3D3V_S0
PW R_1D05V_DCBATOUT
PR4517
100R2F-L1-GP-U
Vout=0.704V*(R1+R2)/R2
1 PR4515 2
0R0402-PAD
VCCIO_SENSE
(8)
VTT_SENSE_L
DY
VSS_SENSE_L
PC4532
SC1000P50V3JN-GP-U
1 PR4510 2
0R0402-PAD
VSSIO_SENSE (8)
<Core Design>
Wistron Corporation
Title
TPS51218_1D05V_VTT
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
45
of
103
SSID = PWR.Plane.Regulator_1p5v0p75v
1D5V_PW R
DCBATOUT
PC4601
SC1U10V3KX-3GP
5V_S5
PW R_1D5V_SW
DRVL
11
TPS51216_DRVL
PGND
10
3
1
VTTGND
1
2
2
1
2
1
GAP-CLOSE-PW R
1
2
PG4612
GAP-CLOSE-PW R
GND
TPS51216RUKR-GP
DY
4
3
2
1
DY
PC4622
SC330P50V2KX-3GP
GAP-CLOSE-PW R
PG4602
1
2
+0D75V_DDR_P
0D75V_S0
PG4601
1
2
1
2
PG4616
GAP-CLOSE-PW R
C
1
2
PG4617
GAP-CLOSE-PW R
1
2
PG4618
GAP-CLOSE-PW R
20101224 A00:
Rename PTC4601,PTC4602 to PT601~PT4602.
1
2
PG4619
GAP-CLOSE-PW R
1
2
PG4620
GAP-CLOSE-PW R
1
2
PG4621
GAP-CLOSE-PW R
20101230 A00:
Follow the standard schematics: remove PR4615,PR4616.
1
2
PG4622
GAP-CLOSE-PW R
GAP-CLOSE-PW R
S5
VDDR
VTTREF
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
Off(Hi-Z)
On
S4/S5
Lo
Lo
Off
Off
Off
PW R_1D5V_VTTREF 1 PR4611 2
0R0603-PAD
Frequency
200k ohm
400kHz
100k ohm
300kHz
68k ohm
300kHz
47k ohm
400kHz
1
2
PG4624
GAP-CLOSE-PW R
DDR_VREF_S3
MODE
PR5003
1
2
PG4623
GAP-CLOSE-PW R
VTT
(19,27) PM_SLP_S4#
Discharge Mode
1 PR4607 2
0R0402-PAD
20101224 A00 Modify:
Change PR4607 to short pad at X-Build.
1
2
PG4625
GAP-CLOSE-PW R
PW R_1D5V_EN
S3
DY
PC4606
SCD1U10V2KX-5GP
State
1
2
PG4613
GAP-CLOSE-PW R
1
2
PG4615
GAP-CLOSE-PW R
PT4601
1
2
1
2
PC4621
SCD1U10V2KX-4GP
TPS51216_PHS_SET
PR4612
2D2R5F-2-GP
PC4620
SC4D7U6D3V5KX-3GP
DY
PT4602
1D5V_PW R
74.51216.073
IND-D68UH-51-GP-U
PU4603
1
2
PG4614
GAP-CLOSE-PW R
PG4607
GAP-CLOSE-PWR-3-GP
VTT
VTTS
PC4610
SCD22U6D3V2KX-1GP
21 GND
+0D75V_DDR_P
SC10U6D3V5MX-3GP
VTTREF
PW R_1D5V_VDDQS
PC4617
2
1
PC4616
2
1
SC10U6D3V5MX-3GP
VTTIN
PC4615
2
1
SCD1U10V2KX-4GP
200KR2F-L-GP
2
1
PR4602
82KR2F-1-GP
2
1
47KR2F-GP
PR4608
2
1
PC4602
SCD01U16V2KX-3GP
2
1
PR4606
240R2F-1-GP
PR4601
2
1
1
2
PR4601_1
PW R_1D5V_VTTREF5
VDDQS
1
2
PG4611
GAP-CLOSE-PW R
1D5V_PW R
TRIP
GAP-CLOSE-PW R
PG4606
2
1
PL4601
PWR_1D5V_VDDQS
PW R_1D5V_TRIP 18
1
2
PG4610
GAP-CLOSE-PW R
84.00172.037
SIR460DP-T1-GE3-GP
S
S
S
G
PC4603
SCD1U25V3KX-GP
MODE
GAP-CLOSE-PW R
PG4605
2
1
SE220U2VDM-8GP
PW R_1D5V_MODE 19
1
2
PG4609
GAP-CLOSE-PW R

22.71A<OCP< 26.84A
SIR172DP-T1-GE3-GP
1
2
PG4608
GAP-CLOSE-PW R
GAP-CLOSE-PW R
PG4604
2
1
SE220U2VDM-8GP
REFIN
PC4614
SC4D7U25V5KX-GP
13
PC4613
SCD1U50V3KX-GP
SW
PC4612
SC10U25V6KX-1GP
PW R_1D5V_DRVH
PC4611
SC10U25V6KX-1GP
14
D
D
D
D
PW R_1D5V_REFIN 8
2
1
DRVH
PR4603
10KR2F-2-GP
PR4605
PW R_1D5V_VBST1
2
2D2R3J-2-GP
VREF
15
PW R_1D5V_VREF 6
VBST
EN/PSV
VTTEN
16
PC4604
SC1U10V3KX-3GP
17
PW R_1D5V_EN
4
3
2
1
0D75V_EN
12
5
6
7
8
(37) 0D75V_EN
PC4619
SCD1U25V3KX-GP
V5IN
S
S
S
G
PGOOD
PR4605_2
PU4601
20
PU4602
D
D
D
D
PR4604
20KR2J-L2-GP
PC4609
SC10U25V6KX-1GP
3D3V_S0
+PW R_SRC_1D5V
5
6
7
8
+PW R_SRC_1D5V
PG4603
1
1D5V_S3
Tracking Discharge
Non-tracking Discharge
<Core Design>
Wistron Corporation
Title
TPS51116_+1.5V_SUS
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
46
of
103
SSID = PWR.Plane.Regulator_1p8v
1A= 40mils
1.5A= 60mils
0.5A= 20mils
3D3V_S5
PW R_1D8V_VIN
PU4701
10
FB
VBST
2
8
RES
MODE
PW R_1D8V_VBST
5
6
7
PW R_1D8V_SW
68.2R210.20B
1
PC4717
SC2200P50V2KX-2GP
TPS51311RGTR-GP
74.51311.073
GAP-CLOSE-PW R
SW#5
SW#6
SW#7
1D8V_S0
PG4704
1
2
DY
2
PC4703
SC1U6D3V2KX-GP
PGOOD
EN
PW R_1D8V_RUN
PL4701
IND-2D2UH-46-GP-U
3
1
PC4721
SC10U6D3V5MX-3GP
PC4719
SC10U6D3V5MX-3GP
1D8V_EN
1 PR4706 2PW R_1D8V_VBST_1

0R0603-PAD
PC4716
SCD1U25V3KX-GP
20KR2J-L2-GP
COMP
PC4715
SC10U6D3V5MX-3GP
2
10KR2J-3-GP
PC4708
SCD1U25V3KX-GP
PR4702
20KR2F-L-GP
2
1
1
PR4715
15
16

(19,27,36,37) PM_SLP_S3#
PR4717
57K6R2F-GP
DY
PW R_1D8V_PS
1
PR4707
PGND
PGND
1PWR_1D8V_FB_2
2
3D3V_S0
PW R_1D8V_FB
2
SC2200P50V2KX-2GP
PW R_1D8V_COMP
2PW R_1D8V_FB_1 1
PC4718
5K9R2F-GP
PR4705
1
1
AGND
PGND
13
14
11
17
VIN
VIN
VDD
SC100P50V2JN-3GP
2
PC4702
1
12
C
2
PG4701
GAP-CLOSE-PW R
2
PG4702
GAP-CLOSE-PW R
PC4720
SC22U6D3V5MX-2GP
PC4707
SCD1U25V3KX-GP
3D3V_S5
PG4705
2
GAP-CLOSE-PW R
PG4706
1
2
GAP-CLOSE-PW R
PR4718
40D2R2F-GP
PW R_1D8V_FB
PR4716
10KR2F-2-GP
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
TPS51311_ +1.8V_RUN
Document Number
Nirvana 13
Rev
A00
Sheet
1
47
of
103
TPS51461 for VCCSA

3D3V_S0
1
5V_S5
VCCSA_PWM PR4809
4K7R2J-2-GP
D85V_PWRGD
(42)
DY 2
PR4812
1
1KR2F-3-GP
VCCSA_PWM
PWR_VCCSA_VID1
1 PR4804 2
0R0402-PAD
1 PR4805 2
0R0402-PAD
PWR_VCCSA_VID0
PWR_VCCSA_EN
VCCSA_SEL
(9)
H_FC_C22
(9)
VCCSA_PWM
1 PR4801 2
0R0402-PAD
1.05VTT_PWRGD
VCCSA_PWM
(37,45)
1 PR4808 2
0R0402-PAD
VCCSA_PWM
PWR_VCCSA_PGOOD
PC4816
VCCSA_PWM
SC2D2U10V3KX-1GP
VCCSA_PWM
SC1U10V2KX-1GP
PR4806
1R2F-GP
VCCSA_PWM PC4814
PWR_VCCSA_V5DRV
1
2
1
2
1
2
1
1PWR_VCCSA_SNUB
2
2
1
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
1
2
3
4
5
6
PC4812
SCD1U25V3KX-GP
DY
VCCSA_PWM
PC4818
DY SC560P50V-GP
2
PC4801
VCCSA
APL5916 for VCCSA
1D05V_VTT
0.675V
VCCSA_PWM
SC22U6D3V5MX-2GP
0.725V
VCCSA_PWM
0.8V
SC22U6D3V5MX-2GP
PC4811
PC4810
0.9V
(9)
VCCSA_PWM
VCCUSA_SENSE
VCCSA_PWM
DY
PWR_VCCSA_COMP_1
VID1
0D85V_S0
1 PR4810 2
0R0402-PAD
VCCSA_PWM PC4806
SCD01U50V2KX-1GP
PR4802
VCCSA_PWM 4K99R2F-L-GP
VID0
1 VCCSA_PWM
2
100R2F-L1-GP-U
SC22U6D3V5MX-2GP
PWR_VCCSA_COMP
PWR_VCCSA_VREF
PWR_VCCSA_VOUT
PWR_VCCSA_SLEW
DY
68.R4710.10M
PR4811
SC22U6D3V5MX-2GP
PR4803
DY 2D2R5F-2-GP
74.51461.043
PC4807
PL4801
1 VCCSA_PWM
2
IND-D47UH-22-GP
SC22U6D3V5MX-2GP
0D85V_S0
VCCSA_PWM
PWR_VCCSA_SW
PC4809

6.6A<OCP< 7.8A
PC4805
SCD1U25V3KX-GP
PWR_VCCSA_BST 1 PR4807 2 PWR_VCCSA_BST_R

1
2
VCCSA_PWM
0R0603-PAD
12
11
10
9
8
7
SC22U6D3V5MX-2GP
TPS51461RGER-GP
PGND
PGND
BST
PGND
SW#11
VIN
SW#10
VIN VCCSA_PWM SW#9
VIN
SW#8
GND
SW#7
PC4808
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SCD1U25V3KX-GP
SC4D7U25V5KX-GP
PC4803
PC4815
PC4813
PC4819
VCCSA_PWM
VCCSA_PWM VCCSA_PWM VCCSA_PWM
19
20
21
22
23
24
25
GND
VREF
COMP
SLEW
VOUT
MODE
5V_S5
PC4804
SC1U6D3V2KX-GP
18
17
16
15
14
13
DY
U4801
PC4817
VCCSA_PWM SC3300P50V3KX-1GP
5V_S5
R1
1
1
PR4815
80K6R2F-GP
PR4816
160KR2F-GP
PQ4801_D
VCCSA_LDO
DY
VCCSA_LDO
PC4821
DY
VCCSA_SEL
(9)
10KR2J-3-GP
PC4826
SCD1U10V2KX-4GP
DY
PR4818
10KR2F-2-GP
DY
DY
2
84.2N702.A3F
2nd = 84.DM601.03F
0.9V
PQ4801
2N7002KDW-GP
VCCSA_PWR
PT4801
ST100U6D3VBM-7GP
PR4813
PQ4801_5
VCCSA_SEL
DY
VCCSA_LDO
3D3V_S0
Vout=0.8*(1+R1/R2)
PC4827
PWR_VCCSA_FB
R2
SC10U6D3V5MX-3GP
74.05916.031
SC10U6D3V5MX-3GP
U4802
APL5916KAI-TRL-GP
PC4823
SC1U6D3V2KX-GP
0D85V_S0
20101224 A00:
Rename PTC4801 to PT4801.
PC4820
VCCSA_LDO
VCCSA_LDO
PR4814
10KR2F-2-GP
FB
VCCSA_LDO
3
4
5
9
Iomax=6A
OCP>9A
VCCSA=0.85V
VIN
VIN
VOUT
VOUT
GND
EN
SC100P50V2JN-3GP
DY
POK
SC10U6D3V5MX-3GP
(37,45) 1.05VTT_PWRGD
PC4822
VCCSA_LDO
2
7
(42) D85V_PWRGD
VCNTL
2
B
PC4824
VCCSA_LDO
R4807
2K2R2J-2-GP
VCCSA_LDO
PC4825
SC1U6D3V2KX-GP
VCCSA_LDO
SB modify 2K2 for no run code
SC10U6D3V5MX-3GP
3D3V_S0
VCCSA_PWM PC4802
SCD22U10V2KX-1GP
PQ4801_G
A
0.8V
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
TPS51461_VCCSA
Document Number
Rev
A00
Nirvana 13
Sheet
1
48
of
103
SSID = VIDEO
DBC_EN_C
R4901 1
33R2J-2-GP
DBC_EN
(22)
SSID = VIDEO
CE_C
R4906
10KR2J-3-GP
CE
(21)
LCD POWER for ROSA
DY
DY
R4912
10KR2J-3-GP
LVDS CONNECTOR
R4911 1
33R2J-2-GP
DCBATOUT_LCD
LCD1
31
NP1
83.1R504.A8F
2nd = 83.1R504.B8F
PD4901
1 R4907
DY
IN#4
G5285T11U-GP
74.05285.07F
DY
IN#5
2nd = 74.09724.09F
2
100KR2J-1-GP
BLON_OUT_C
LCD_TST_C
TP4904TPAD14-GP 3D3V_S0
LCDVDD
0R0402-PAD
EN
GND
OUT
LVDS_VDD_EN
R4951
100KR2J-1-GP
LVDS_DDC_DATA_R (17,97)
LVDS_DDC_CLK_R (17,97)
ENVDD
4
3
LVDS_DDC_CLK_R
LVDS_DDC_DATA_R
C4907
SC1U10V3KX-3GP
1
2
83.R2003.E81
2ND = 83.00054.Q81
SRN2K2J-1-GP
RN9403
LVDSA_DATA0_R
LVDSA_DATA0#_R
D4901
LVDSA_DATA1_R
LVDSA_DATA1#_R
LCD_TST_C
(27) LCD_TST_EN
LCDVDD_EN
3D3V_S0
(29,97)
(29,97)
1
2
3
R4904
TP4903TPAD14-GP
C4908
AUD_DMIC_CLK
AUD_DMIC_IN0
(17) LVDS_VDD_EN
USB_PN12 (18)
USB_PP12 (18)
3D3V_CAMERA_S0
2
R4908 2
R4909
3D3V_S0
U4901
BAT54CPT-GP
L_BKLT_CTRL (17)
R4905
49K9R2F-L-GP
USB_CAMERA#
1
USB_CAMERA 0R2J-2-GP1
0R2J-2-GP
LVDSA_CLK_R
LVDSA_CLK#_R
CE_C
LVDSA_DATA2_R
LVDSA_DATA2#_R
LCDVDD
BLON_OUT_C
A
2 R4902 1
SD103AWS-1-GP 33R2J-2-GP
BLON_OUT_C_1
LCD_BRIGHTNESS
DBC_EN_C
SCD1U10V2KX-5GP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RN4901
1
2
4
3
BLON_OUT (27)
LCD_TST (27)
PS-CON30-GP
20.F1816.030
C4902
SC1U6D3V2KX-GP
NP2
32
C4901
SCD1U10V2KX-5GP
SRN100J-3-GP
CAMERA and DIGITAL MIC PIN DEFINE!
DCBATOUT_LCD
20101227 A00:
Change R4908,R4909,R4903,R4910,R4913~R4916
R4917,R4918 to 0R 0402 pad.
20110111 A00:
Change R4908,R4909,R4903,R4910,R4913~R4916
R4917,R4918 to 0R 0402 reisstors.
BLON_OUT_C_1
LVDSA_DATA2_R
LVDSA_DATA2#_R
1 R4903
1 R4910
2 0R2J-2-GP
2 0R2J-2-GP
LVDSA_DATA2 (17)
LVDSA_DATA2# (17)
LVDSA_DATA1_R
LVDSA_DATA1#_R
1 R4913
1 R4914
2 0R2J-2-GP
2 0R2J-2-GP
LVDSA_DATA1 (17)
LVDSA_DATA1# (17)
LVDSA_DATA0_R
LVDSA_DATA0#_R
1 R4915
1 R4916
2 0R2J-2-GP
2 0R2J-2-GP
LVDSA_DATA0 (17)
LVDSA_DATA0# (17)
LVDSA_DATA2_R
LVDSA_DATA2#_R
EC4906 1
EC4907 1
DY2 SC10P50V2JN-4GP
DY2 SC10P50V2JN-4GP
LVDSA_DATA1_R
LVDSA_DATA1#_R
EC4908 1
EC4909 1
DY2
DY2
SC10P50V2JN-4GP
SC10P50V2JN-4GP
LVDSA_DATA0_R
LVDSA_DATA0#_R
EC4910 1
EC4911 1
DY2
DY2
SC10P50V2JN-4GP
SC10P50V2JN-4GP
LVDSA_CLK_R
LVDSA_CLK#_R
1 R4917
1 R4918
2 0R2J-2-GP
2 0R2J-2-GP
1 R4919 2
100KR2J-1-GP
LVDSA_CLK (17)
LVDSA_CLK# (17)
DCBATOUT
20100104 A00:
Remove TR4902.
F4901
69.50007.A31
2nd = 69.50007.A41
1
C4903
SC10U6D3V5KX-1GP
<Core Design>
DY
DY
SC33P50V2JN-3GP
DY
EC4903
SCD1U10V2KX-5GP
20110107 A00:
Change F4902 to 0603 0 ohm.
EC4901 EC4902
DY
2
3D3V_CAMERA_S0
EC4905
SC33P50V2JN-3GP
DY
SC5D6P50V2CN-1GP
2
EC4904
F4902
0R3J-0-U-GP
LCD_BRIGHTNESS
LCD_TST_C
LVDSA_CLK#
LVDSA_CLK
Camera Power
1
For EMI request

Close to LVDS connector
SCD1U50V3KX-GP
2
SC1KP50V2KX-1GP
3D3V_S0
POLYSW -1D1A24V-GP-U
C4905
SC5D6P50V2CN-1GP
2
2
C4904
Wistron Corporation
Title
Size
A3
Date:
LCD/Inverter Connector
Document Number
Nirvana 13
Sheet
Rev
A00
49
of
103
5V_S0
500mA
5V_CRT_S0
5V_CRT_S0_R
Place closer
D5001
F5001
FUSE-1D1A6V-4GP-U
83.R5003.C8FCH551H-30PT-GP
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
69.50007.691
2nd = 69.50007.771
R5006
1 DY
CRT1
16
0R3J-0-U-GP
CRT_G
C5013
SCD01U16V2KX-3GP
L5003
CRT_HSYNC_CON
14
CRT_VSYNC_CON
15
CRT_DDCCLK_CON
D-SUB-15-81-GP
C5006
SC10P50V2JN-4GP
2
1
CRT_DDCDATA_CON
CRT_DDCCLK_CON
DY
DY
DY
C5008
SC100P50V2JN-3GP
2
1
D5002
BAV99PT-GP-U
DY
2
CRT_VSYNC_CON
C5009
SC18P50V2JN-1-GP
2
1
3
D5003
BAV99PT-GP-U
DY
CRT_HSYNC_CON
3D3V_S0
C5011
SC100P50V2JN-3GP
D5004
BAV99PT-GP-U
DY
1
CRT_R
CRT_G
CRT_B
C5005
SC10P50V2JN-4GP
2
1
DY
C5004
SC10P50V2JN-4GP
2
1
DY
C5003
SC10P50V2JN-4GP
2
1
C5002
SC10P50V2JN-4GP
2
1
C5001
SC10P50V2JN-4GP
2
1
R5003
150R2F-1-GP
2
1
R5002
150R2F-1-GP
2
1
R5001
150R2F-1-GP
2
1
DY
CRT_DDCDATA_CON
13
17
CRT_B
1
2
FCM1608CF-220T05-GP
CRT_BLUE
(17) CRT_BLUE
12
C5010
SC18P50V2JN-1-GP
2
1
L5002
1
2
FCM1608CF-220T05-GP
CRT_GREEN
(17) CRT_GREEN
CRT_B
1
2
FCM1608CF-220T05-GP
11
7
2
8
3
9
4
10
5
CRT_G
5V_CRT_S0_R
CRT_R
(17) CRT_RED
6
1
CRT_R
L5001
CRT_RED
DY
CRT DDCDATA & DDCCLK level shift

B
3D3V_S0
RN5007
SRN2K2J-1-GP
2
1
2
1
CRT Hsync & Vsync level shift
5V_CRT_S0
3D3V_S0
RN5003
SRN2K2J-1-GP
RN5001
4
3
(17) CRT_DDC_DATA
SRN33J-5-GP-U
CRT_DDC_DATA
Q5001
20101231 A00:
Change R5004,R5005 to RN5001 33 ohm array resistor.
3
4
1
2
CRT_HSYNC_CON
CRT_VSYNC_CON
3
4
(17) CRT_HSYNC
(17) CRT_VSYNC
CRT_HSYNC
CRT_VSYNC
CRT_DDCDATA_CON
2N7002KDW -GP
(17) CRT_DDC_CLK
CRT_DDC_CLK
84.2N702.A3F
2nd = 84.DM601.03F
CRT_DDCCLK_CON
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
CRT Connector
Rev
Nirvana 13
Sheet
1
A00
50
of
103
HDMI Level Shifter & CONNECTOR
SSID = VIDEO
Removed HDMI_IN# CIRCUIT

connect to KBC GPIO.
HDMI CONN
HDMI_PLL_GND
HDMI1
23
21
1
R5123
1
R5113
100KR2J-1-GP
DY
HDMI_DATA1_R_C#
HDMI_DATA0_R_C
HDMI_DATA0_R_C#
HDMI_CLK_R_C
HDMI_CLK_R_C#
DDC_CLK_HDMI
DDC_DATA_HDMI
RN5105
2
1
SRN0J-6-GP
3
4
2
1
(17) HDMI_DATA2_R#
(17) HDMI_DATA2_R
RN5104
3
4
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_CLK_R_C#
HDMI_CLK_R_C
HDMI_DATA0_R#_1
HDMI_DATA0_R_1
C5105
C5106
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA0_R_C#
HDMI_DATA0_R_C
HDMI_DATA1_R#_1
HDMI_DATA1_R_1
C5110
C5107
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA1_R_C#
HDMI_DATA1_R_C
HDMI_DATA2_R#_1
HDMI_DATA2_R_1
C5108
C5109
1
1
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
HDMI_DATA2_R_C#
HDMI_DATA2_R_C
SRN0J-6-GP
22.10296.341
8
7
6
5
8
7
6
5
Q5102
PMBS3904-1-GP
2HDMI_HPD_B 1
150KR2J-L1-GP
84.03904.L06
2nd = 84.03904.P11
3rd = 84.03904.T11
HDMI_HPD_E
DY
RN5107
SRN680J-GP
1
R5125
2
0R0402-PAD
HDMI_PCH_DET
(17)
R5112
10KR2J-3-GP
HDMI_PLL_GND
1
2
3
4
20110111 A00:
Change R5101~R5108 to 0 ohm array resistors RN5102~RN5105.
1
2
3
4
RN5106
SRN680J-GP
1
R5111
R5110
200KR2J-L1-GP
Close to HDMI Connector
3D3V_S0
SRN0J-6-GP
2
2
(17) HDMI_DATA1_R#
(17) HDMI_DATA1_R
RN5103
1
1
HPD_HDMI_CON
(17) HDMI_DATA0_R#
(17) HDMI_DATA0_R
C
3
4
C5103
C5104
2
1
HDMI_CLK_R#_1
HDMI_CLK_R_1
RN5102 SRN0J-6-GP
2
3
1
4
(17) HDMI_CLK_R#
(17) HDMI_CLK_R
C5102
SCD1U10V2KX-5GP
SKT-HDMI23-GP
5V_CRT_S0_R
2ND = 84.2N702.031
HDMI_DATA2_R_C#
HDMI_DATA1_R_C
84.2N702.J31
5V_S0
HDMI_DATA2_R_C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
Q5103
2N7002K-2-GP
Removed LEVEL SHIFTER base on DELL feedback spec.

(No support 220MHZ deep color mode, so can be removed
HDMI LEVEL SHIFTER circuit.
DY 0R2J-2-GP
20100723 Swap RN5106 and RN5107 base in the swap report.

5V_CRT_S0_R
4
3
suggestion to stuff 680-ohm for UMA.

3D3V_S0
RN5101
SRN2K2J-1-GP
PCH_HDMI_CLK
6
20101224 A00:
20110111 A00:
Change RN5117 to 0 ohm resistor.
20110118 A00:
Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.
1
2
Q5104
DDC_CLK_HDMI
1
2N7002KDW -GP
PCH_HDMI_DATA
84.2N702.A3F
DDC_DATA_HDMI
2nd = 84.DM601.03F
Already PH on PCH side.(RN1706)

3D3V_S0
PCH_HDMI_CLK
PCH_HDMI_DATA
(17) PCH_HDMI_CLK
(17) PCH_HDMI_DATA
R5109
20KR2J-L2-GP
Routing Guidelines:
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK.
DY
HDMI_OE#
2 R5127
DY 0R2J-2-GP
HDMI_IN#
(27)
<Core Design>
Wistron Corporation
Q5101
2N7002K-2-GP

84.2N702.J31
Title
2ND = 84.2N702.031
DY
Size
A3
HPD_HDMI_CON
Date:
5
HDMI Level Shifter/Connector
Document Number
Nirvana 13
Rev
A00
Sheet
1
51
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
52
of
103
(Blanking)
C
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
LVDS_Switch
Rev
Nirvana 13
A00
Sheet
1
53
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
54
of
103
SSID = User.Interface
ITP Connector
D
H_CPURST# use pull-up Resistor close

ITP connector 500 mil ( max ),
others place near CPU side.
CPU
ITP Connector
TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
ITP
Document Number
Rev
Nirvana 13
A00
Sheet
1
55
of
103
SATA HDD Connector
SSID = SATA
C5605 C5606
HDD1
19
1
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
SC10U10V5ZY-1GP
2
DY
2
SC10U6D3V5KX-1GP
C5604 C5601
DY
5V_S0
3D3V_S0
SATA_TXN0_C
SATA_RXN0_C
20
HDD1_20 1
SATA_TXP0_C
TP5601 TPAD14-GP
4
6
SATA_RXP0_C
7
8
9
3D3V_S0
10
3D3V_S0
12
5V_S0
11
13
5V_S0
(79)
14
15
FFS_INT2
16
17
TPAD14-GP
(21) SATA_TXP0
(21) SATA_TXN0
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
C5616
C5615
(21) SATA_RXN0
(21) SATA_RXP0
1
1
1 C5614
1 C5613
SATA_TXP0_C
SATA_TXN0_C
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
SATA_RXN0_C
SATA_RXP0_C
2
2
TP5602
1HDD1_21
21
18
22
HDD1_22
TP5603 TPAD14-GP
MLX-CONN18A-S1GP
20.K0229.018
AFTP5601
FFS_INT2
SATA Zero Power ODD
ODD Connector
(22) SATA_ODD_PW RGT

U5601
G547F1P81U-GP
SATA_RX- and SATA_RX+ Trace

Length match within 20 mil
S1
Mars:
Exchange ODD and ESATA differential pair each other.
1
SATA_RXN4
SATA_RXP4
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
When the drive is powered off, the FET to the MD/DA pin is ON
(21)
(21)
(21)
(21)
EN/EN#
IN#3
IN#2
GND
OC#
OUT#6
OUT#7
OUT#8
5
6
7
8
ODD_PW R_5V
74.00547.C79
2ND = 74.02191.079
5V_S0
SATA_ODD_PRSNT# (22)
SATA_ODD_DA#_C
ODD_PW R_5V
0R2J-2-GP
DY
1 R5602
Current limit
Active High
typ =>2A
R5605
100KR2J-1-GP
SATA_ODD_DA# (18)
1
2
4
3
RN5601
SATA_ODD_PW RGT
SATA_ODD_DA#
SATA_ODD_DA#_C
<Core Design>
DY
R5604
10KR2J-3-GP
3D3V_S0
Q5601
2N7002KDW -GP
SRN10KJ-5-GP
62.10065.651
2nd = 62.10065.221
C5609
SC10U6D3V5KX-1GP
SATA_TXP4
SATA_TXN4
2SCD01U16V2KX-3GP
2SCD01U16V2KX-3GP
ODD_PWRGT#
9
SKT-SATA7P+6P-50-GP
2 SCD01U16V2KX-3GP
2 SCD01U16V2KX-3GP
C5607 1
C5608 1
P1
P2
P3
P4
P5
P6
C5612 1
C5611 1
SATA_RX4-_C
SATA_RX4+_C
SATA_TXP4_C
SATA_TXN4_C
4
3
2
1
S2
S3
S4
S5
S6
S7
5V_S0
ODD1
Wistron Corporation
84.2N702.A3F
2nd = 84.DM601.03F
SUPPORT ZERO SATA ODD

Title
SATA_ODD_PW RGT
SATA_ODD_DA#
Size
A3
Date:
Document Number
HDD/ODD
Rev
Nirvana 13
A00
Sheet
56
of
103
SSID = ESATA
USB CHARGER
U5702
USB_PP1_R
USB_PN1_R
S0
D+
DGND
A+
GND
S1
Y+
YVDD
A-
11
10
9
8
7
6
PI5USB14550AZEE-GP
CB
1
R5721
2
USBCHARGER_CB0
0R0402-PAD
USB_PP1 (18)
USB_PN1 (18)
5V_S5
C5701
S1
0
1
0
1
Auto
D+/- connects to Y+/-
SCD1U10V2KX-4GP
S0
0
0
1
1
Switch Control Bit:

CB=0 (AM):auto detection charger identification active.
CB=1 (PM):connect DP/DM to TDP/TDM.
73.5USB1.003
(27)
1
2
3
4
5
ESATA CONN
5V_USB1_S3
20100104 A00:
Remove R5718,R5719
(21) SATA_TXP5
(21) SATA_TXN5
(21) SATA_RXP5
(21) SATA_RXN5
USB_PN1_R
TR5701
VBUS
C5707 1
C5708 1
2 SCD01U16V2KX-3GP SATA_TXP5_C 6
2 SCD01U16V2KX-3GP SATA_TXN5_C 7
A+
A-
C5705 1
C5702 1
2 SCD01U16V2KX-3GP SATA_RXP5_C10
2 SCD01U16V2KX-3GP SATA_RXN5_C 9
B+
B-
USB_PP1_C
USB_PN1_C
USB_PP1_R
ESATA1
3
2
D+
D-
DT1
DT2
12
13
GND
GND
GND
GND
GND
GND
GND
GND
4
5
8
11
14
15
16
17
R5722
0R0402-PAD
ESATA1_D1 1
2
USBDET_CON# (27)
1
EC5701
DY2SC5P50V2CN-2GP
USB_PP1_C
SKT-ESATA-USB-11P-6-GP-U
69.10084.081
3
W CM2012F2S-GP-U2
USB_PN1_C
22.10321.W11
2nd = 22.10339.261
AFTP5714
AFTE14P-GP
close to ESATA1
AFTP5716
AFTP5715
AFTP5703
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
5V_USB1_S3
USB_PN1_C
USB_PP1_C
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
USB/ESATA
Rev
Nirvana 13
A00
Sheet
1
57
of
103
SSID = AUDIO
Speaker
Connector
LINE OUT
20101224 A00:
Rename LINEOUT1 to LOUT1.
20101224 A00:
Change R5803,R5804 to 0603 0 ohm pad.
SPK1
40 mils R5803 1
(29) AUD_SPK_L+
2
0R0603-PAD
2
0R0603-PAD
AUD_SPK_L+_C
(29) AUD_HP1_JACK_R2
AUD_HP1_JACK_L2
L5801
1
2AUD_HP1_JACK_L2_R 1
2
BLM18BD601SN1D-GP
0R0402-PAD R5805
AUD_HP1_JACK_L1
AUD_HP1_JACK_R2
L5802
1
2AUD_HP1_JACK_R2_R 1
2
0R0402-PAD R5806
BLM18BD601SN1D-GP
AUD_HP1_JACK_R1
8
7
3
1
4
LOUT1
AUD_HP1_JD#
2
5
6
AFTP5805
EC5804
SCD01U16V2KX-3GP
EC5806
SC1KP50V2KX-1GP
EC5805
SC1KP50V2KX-1GP
EC5802
DY
EC5803
SCD01U16V2KX-3GP
2
1
(29) AUD_HP1_JD#
JST-CON2-33-GP
21.D0300.102
EC5801
DY
MLVG0402220NV05BP-GP-U
MLVG0402220NV05BP-GP-U
R5804
(29) AUD_HP1_JACK_L2
AUD_SPK_L-_C
(29) AUD_SPK_L-
20101224 A00:
0402 0R pad: R5805,R5806.
PHONE-JK383-GP-U
22.10133.K31
1
AFTP5810
AFTP5801
AFTP5802
1
1
AUD_SPK_L-_C
AUD_SPK_L+_C
AFTP5811
AUD_HP1_JD#
AFTP5803
AUD_HP1_JACK_L1
AFTP5804
AUD_HP1_JACK_R1
MIC IN
B
600ohm 100MHz
200mA 0.5ohm DC
MIC_IN_L
(29) MIC_IN_L
R5801
MIC_IN_R
(29) MIC_IN_R
R5802
MICIN1
2
BLM18BD601SN1D-GP
MIC_IN_L_C
2
BLM18BD601SN1D-GP
MIC_IN_R_C
8
7
3
1
4
2
5
6
(29) EXT_MIC_JD#
PHONE-JK383-GP-U
MIC_IN_L_C
AFTP5807
MIC_IN_R_C
AFTP5809
EXT_MIC_JD#
DY
22.10133.K31
SC100P50V2JN-3GP
DY
AFTP5806
SC100P50V2JN-3GP
2
1
EC5807 EC5808
AFTP5808
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Audio Jack
Rev
Nirvana 13
Sheet
1
A00
58
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Reserved
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
Sheet
1
A00
59
of
103
SSID = Flash.ROM
SPI FLASH ROM (4M byte) for PCH
3D3V_S5
3D3V_S5
C6002
1
2
3
4
DY
SPI_HOLD_0#
2
SCD1U10V2KX-5GP
RN6001
SRN4K7J-10-GP
SC10U6D3V5KX-1GP
8
7
6
5
C6001
Notes:
The total SPI interface signal between EC and PCH
cant not exceed 6500mil. The mismatch between
SPI signal must be within 500mil
3D3V_S5
U6001
(21,27) SPI_CS0#_R
(21,27) SPI_SO_R
1
2
3
4
SPI_SO
SPI_W P#
2
33R2J-2-GP
CS#
DO
WP#
VSS
VCC
HOLD#
CLK
DI
8
7
6
5
SPI_CLK_R (21,27)
SPI_SI_R (21,27)
EC6003
Wistron P/N
Manufacturer
2nd = 72.25320.C01
3rd = 72.25P32.C01
Priority
DY DY
SC4D7P50V2CN-1GP
2
72.25Q32.A01
W 25Q32BVSSIG-1-GP
EC6001
SC4D7P50V2CN-1GP
DY
2
EC6002
SC4D7P50V2CN-1GP
1
R6001
Vendor P/N
72.25Q32.A01
WINDBOND
W25Q32BVSSIG
72.25320.C01
MXIC
MX25L3206EM2I-12G
72.25P32.C01
NUMONYX
M25PX32-VMW6F
SSID = RBATT
3D3V_AUX_S5
RTC_AUX_S5
Q6001
+RTC_VCC
RTC1
3
2
83.R0304.B81
2nd = 83.00040.E81
2N7002K-2-GP
R6003
10MR2J-L-GP
R6002
2
1KR2J-1-GP
1
2
NP1
NP2
TPAD14-GP
TP6001
Width=20mils
RTC_PW R
CH715FPT-GP
C6003
SC1U6D3V2KX-GP
RTC_PW R
PWR
GND
NP1
NP2
<Core Design>
BAT-060003HA002M213ZL-GP
Wistron Corporation
62.70014.001
RTC_DET# (22)

TPAD14-GP
TP6002
+RTC_VCC
Title
Q6002
84.2N702.J31
2ND = 84.2N702.031
Size
A3
Date:
Document Number
Flash/RTC
Rev
Nirvana 13
Sheet
1
A00
60
of
103
SSID = USB
Close to ESATA Combo connector
Support 2A
5V_S5
OUT#8
OUT#7
OUT#6
OC#
8
7
6
5
G547F2P81U-GP
C6102
SC1U10V2KX-1GP
GND
IN#2
IN#3
EN/EN#
1
2
3
4
(27) USB_PW R_EN#
C6101
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C6103
at least 80 mil
at least 80 mil
USB POWER SW
Main G547F2P81U-GP P/N:74.00547.A79
5V_USB1_S3
U6101
TC6101
ST100U6D3VAM-3-GP
80.10715.B1L
2nd = 77.C1071.20L
74.00547.A79
2nd = 74.00547.079
USB_OC#0_1 (18)
<Core Design>
A
Wistron Corporation
Title
Size
Document Number
USB2.0 Power SW
Rev
Nirvana 13
Date:
5
A00
Sheet
1
61
of
103
1V_USB30 LDO
D
USB3.0 Host
20101227 A00:
Change R6205 to 0R 0402 pad.
20101228 A00:
20101229 A00:
Remove R6205,R6201 and rename USB3_PWR_ON from USB_PWR_EN.
RT (R6202)
RB (R6203)
VOUT
NEC
2.37k ohm (64.23715.6DL)
7.5k ohm (64.75015.6DL)
TI
11.8k ohm (64.11825.6DL)
30.9k ohm (64.30925.6DL)
1.05V
1.1V
(27,82) USB3_PW R_ON
U6201
5V_S5
9
8
7
6
5
G9661-25ADJF11U-GP
RB DY
R6203
7K5R2F-1-GP
GND
GND
ADJ
VO
NC#5
1V_USB30_LDO_FB (82)
RT DY
74.09661.07D
2nd = 74.09025.03D
R6202
2K37R2F-GP
1V_USB30
0.6A
Vo = 0.8 * ( 1 + ( RT / RB ) )
1
C6203
SC1U10V2KX-1GP
C6201
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C6202
POK
VEN
VIN
VPP
USB3_PW R_ON
1
2
3
4
3D3V_S5
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
USB 3.0 Port
Rev
Nirvana 13
A00
Sheet
1
62
of
103
D
Bluetooth Module
BT1
AFTP6302
AFTP6304
AFTP6305
AFTP6307
1
1
1
BLUETOOTH_DET#
WLAN_ACT
BDC_ON
BLUETOOTH_EN
BT_LED
BLUETOOTH_GPIO3
BLUETOOTH_GPIO5
3
5
7
9
11
13
15
NP1
2
BT
4
6
8
10
12
14
NP2
16
ACES-CONN14D-GP
3D3V_S0
BT_ACT
USB_PP3
USB_PN3
C6301
BT
2
AFTP6301
SC2D2U6D3V3KX-GP
AFTP6306
20.F1500.014
(18)
USB_PP3
(18)
USB_PN3
(65)
BT_ACT
(65) WLAN_ACT
BT_ACT
BLUETOOTH_EN
WLAN_ACT
WLAN_ACT
BLUETOOTH_EN
BT_ACT
3D3V_S0
USB_PP3
USB_PN3
BT
10KR2J-3-GP
DY
R6303
DY
1
1
1
1
1
1
EC6301 R6302
SC220P50V2KX-3GP
2
DY
100KR2J-1-GP
R6301
AFTP6309
AFTP6310
AFTP6308
AFTP6311
AFTP6312
AFTP6313
0R2J-2-GP
<Core Design>
Q6301
BT_LED
BT
WLAN_WWAN_LED#
Wistron Corporation
WLAN_WWAN_LED# (68)

Title
2N7002K-2-GP
84.2N702.J31
Size
A4
2ND = 84.2N702.031
Document Number
Bluetooth
Nirvana 13

5
Sheet
Rev
A00
63
of
1
103
3D3V_S0
FP1
C6401
SCD1U10V2KX-4GP
1
Biometric_USBPP
Biometric_USBPN
2
3
4
5
6
8
20101227 A00:
Change R6403,R6404 to 0R 0402 pad.
20100104 A00:
Remove TR6401.
(18) USB_PN2
1 R6403
AFTP40
ACES-CON6-7GP
20.K0256.006
Biometric_USBPN
0R0402-PAD
AFTP42
AFTP43
AFTP44
(18) USB_PP2
1 R6404
3D3V_S0
Biometric_USBPN
Biometric_USBPP
1
1
1
Biometric_USBPP
0R0402-PAD
<Core Design>
Wistron Corporation
Title
Finger Printer Conn
Size
A4
Document Number
Rev
Nirvana 13

5
Sheet
A00
64
of
1
103
SSID = Wireless
Mini Card Connector(802.11a/b/g/n)

D
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C6507
C6506
SC10U6D3V5KX-1GP
1
C6505
C6504
SCD1U16V2KX-3GP
3D3V_S0
1D5V_S0
5V_S5
W LAN1
1
C6508
DY
2
(27)
(27)
1.5V
3.3V
28
48
+1.5V
+1.5V
52
+3.3V
24
E51_RXD
E51_TXD
(63)
W LAN_ACT
(63)
BT_ACT
(21,27,71) LPC_AD0
(21,27,71) LPC_AD1
(21,27,71) LPC_AD2
(21,27,71) LPC_AD3
(21,27,71) LPC_FRAME#
R6501
DY10R2J-2-GP
2
R6502
DY0R2J-2-GP
R6505 1
R6504 1
R6507 1
R6506 1
R6509 1
E51_RXD_R
E51_TXD_R
DY
DY
DY
DY
DY
2
2
2
2
2
(27) W IFI_RF_EN
3D3V_S0
20101227 A00:
R6510
1
R6503
5V_S5
(68) W LAN_LED#
(68) W PAN_LED#
W PAN_LED#
R6511
3
5
LPC_AD0_C
8
LPC_AD1_C
10
LPC_AD2_C
12
LPC_AD3_C
14
LPC_FRAME#_C 16
17
19
20
37
39
41
43
2
45
0R0603-PAD
47
49
2 +5V_MINI_DEBUG
51
0R3J-0-U-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
DY
2
0R0402-PAD
20101227 A00:
1
R6508
(18,71) CLK_PCI_LPC
DY
2
0R2J-2-GP
W PAN_LED#_R
42
44
46
REFCLK+
REFCLK-
13
11
PERN0
PERP0
23
25
PETN0
PETP0
31
33
RESERVED#3
RESERVED#5
RESERVED#8
RESERVED#10
RESERVED#12
RESERVED#14
RESERVED#16
RESERVED#17
RESERVED#19
RESERVED#20
RESERVED#37
RESERVED#39
RESERVED#41
RESERVED#43
RESERVED#45
RESERVED#47
RESERVED#49
RESERVED#51
LED_WWAN#
LED_WLAN#
LED_WPAN#
SKT-MINI52P-42-GP-U1
CLK_PCIE_W LAN (20)

CLK_PCIE_W LAN# (20)
PCIE_RXN4 (20)
PCIE_RXP4 (20)
PCIE_TXN4 (20)
PCIE_TXP4 (20)
USB_P11USB_P11+
USB_DUSB_D+
36
38
SMB_CLK
SMB_DATA
30
32
PCH_SMBCLK (14,15,20,79,82)
PCH_SMBDATA (14,15,20,79,82)
WAKE#
CLKREQ#
PERST#
1
7
22
CLK_PCIE_W LAN_REQ# (20)

PLT_RST# (5,18,27,71,82)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
9
15
18
21
26
27
29
34
35
40
50
53
54
+3.3VAUX
NP1
NP2
SCD1U16V2KX-3GP
C6501
SC220P50V2KX-3GP
W LAN_ACT
USB_P11-
R6406
USB_PN11 (18)
0R0402-PAD
NP1
NP2
1
2
SC10U6D3V5KX-1GP
C6503
C6502
SCD1U16V2KX-3GP
1D5V_S0
3D3V_S0
62.10043.831
USB_P11+
R6405
USB_PP11 (18)
0R0402-PAD
20101230 A00:
Change R4606,R4605 to 0R short pad.
20100104 A00:
Remove TR6501.
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
MINICARD(WLAN)/ITP CONN
Document Number
Rev
A00
Nirvana 13
Sheet
1
65
of
103
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
A00
Nirvana 13
Sheet
1
66
of
103
(Blanking)
C
<Core Design>
Wistron Corporation

Title
Size
A4
Document Number
Reserved
Date: Wednesday, December 22, 2010

5
Rev
Nirvana 13
2
A00
Sheet
67
of
1
103
Power LED(White)
R2
PWRLED#_C
LED BD Connector
20110103 A00:
Change R6804,R6806,R6808,R6810 to 620 ohm 5%.
20100106 A00:
Change R6804,R6806,R6808,R6810 to 1k ohm 5%.
5V_S5
Q6801
E
LED_PWR
R1
84.00143.M11
2nd = 84.02143.011
PWR_LED_B
1 R6804 2
1KR2J-1-GP
LEDBD1
7
EC6801
DYSC220P50V2KX-3GP
PDTA143ET-GP
R6801 2
1KR2J-1-GP
POWER_SW_LED_B
20110103 A00:
Change R6801 to 1k.
3rd = 84.00143.N11
PWR_LED_B
SATA_LED
BAT_WHITE
BAT_AMBER
LED_WLAN_OUT_B
2
3
4
5
6
SATA HDD LED(White)
5V_S0
ACES-CON6-13-GP
20.K0320.006
Q6802
R2
B
E
SATA_LED_R
R1
PDTA143ET-GP
DY
84.00143.M11
2nd = 84.02143.011
EC6805
SC220P50V2KX-3GP
SATA_LED#_C
3rd = 84.00143.N11
RN6801
8
7
6
5
PWRLED#_C
WHITE_LED_BAT#
AMBER_LED_BAT#
SATA_LED#_C
1 R6806 2
1KR2J-1-GP
SATA_LED
Battery LED1(White)
5V_AUX_S5
Q6805
SRN15KJ-2-GP
R2
WHITE_LED_BAT#
E
WHITE_LED_BAT
R1
PDTA143ET-GP
DY
2
84.00143.M11
2nd = 84.02143.011
1 R6808 2 BAT_WHITE
1KR2J-1-GP
EC6604
SC220P50V2KX-3GP
1
2
3
4
(27) PWRLED#
(27) BATT_WHITE_LED#
(27) CHG_AMBER_LED#
(21)
SATA_LED#
3rd = 84.00143.N11
AFTP6801
AFTP6802
AFTP6803
AFTP6804
AFTP6805
1PWR_LED_B
1SATA_LED
1BAT_WHITE
1BAT_AMBER
1LED_WLAN_OUT_B
AFTP6806
AFTP6807
1 KBC_PWRBTN#_C
1 POWER_SW_LED_B
Battery LED2(Amber)
5V_AUX_S5
Q6804
R2
B
WLAN_WWAN_LED#
(63) WLAN_WWAN_LED#
R1
AMBER_LED_BAT#
AMBER_LED_BAT
PDTA143ET-GP
DY
WLAN LED (White)
R6805
100KR2J-1-GP
R6802
WLAN_WWAN_LED#
E
WLAN_LED
1 R6810 2 LED_WLAN_OUT_B
1KR2J-1-GP
1
15KR2J-1-GP
PDTA143ET-GP
BAT54A-5-GP
DY
84.00143.M11
2nd = 84.02143.011
D6801
(82) WWAN_LED#
LED_WLAN_OUT_R#
R1
R2
83.BAT54.U81
5V_S0
Q6803
(65) WLAN_LED#
EC6802
SC220P50V2KX-3GP
3rd = 84.00143.N11
3D3V_S0
DY
84.00143.M11
2nd = 84.02143.011
U6801
BAT_AMBER
2
390R2J-1-GP
1
R6809
EC6803
SC220P50V2KX-3GP
3rd = 84.00143.N11
1
3
(65) WPAN_LED#
2
BAS16-6-GP
83.00016.K11
2ND = 83.00016.F11
TPLOCK LED
5V_S0
Q6812
R2
Q6804_B
R6813
C
TP_LOCK_LED_R
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
DY
2
15KR2J-1-GP
Need change to LOW actived from KBC GPIO
1
EC6804
SC220P50V2KX-3GP
R6807
1
R1
(27) TP_LOCK_LED#
E
2
LED1
TP_LOCK_LED_A A
390R2J-1-GP
LED-Y-57-GP
83.01921.P70
Power button LED(White)
20101224 A00:
Rename PWRBTN1 to PWRBT1.
PWRBT1
6
(27) KBC_PWRBTN#
1
R6803
KBC_PWRBTN#_C
2
100R2J-2-GP
1
EC6807
SCD1U10V2KX-5GP
2
1
EC6806
SCD1U10V2KX-5GP
2
1
POWER_SW_LED_B
4
3
2
5
A
ACES-CON4-10-GP-U
20.K0320.004
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
LED Bord/Power Button
Document Number
Sheet
1
Rev
A00
Nirvana 13
68
of
103
SSID = KBC
CAP LED CONTROL
Internal KeyBoard Connector
20110103 A00:
Change R6906 to 620 ohm 5%.
20110106 A00:
Change R6906 to 1k ohm 5%.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
JAE-CON30-7-GP
R6905
KB_DET# (21)
KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
CAP_LED_R
(27)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AFTP6911
AFTP6912
AFTP6913
AFTP6914
AFTP6917
AFTP6918
AFTP6915
AFTP6916
AFTP6921
AFTP6922
AFTP6919
AFTP6920
AFTP6925
AFTP6926
AFTP6923
AFTP6924
AFTP6929
AFTP6930
AFTP6927
AFTP6928
AFTP6933
AFTP6934
AFTP6931
AFTP6932
AFTP6935
CAP_LED
CAP_LED_R
E
CAP_LED_Q
15KR2J-1-GP
1R6906
2
1KR2J-1-GP
CAP_LED_R
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd CAP_LED_1
= 84.00143.N11
KROW [0..7]
(27)
KCOL[0..16]
(27)
1
R6907
2
DY100R2J-2-GP
CAP_LED:(X01 Low actived)

Connect to KB driving internal LED directly.(MAX 25mA)
CAP_LED_R
AFTP6901
TouchPad LOCKED
AFTP72
5V_S5
Q6902
AFTP6936
31
1
R1
R2
KB1
20.K0565.030
5V_S0
5V_S0
2
1
TouchPad Connector
2
RN6901
SRN10KJ-5-GP
C6901
SCD1U10V2KX-5GP
TPAD1
3
4
0R0402-PAD
AFTP71
20.K0382.004
1
1
1
5V_S0
TPCLK
TPDATA
2
3
4
6
+5V_KB_BL
KB_LED_BL_DET
KB_BL_CTRL#
ACES-CON4-34-GP
20.K0589.004
2nd = 20.K0613.004
1
1
1
1
AFTP76
AFTP77
AFTP78
<Core Design>
AFTP79
1
2
100KR2J-1-GP
KB_BL_CTRL#
C6906
SCD1U10V2KX-5GP
KB_LED_DET_C
51KR2J-1-GP
R6903
AFTP73
AFTP74
AFTP75
5
1
R6904
PTW O-CON4-9-GP-U1
C6905
SCD1U10V2KX-5GP
KBLIT1
(18) KB_LED_BL_DET
5
1
20101227 A00:
C6903
SC33P50V2JN-3GP
2
1
DY DY
2
C6902
SC33P50V2JN-3GP
R6902
+5V_KB_BL
5V_S0
4
3
2
TPDATA
TPCLK
KB Backlight Connector
(27)
(27)
Wistron Corporation
Q6901
P8503BMG-GP
G
S
Title
Size
A3
R6901
100KR2J-1-GP

84.P8503.031
2nd = 84.03404.C31
(27) KB_BL_CTRL
Date:
5
Key Board/Touch Pad/Media Board

Document Number
Rev
Nirvana 13
A00
Sheet
1
69
of
103
AFTP80 AFTE14P-GP 1
AFTP81 AFTE14P-GP 1
3D3V_S5
LID_CLOSE#_1
3D3V_S5
C7002
SCD1U10V2KX-5GP
AFTP82
1
AFTE14P-GP
DY
20101224 A00:
Rename HALLSW1 to LID1.
3D3V_S5
R7001
100KR2J-1-GP
LID1
R7002
LID_CLOSE#
(27) LID_CLOSE#
LID_CLOSE#_1
0R0402-PAD
DY
C7001
SCD047U16V2KX-1-GP
1
2
3
VCC
VOUT
GND
TCS20DPR-GP
20101227 A00:
74.TCS20.03B
74.09132.A7B
<Core Design>
Wistron Corporation

Title
Size
A4
Document Number
Hall Sensor

5
Rev
Nirvana 13
2
A00
Sheet
70
of
1
103
3D3V_S0
DB1
11
1
C
2
3
4
5
6
7
8
9
10
12
(21,27,65) LPC_AD0
(21,27,65) LPC_AD1
(21,27,65) LPC_AD2
(21,27,65) LPC_AD3
(21,27,65) LPC_FRAME#
(5,18,27,65,82) PLT_RST#
(18,65) CLK_PCI_LPC
DY
20101229 A00 Modify:

DB1 change to ZZ.00PAD.Y41(solder mask type)
and keep un-stuff at X-Build stage.
PAD-10P-177042-GP
ZZ.00PAD.Y41
PCB Footprint = PAD-10P-177042

B
<Core Design>
Wistron Corporation

Title
Dubug CONN
Size
A4
Document Number
Nirvana 13

5
Rev
A00
Sheet
71
of
1
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
72
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
73
of
103
SSID = SDIO
SC10U6D3V5MX-3GP
C7405
C7404
SC2D2U6D3V3KX-GP
1
2
DY
C7403
SCD01U16V2KX-3GP
C7402
SCD1U10V2KX-5GP
DY
Close to CARD1
C7401
SCD1U10V2KX-5GP
3D3V_CARD_S0
SD/XD/MS/MMC+ Card Reader

3D3V_CARD_S0
CARD1
P13
SD_VCC
P22
MS_VCC
18
XD_VCC
XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP_IN
(32)
(32)
(32)
(32)
SP4
SP3
SP13
SP12
P4
P3
P25
P23
(32)
(32)
(32)
(32)
SP8
SP6
SP1
SP10
P10
P1
P2
P19
SD_CLK
SD_CD
SD_WP
SD_CMD
(32)
(32)
(32)
SP14
SP2
SP1
P9
P16
P20
MS_BS
MS_INS
MS_SCLK
(32)
(32)
(32)
(32)
SP9
SP12
SP8
SP5
P12
P11
P14
P18
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
(32)
(32)
(32)
(32)
SP11
SP9
SP7
SP5
P21
P17
P8
P5
MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7
SD_DAT0
SD_DAT1
SD_DAT2
SD_DATA3
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
1
2
3
4
5
6
7
8
XD_CD#
SP1
SP2
SP3
SP4
SP5
SP6
SP7
(32)
(32)
(32)
(32)
(32)
(32)
(32)
(32)
10
11
12
13
14
15
16
17
SP8
SP9
SP10
SP11
SP12
SP13
SP14
XD_D7
(32)
(32)
(32)
(32)
(32)
(32)
(32)
(32)
SD_WP_COM/SDIO_GND
SD_CD_COM/SDIO_GND
SD_GND
SD_GND
P26
P27
P7
P15
MS_GND
MS_GND
P6
P24
XD_GND
XD_GND
9
19
NP1
NP2
NP1
NP2
CARD-PUSH-46P-1-GP-U
20.I0129.001
2nd = 20.I0135.001
XD_CD#
XD_D7
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
1
R7415
47R2J-2-GP
SP1_1
EC7417
SC220P50V2KX-3GP
<Core Design>
DY
2
DY
2
DY
2
1
1
SP2_1
DY
EC7416
SC220P50V2KX-3GP
DY
2
R7416
47R2J-2-GP
1
R7413
47R2J-2-GP
SP3_1
EC7415
SC220P50V2KX-3GP
DY
2
DY
2
1
R7414
47R2J-2-GP
SP4_1
EC7414
SC220P50V2KX-3GP
DY
2
DY
2
1
1
SP5_1
DY
EC7413
SC220P50V2KX-3GP
DY
2
R7411
47R2J-2-GP
1
1
SP6_1
DY
EC7412
SC220P50V2KX-3GP
DY
2
R7412
47R2J-2-GP
1
R7409
47R2J-2-GP
SP7_1
EC7411
SC220P50V2KX-3GP
DY
2
DY
2
1
R7410
47R2J-2-GP
SP8_1
EC7410
SC220P50V2KX-3GP
DY
2
DY
2
1
1
SP9_1
DY
EC7409
SC220P50V2KX-3GP
DY
2
R7407
47R2J-2-GP
1
R7408
47R2J-2-GP
SP10_1
EC7408
SC220P50V2KX-3GP
DY
2
DY
2
1
R7405
47R2J-2-GP
SP11_1
EC7407
SC220P50V2KX-3GP
DY
2
DY
2
1
1
SP12_1
DY
EC7406
SC220P50V2KX-3GP
SP13_1
EC7405
SC220P50V2KX-3GP
DY
2
R7406
47R2J-2-GP
1
R7403
47R2J-2-GP
DY
2
1
R7404
47R2J-2-GP
SP14_1
DY
2
DY
EC7404
SC220P50V2KX-3GP
2
XD_D7_1
DY
2
R7402
47R2J-2-GP
1
EC7403
SC220P50V2KX-3GP
DY
DY
2
XD_CD#_1
EC7402
SC220P50V2KX-3GP
DY
R7417
47R2J-2-GP
For EMI Reserved
Wistron Corporation
Title
Size
A3
Date:
CARD Reader CONN
Document Number
Rev
Nirvana 13
A00
Sheet
1
74
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
75
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
76
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
77
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
78
of
103
Free Fall Sensor
Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
DY
1
C7902
SCD1U10V2KX-4GP
3D3V_S0
SDA/SDI/SDO
INT2
12
SDO
GND
GND
GND
GND
2
4
5
10
(18)
R7903
100KR2J-1-GP
3
11
CS
RESERVED#3
RESERVED#11
3D3V_S0
DE351DLTR8-GP
84.2N702.A3F
2nd = 84.DM601.03F
DYR7904
100KR2J-1-GP
DY
R7906
10KR2J-3-GP
74.00351.0B3
2nd = 74.00345.0BZ
5V_S0
Q7901
2N7002KDW -GP
09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b
FALL_INT2
13
HDD_FALL_INT1
PCH_SMBDATA
2
100KR2J-1-GP
3D3V_S0
HDD_FALL_INT1
INT1
SCL/SPC
14
PCH_SMBCLK
GSENSOR_ADIR7901HDD_FALL_SDO
R7902
100KR2J-1-GP
3D3V_S0
For ADI G-sensor : R7901 is required.

For ST G-sensor : R7901 need DY
DY
2
VDD
(14,15,20,65,82) PCH_SMBCLK
(14,15,20,65,82) PCH_SMBDATA
VDD_IO
U7901
C7901
SC10U6D3V5MX-3GP
3D3V_S0
FFS_INT2_R
FFS_INT2 (56)
2 R7905
0R2J-2-GP
DY
FFS_INT2_R (18)
Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
<Core Design>
Wistron Corporation
Title
Free Fall Sensor

Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
79
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
80
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
81
of
103
IO Board CONN 80 pin

IOBD1
USB3.0 CLK
WWAN USB
(20) CLK_PCIE_USB3
(20) CLK_PCIE_USB3#
(18) USB_PP4
(18) USB_PN4
(38)
WWAN PCIE
WWAN PCIE
PS_ID_R
(20) PCIE_RXP3
(20) PCIE_RXN3
(20) PCIE_TXP3
(20) PCIE_TXN3
(14,15,20,65,79) PCH_SMBDATA
WWAN SMBUS
(14,15,20,65,79) PCH_SMBCLK
USB3_PW R_ON
(27,62) USB3_PW R_ON
1V_USB30
(62) 1V_USB30_LDO_FB
3D3V_S5
20101224 A00:
Change R8210 to 0402 0 ohm pad.
20101228 A00:
(20) CLK_PCIE_W W AN_REQ#
(22)
3G_EN
20101229 A00:
(68) W W AN_LED#
Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.
(18) USB30_SMI#
LAN PCIE
LAN PCIE
(20) PCIE_RXP2
(20) PCIE_RXN2
(20) PCIE_TXP2
(20) PCIE_TXN2
(20) PCIE_CLK_LAN_REQ#
NP4
80
NP1
1
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NP3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NP2
PCIE_TXP5
PCIE_TXN5
(20)
(20)
USB3.0 PCIE
PCIE_RXP5
PCIE_RXN5
(20)
(20)
USB3.0 PCIE
CLK_PCIE_LAN (20)
CLK_PCIE_LAN# (20)
LAN CLK
CLK_PCIE_W W AN (20)
CLK_PCIE_W W AN# (20)
WWAN CLK
5V_S5
at least 160 mil
5V_USB FOR USB3.0 POWER at least 4A

1D05V_VTT FOR USB3.0 POWER at least ?A
3D3V_S0
3D3V_S5 FOR LAN POWER at least over 3pin amount.

1D5V_S0 FOR USB3.0 POWER at least ?A
1D5V_S0
PM_LAN_ENABLE (27)
PLT_RST# (5,18,27,65,71)
PCIE_W AKE# (27)
USB3_PEGB_CLKREQ# (20)
+DC_IN
ACES-CONN80C-GP-U
20.F1432.080
Media Button Board Connector

5V_S5
5V_S5
RN8209
MEDIA_LED3#
MEDIA_LED2#
MEDIA_LED1#
EC8202
SCD1U10V2KX-5GP
2
1
EC8201
SCD1U10V2KX-5GP
2
1
5V_S5
20110103 A00:
Change R8201~R8203 to 1k.
20110104 A00:
Merge R8201~R8203 to RN8201 1k array resistor.
20110113 A00:
MEDIA1
8
7
6
5
DY
1
2
3
4
SRN10KJ-6-GP
EC8208
1
EC8207
1
EC8206
1
MEDIA_LED2# (27)
MEDIA_LED3# (27)
INSTANT_ON# (27)
DATA_RECOVERY# (27)
MEDIA_BTN3# (27)
EC8205
1
SRN1KJ-4-GP
MEDIA1_1
MEDIA1_2
MEDIA1_3
INSTANT_ON#
DATA_RECOVERY#
MEDIA_BTN3#
Low active
MEDIA_LED1# (27)
EC8204
1
<Core Design>
Wistron Corporation

SCD1U10V2KX-5GP 2
ACES-CON8-19-GP
20.K0320.008
SCD1U10V2KX-5GP 2
10
SCD1U10V2KX-5GP 2
MEDIA1_1
MEDIA1_2
MEDIA1_3
5V_S5
INSTANT_ON#
DATA_RECOVERY#
MEDIA_BTN3#
8
7
6
5
SCD1U10V2KX-5GP 2
1
1
1
1
1
1
1
1
2
3
4
SCD1U10V2KX-5GP 2
AFTP8201
AFTP8202
AFTP8203
AFTP8204
AFTP8205
AFTP8206
AFTP8207
RN8201
5V_S5
MEDIA1_1
MEDIA1_2
MEDIA1_3
SCD1U10V2KX-5GP 2
2
3
4
5
6
7
8
EC8203
1
Title
Size
A3
Date:
2
IO Board Connector
Document Number
Rev
Nirvana 13
A00
Sheet
1
82
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
A00
Nirvana 13
Sheet
1
83
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
A00
Nirvana 13
Sheet
1
84
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Reserved
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
85
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
Nirvana 13
A00
Sheet
1
86
of
103
(Blanking)
<Core Design>
A
Wistron Corporation
Title
Reserved
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
87
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
A00
Nirvana 13
Sheet
1
88
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
A00
Nirvana 13
Sheet
1
89
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
90
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
91
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reverved
Document Number
Rev
Nirvana 13
A00
Sheet
1
92
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Reserved
Size
A3
Date:
5
Document Number
Rev
Nirvana 13
A00
Sheet
1
93
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Reserved
Size
Document Number
Rev
Nirvana 13
Date:
5
A00
Sheet
1
94
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Document Number
Reserved
Rev
Nirvana 13
A00
Sheet
1
95
of
103
(Blanking)
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Reserved
Document Number
Rev
Nirvana 13
A00
Sheet
1
96
of
103
H2
HOLE335R115-GP
H6
HT85BE85R29-U-5-GP
H5
HOLE256R115-GP
H3 STF276R160H209-1-GP
H7
HOLE256R115-GP
H8
HOLE256R115-GP
H1
HT85B85X925R29-S-GP
ZZ.00PAD.D11
1
ZZ.00PAD.D41
1
ZZ.00PAD.D11
H11
HOLE197R166-1-GP
H10
HT85BE85R29-U-5-GP
34.4ID01.001
ZZ.00PAD.D01
ZZ.00PAD.V71
H15
HOLE335R115-GP
ZZ.00PAD.U61
ZZ.00PAD.D01
ZZ.00PAD.D41
1
H13
HOLE197R166-1-GP
H17
HOLE276R158-GP
H16
HT85B85X925R29-S-GP
H12
HOLE197R166-1-GP
H14
HT85BE85R29-U-5-GP
ZZ.00PAD.V71
ZZ.00PAD.V71
34.42T14.002
DY
34.45T31.001
DY
DY
34.4F822.002
DY
3D3V_S0
DY
EC9743 SCD1U10V2KX-5GP
1
1D05V_VTT 2
3D3V_S0
1
1D05V_VTT
1
1
5V_S0
DY
5V_S0
2
1
3D3V_S0
DY
3D3V_S0
1
1D05V_VTT 2
3D3V_S0
DY
DY
SCD1U10V2KX-5GP
DY
SCD1U10V2KX-5GP
EC9737
2
1
DY
EC9735
2
1
1
5V_S0
DY
3D3V_S0 3D3V_S0 3D3V_S0

SCD1U10V2KX-5GP
EC9736
2
1
DY
5V_S0
SCD1U10V2KX-5GP
5V_S5
DY
DY
5V_S0
SCD1U10V2KX-5GP
EC9732
2
1
1
DCBATOUT
DY
EC9730
2
1
DY
5V_S0
SCD1U10V2KX-5GP
EC9731
2
1
5V_S5
DY
DY
5V_S5
SCD1U10V2KX-5GP
5V_S5
2
1
+DC_IN
5V_S5
SCD1U10V2KX-5GP
EC9729
2
1
1
3D3V_S0
SCD1U10V2KX-5GP
EC9726
2
1
5V_S0
1D05V_VTT 1D05V_VTT 1D05V_VTT
DY
SCD1U10V2KX-5GP
1
5V_S5
EC9725
2
1
SCD1U10V2KX-5GP
3D3V_S0
EC9724
2
1
SCD1U10V2KX-5GP
DY
EC9722
LVDS_DDC_CLK_R
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
EC9721
DY
2
1
DY
EC9720
1
2
SCD1U10V2KX-5GP
EC9719
AUD_DMIC_IN01
AUD_DMIC_CLK1
DY
47R2J-2-GP
DY
DY
R9701
DY
RF Request
LVDS_DDC_DATA_R
R9702
AUD_DMIC_IN0
47R2J-2-GP
AUD_DMIC_CLK
SPR6
SPR8
SPRING-51-GP
EC9728
2
1
EMI Request
DY
SPRING-24-GP-U
1
SPR3
DY
SPRING-24-GP-U
1
SPR2
SPRING-24-GP-U
1
SPR1
SPRING-51-GP
DY 34.4F822.002
SPR7
SPRING-57-GP
SPR4
SPRING-24-GP-U
DY
DY
DY
DY
DY
(20,32)
(29,49)
(29,49)
(17,49)
(17,49)
EC9723
DY
SCD1U10V2KX-5GP
CLK_PCH_48M
A
CLK_PCH_48M
AUD_DMIC_CLK
AUD_DMIC_IN0
LVDS_DDC_DATA_R
LVDS_DDC_CLK_R
3D3V_S0
1
5V_S0
1D5V_S3
1
5V_S5
5V_S0
2
1
3D3V_S0
DY
DY
<Core Design>
A
Wistron Corporation
DY

Title
Size
A3
Date:
5
UNUSED PARTS/EMI Capacitors

Document Number
Nirvana 13
Rev
A00
Sheet
1
97
of
103
Huron River Platform Power Sequence

(AC mode)
(DC mode)
red word: KBC GPIO
+RTC_VCC
+RTC_VCC
T1
>9ms
DCBATOUT
DCBATOUT
Within logic high level and disable if
it is less than the logic low level.
T2
KBC GPIO34 control power on by 3V_5V_EN

Sense the power button status
5V_S5
T3
3D3V_S5
T4
+5VA_PCH_VCC5REFSUS
AC_PRESENT
Sense the power button status
AC KBC_PWRBTN#
>10ms
PCH to KBC GPIO00

T7 >5ms
V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
KBC GPO84 to PCH
0ms<T8 <90ms
5V_S5
T4
3D3V_S5
T5
+5V_ALW & +3.3V_ALW need meet 0.7V difference

+5V_ALW & +3.3V_ALW need meet 0.7V difference
+5VA_PCH_VCC5REFSUS
T6
KBC GPIO20 to PCH
PM_PWRBTN#
Platform to KBC PSL_IN2
KBC GPIO43 to PCH

T9
>16ms
PM_RSMRST#
KBC GPIO20 to PCH
T8
>10ms
PCH to KBC GPIO00

T9 >5ms
PCH_SUSCLK_KBC
AC PM_PWRBTN#
DC PCH_RSMRST#
T10
T10
PCH to KBC GPIO44
PM_SLP_S4#
T11
PM_SLP_S3#
>30us
DDR_VREF_S3(0.75V)
T13
5V_S0
T14
3D3V_S0
T15
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
T16
1D5V_S0
T17
1D8V_S0
T18
0D75V_S0
T19
1D8V_S0 & 1D5V_S3 power ready
RUNPWROK
T20
KBC GPIO23 to LAN

Enable by PM_SLP_S4#
1D5V_S3
T12
DDR_VREF_S3(0.75V)
T13
5V_S0
T14
3D3V_S0
T15
+5V_RUN & +3.3V_RUN need meet 0.7V difference
+5VS_PCH_VCC5REF
T16
1D5V_S0
T17
1D8V_S0
T18
0D75V_S0
T19
1D8V_S0 & 1D5V_S3 power ready
RUNPWROK
1D05V_VTT
T21
1.05VTT_PWRGD
T20
1D05V_VTT
VT357FCX PGOOD
T22
T21
1.05VTT_PWRGD
0D85V_S0
T23
0D85V_S0
PCH to KBC GPIO01
>30us
PM_LAN_ENABLE
Enable by PM_SLP_S4#
T12
T11
PM_SLP_S3#
KBC GPIO23 to LAN
1D5V_S3
PCH to KBC GPIO44
PM_SLP_S4#
PCH to KBC GPIO01
PM_LAN_ENABLE
VT357FCX PGOOD
T22
0D85V_S0
T24
T23
0D85V_S0
TPS51461RGER PGOOD
D85V_PWRGD
T24
TPS51461RGER PGOOD
D85V_PWRGD
SetVID
CPU SVID BUS
ACK
50us< T25 <2000us
SetVID
CPU SVID BUS
VCC_CORE
ACK
50us< T25 <2000us
VCC_CORE
VCC_GFXCORE
VCC_GFXCORE
T26
<5ms
IMVP_PWRGD
T26
ISL95831 PGOOD to system
<5ms
IMVP_PWRGD
CLK_EXP_P
ISL95831 PGOOD to system
CLK_EXP_P
This signal represents the Power

Good for all the non-CORE and
non-graphics power rails.
KBC GPIO34 control power on by 3V_5V_EN
T7 >16ms
Press Power button
AC PM_PWRBTN#
V5REF must be powered up before

Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V.
T3
S5_ENABLE
KBC GPIO43 to PCH

T6
3D3V_AUX_KBC
Platform to KBC PSL_IN2

EC_ENABLE#_1(GPIO31) keep low
PCH_SUSCLK_KBC
Not floating.
Press Power button
KBC_PWRBTN#
3D3V_AUX_KBC
T5
PM_RSMRST#(EC Delay 40ms)
This signal has an internal

pull-up resistor and has an
internal 16 ms de-bounce on the
input.
T2
3D3V_AUX_S5
3D3V_AUX_S5
S5_ENABLE
V5REF_Sus must be powered up before

VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before
VccSus3_3 within 0.7 V.
T1 >9ms
RTC_RST#
RTC_RST#
red word: KBC GPIO
ALL_SYS_PWRGD=D85V_PWRGD
T27 >99ms
PWROK
D85V_PWRGD
KBC GPIO77 to PCH

T28 >0us
2ms<
T29 <650ms
This signal represents the Power

Good for all the non-CORE and
non-graphics power rails.
D85V_PWRGD
PCH to CPU
VDDPWRGOOD
ALL_SYS_PWRGD=D85V_PWRGD
T27 >99ms
PWROK
KBC GPIO77 to PCH

T28 >0us
2ms<
T29 <650ms
PCH to CPU
VDDPWRGOOD
T30 >1ms
T31 >2ms
5ms< T32 <650ms
1D8V_S0
1D8V_S0
PCH to CPU
H_CPUPWRGD
T30 >1ms
T31 >2ms
5ms< T32 <650ms
PCH to CPU
H_CPUPWRGD
T33 >0ms
SYS_PWROK
1ms<
PLT_RST#
T35 <100ms
T33 >0ms
SYS_PWROK
T34 >1ms+60us
PCH to all system
1ms<
PLT_RST#
T36 <200us
DMI
T35 <100ms
T34 >1ms+60us
PCH to all system
T36 <200us
DMI
Robson XT Power-Up/Down Sequence

3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(Discrete only)
3D3V_VGA_S0 above VT357 VIH
8209A_EN/DEM_VGA(Discrete only)
A
VGA_CORE(Discrete only)
Ta >0ms
1V_VGA_S0(Discrete only)
RT9035 PGOOD
9035_PGOOD_1V(Discrete only)
Tb >0ms
Tc >0ms
VT357 PGOOD
<Core Design>
DGPU_PWROK(Discrete only)
Wistron Corporation
Td <20ms
Title
Power Sequence
For power-down, reversing the ramp-up sequence is recommended.
Size
A1
Date:
Document Number
Rev
Nirvana 13
Wednesday, December 22, 2010
1
A00
Sheet
98
of
103
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5
-6
AC
Adapter in
AD+
-3.1
Page38
DCBATOUT
-3.1
-3.1
VDDP
PWR_5V3D3V_ENC
3V_5V_EN
VIN
S5_ENABLE
VOUT
1D5V_S3
3
PM_SLP_S4#
-3.2
PWR_CHG_ACOK
EN
-3.3
REF
SWITCH
ENC
LL1
Page40
LL2
VREG5
RT8223MGQW
DC/DC
(3V/5V)
-6.1
DCBATOUT
VREG3
VIN
PGOOD
5V_S5
PUMP
3D3V_S5
5V_AUX_S5
15V_S5
VTT
3D3V_AUX_S5
-5
3V_5V_POK
-2
DDR_VREF_S3
TPS51116RGER
0D75V_S0
RUNPWROK
PGD
PM_SLP_S4#
Page46
Page41
DC
Battery
5V_S5
BQ24745
Charger
BT+
-3
Page39
SWITCH
Page37
BJT
3D3V_AUX_KBC
VDD
-3.1
Page40 ACOK
-4
KBC_PWRBTN#
EN
PGD
1D5V_S0
RUNPWROK
C
Page47
SWITCH
PM_SLP_S4#
GPIO43
GPIO44
PM_SLP_S3#
SLP_S4#
KBC
NPCE795P
GPIO6
Power Button
GPIO20
GPIO01
SLP_S3#
-2.1
PM_RSMRST#
PM_PWRBTN#
11
RSMRST#
PWRBTN#
GPIO77
S0_PWR_GOOD
SM_DRAMPWROK
Y
A
H_CPUPWRGD_R
UNCOREPWRGOOD
12
Sandy Bridge
CPU
13
APWROK
PWROK
SYS_PWROK
VDDPWRGOOD
H_CPUPWRGD
PROCPWRGD
Cougar Point
PCH
AND GATE
0D75V_EN
PM_DRAM_PWRGD
DRAMPWRGD
2
Page27
PLTRST#
PLT_RST#
BUF_CPU_RST#
RSTIN#
SVID
SYS_PWROK
SVID
10
5V_S5
1D8V_S0
Page37
1
-1
GPIO34
GPIO70
VOUT
TPS53311RGTR
PM_SLP_S3#
Page37
AC_IN#
VIN
3D3V_S0
SWITCH
S5_ENABLE
3D3V_S5
5V_S0
PM_SLP_S3#
DCBATOUT
V5IN
VIN
VOUT
5
RUNPWROK
S0_PWR_GOOD
TPS51218DSCR
PGOOD
VDDP
IMVP_PWRGD
SYS_PWROK
5a
5V_S5 DCBATOUT
VIN
VOUT
5a
10
AND GATE
A
1.05VTT_PWRGD
EN
Page45
1.05VTT_PWRGD
1D05_VTT
-5
0D85_S0
-7
RT8208BGQW
EN
Page48
PGOOD
RTC_AUX_S5
D85V_PWRGD
-8
+RTC_VCC
6
DCBATOUT
RTC battery
VIN
OUTPUT
SVID
D85V_PWRGD
IMVP_VR_ON
3D3V_AUX_S5
VCC_CORE
SVID
VCC_GFXCORE
VR_ON
IMVP_PWRGD
VR OUTPUT
ISL95831HRTZ
<Core Design>
Wistron Corporation
Page42 & 43 & 44 PGOOD

Power Up Sequence: -8 ~ 13
Title
Power Up Sequence Diagram

Size
A2
Date:
Document Number
Rev
A00
Nirvana 13
1
Sheet
99
of
103
Adapter
DCBATOUT
DCBATOUT_LCD
POLYSW
1D5V_S3
TPS51216
AO4407A
TPS51218
Charger
BQ24745
Battery
TPCA8062
DDR_VREF_S3
+PBATT
0D75V_S0
1D05V_VTT
1D5V_S0
TPS51427
C
3D3V_AUX_S5
15V_S5
5V_AUX_S5
5V_S5
G547F2P81
VT1317
3D3V_S5
TPCA8062
TPS51461
AO4468
TPS51311
VT1317
5V_USB1_S3
5V_S0
0D85V_S0
3D3V_S0
AO3403
3D3V_LAN_S5
1D8V_S0
VCC_GFXCORE
VCC_CORE
G5285T11
RTS5138
3D3V_CARD_S0
LCDVDD
Power Shape
Regulator
LDO
Switch
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Power Block Diagram
Document Number
Nirvana 13
Rev
A00
Sheet
1
100
of
103
PCH SMBus Block Diagram

+3.3V_ALW
+5V_RUN
+3.3V_RUN
SRN2K2J-1-GP
SMBCLK
PCH_SMB_CLK
SMBDATA
PCH_SMB_DATA
SRN2K2J-1-GP
DIMM 1
PCH_SMBCLK
SRN10KJ-5-GP
SDA
SMBus Address:A0
PSDAT1
TPDATA
PSCLK1
TPCLK
2N7002SPT
SML1CLK
KBC_SCL1
SML1DATA
KBC_SDA1
To KBC
SML0CLK
SML0_CLK
SML0DATA
SML0_DATA
PCH_SMBCLK
SCL
PCH_SMBDATA
SRN2K2J-1-GP
XDP
SRN2K2J-1-GP
PCH_SMBCLK
PCH_SMBDATA
Battery Conn.
SRN100J-3-GP
SDA
SCL1
BAT_SCL
PBAT_SMBCLK1
CLK_SMB
SDA1
BAT_SDA
PBAT_SMBDAT1
DAT_SMB
Clock
Generator
Level
Shift
PCH_HDMI_CLK
PCH_HDMI_DATA
SDATA
SCL
SDA
SMBus address:12
+3.3V_RUN
PCH_HDMI_CLK
PCH_HDMI_DATA
UMA
+3.3V_RUN
PCH_SMBCLK
PCH_SMBDATA
SRN2K2J-1-GP
UMA
SMBus address:16
BQ24745
KBC
NPCE781BA0DX
SCLK
SMBus address:D2
UMA
SRN0J-6-GP
PCH_SMBCLK
LDDC_CLK_PCH
PCH_SMBDATA
L_DDC_DATA
SMBus Address:A4
+3.3V_RUN
L_DDC_CLK
TPCLK
SRN4K7J-8-GP
DIMM 2
+3.3V_ALW
SDVO_CTRLCLK
TPDATA
TPCLK
2N7002DW-1-GP
SDVO_CTRLDATA
TPDATA
+KBC_PWR
SRN2K2J-8-GP
PCH
TouchPad Conn.
SCL
PCH_SMBDATA
+3.3V_ALW
KBC SMBus Block Diagram
+3.3V_RUN
LDDC_DATA_PCH
Minicard
WLAN
+3.3V_RUN
SMB_CLK
SMB_DATA
Minicard
W-WAN
GPIO73/SCL2
KBC_SCL1
GPIO74/SDA2
KBC_SDA1
SRN4K7J-8-GP
Thermal
THERM_SCL
SCL
THERM_SDA
SDA
SMBus address:7A
2N7002DW-1-GP
SMB_CLK
SMB_DATA
UMA
CRT_DDC_CLK
CRT_DDC_DATA
+3.3V_RUN_VGA
PCH_CRT_DDCCLK
PCH_CRT_DDCDATA
SRN2K2J-1-GP
DIS
B
DDC1CLK
LCD CONN
DDC1DATA
SRN0J-6-GP
DDC2CLK
DDC2DATA
VGA_CRT_DDCCLK
VGA_CRT_DDCDATA
+3.3V_RUN
+5V_RUN
DIS
VGA
+3.3V_RUN
UMA
SRN0J-6-GP
SRN2K2J-1-GP
UMA
SRN2K2J-1-GP
CRT_DDCCLK_CON
CRT_DDCDATA_CON
+5V_RUN
+3.3V_RUN_VGA
+5V_RUN
CRT CONN
UMA
2N7002DW-1-GP
SRN2K2J-1-GP
SRN2K2J-1-GP
DIS
IFPC_AUX_I2CW_SCL
GPU_HDMI_CLK
IFPC_AUX_I2C_SDA#
GPU_HDMI_DATA
TSCBTD3305CPWR
HDMI CONN
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
SMBUS Block Diagram
Document Number
Nirvana 13

1
Rev
A00
Sheet
101
of
103
Thermal Block Diagram
Audio Block Diagram
SPKR_PORT_D_LDXP
PAGE28
SPEAKER
SPKR_PORT_D_L+
P2800_DXP
MMBT3904-3-GP
SC2200P50V2KX-2GP
DXN
UMA
Thermal
P2800
P2800_DXN
Codec
92HD79B1
Place near CPU

PWM CORE
HP
OUT
HP1_PORT_B_L
MMBT3904-3-GP
GPIO5
PAGE27
C
KBC
NPCE795P
GPIO92
SYS_THRM
TDR
CPU_THRM
TDL
HP1_PORT_B_R
T8
OTZ
THERM_SYS_SHDN#
2N7002
PURE_HW_SHUTDOWN#
IMVP_PWRGD
S
G
Put under CPU(T8 HW shutdown)
EN
D
PGOD
VR
GPIO4
GPIO94
3V/5V
MIC
IN
HP0_PORT_A_L
GPIO56
HP0_PORT_A_R
FAN_TACH1
FAN1_DAC
TACH
FAN
Digital
MIC
DMIC_CLK/GPIO1
VIN
5V
VIN
VREFOUT_A_OR_F
DMIC0/GPIO2
VSET
VOUT
FAN CONTROL
P2793
PORTC_L
PAGE28
Analog
MIC
PORTC_R
VREFOUT_C
<Core Design>
Wistron Corporation
Title
Size
A3
Date:
5
Thermal/Audio Block Diagram
Document Number
Rev
A00
Nirvana 13
Sheet
1
102
of
103
Version
Date
A00
20101222
A00
20101222
A00
20101224
Page
20101224
A00
20101224
A00
Change Item
40
Power
Power/Brian: Change PR4047 to 174k ohm from 121k ohm. Change PR4035 to 300k from 49.9k. Change PR4031 to 150k from 0 ohm. Change PR4034 to 0 ohm pad. Stuff PQ4003. Change PR4036 to 0 ohm pad. Stuff PQ4004.
Change PR4037 to 76.8k ohm from 49.9k ohm. Change PR4032 to 0 ohm pad.
42
Power
Power/Brian: Change PU4201 to 74.01316.F33.
EE
Change all of 0ohm to short pad at X-build stage:

0402: R1404 R1405 R1503 R1504 R5010~R5012 R1807 R2301 R2306 R2307 R2308 R2404 R2405 R2735 R2737 R2758 R2759 R2760 R3614 R3710
0603: R5803 R5804 R8507
Parallel resistor: RN1704 RN2010 RN2011 RN2012 RN2013 RN2014 RN2016
RN5117,RN5112,RN5113,RN5114,RN5115
A00
Function
EE
Rename PRN3901 to PN3901. Rename PTC4101~PTC4103 to PT4101~PT4103. Rename PTC4502,PTC4509 to PT4502~PT4509. Rename PTC4601,PTC4602 to PT601~PT4602. Rename PTC4801 to PT4801. Rename LINEOUT1 to LOUT1. Rename PWRBTN1 to PWRBT1.
Rename HALLSW1 to LID1.
27
EE
Change R2724 to 47K from 33K.
20101224
28
EE
If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.
A00
20101224
45,46
Power
Change PR4514,PR4607 to 0ohm short pad from 0402 and un-stuff PC4523 at X-Build stage.
A00
20101224
28
EE
If stuff P2800EA1 then must stuff R2803,R2804 C2805 but if stuff P28003B0 should be un-stuff.
A00
20101227
32,42,49
62,64,65
69,70
EE
Change R3210,R3211;PR4217~PR4220,PR4254;R4908,R4909,R4903,R4910,R4913~R4916, R4917,R4918;R6205;R6403,R6404;R6511;R6902;R7002 to 0R 0402 pad.
A00
20101228
23
EE
0402 0R pad: R2301.
A00
20101228
27,62,82
EE
A00
20101228
27
EE
Change R2756,R2763,R2766 to 0R short pad.
A00
20101228
28
EE
Un-stuff U2805 G709T1UF related circuit and R2812 then stuff R2805 at X-Build.
A00
20101229
71
EE
DB1 change to ZZ.00PAD.Y41(solder mask type) and keep un-stuff at X-Build stage.
A00
20101229
27,62,82
EE
Rename USB_PWR_EN to USB3_PWR_ON. Remove R6205,R620. Remove R2809 and R8210. Connect USB3_PWR_ON from KBC to IOBD1.61.
A00
20101230
41,46,65
EE
Change PR4119 to 0R short pad. Change PR4114 to 0R short pad. Follow the standard schematics: remove PR4615,PR4616. Change R6406,R6405 to 0R short pad. Change PR4116 to 0R0603 short pad. Change PR4106 to 0R0603 short pad.
Change R6510 to 0R 0603 pad. Change PR4103,PR4104 to 0R0805 short pad.
A00
20101231
43
Power
Power/Brian: change PL4201 to 68.2415N.101 from 68.10110.10G.
A00
20101231
42,50,18
14,9,8
EE
Change PR4209,PR4212 to PN4201 10k array resistor. Change R5004,R5005 to RN5001 33 ohm array resistor. Merge R1804,R1806 to RN1804 22 ohm array resistor. Merge R1401,R1402 to RN1401 10k ohm array resistor.
Merge R906,R907 to RN902 100 ohm array resistor. Merge R801,R802 to RN801 100 ohm array resistor.
A00
20110103
68,82
EE
Change R6801,R8201~R8203 to 1k.
A00
20110103
68,82
EE
Change R6801,R8201~R8203 to 1k.
A00
20110104
EE
merge R512,R514 to RN502 1k array resistor.
A00
20110104
EE
Swap VCC_CORE to RN801.4 and VCCSENSE to RN801.1.
A00
20110104
EE
Swap VCC_GFXCORE to RN902.1 and VCC_AXG_SENSE to RN902.4.
A00
20110104
14
EE
Change RN1401 to 0R short pad.
A00
20110104
15
EE
Change R1502 to 0R0402 short pad.
A00
20110104
17
EE
Merge RN1701,RN1706 to RN1703 2.2k array resistor.
<Core Design>
A
Wistron Corporation
A00
20110104
32,49,57
64
EE
Remove TR3201,TR4902,R5718,R5719,TR6401
A00
20110104
68,69
EE
Change R6804,R6806,R6808,R6810,R6906 to 620 ohm 5%.
Title
A00
20110104
82
EE
Merge R8201~R8203 to RN8201 1k array resistor.
Size
A3
A00
20110107
68,69
EE
5

Date:
Change R6804,R6806,R6808,R6810,R6906 to 1k ohm 5%.

4
Change History
Document Number
Rev
Nirvana 13
Thursday, January 06, 2011
A00
Sheet
1
103
of
103
Version
Date
A00
20110107
Page
49
Function
Change Item
EE
Change F4902 to 0603 0 ohm.
A00
20110110
21
EE
Merge R2115,R2116 to RN2101.
A00
20110110
41
Power
Change PG4110,PG4112,PG4114~PG4119,PG4122,PG4126,PG4129,PG4131,PG4133,PG4135~PG4138,PG4140,PG4142,PG4102~PG4109,PG4111,PG4113,PG4118,PG4120,PG4123,PG4101,PG4127,PG4130,PG4132,PG4134, PG4139,PG4141 to ZZ.CLOSE.001.
A00
20110110
41
Power
Add PT4104 47uF.
A00
20110111
49,51
EE
Change R4908,R4909,R4903,R4910,R4913~R4916 R4917,R4918 to 0R 0402 reisstors. Change R5101~R5108 to 0 ohm array resistors RN5102~RN5105. Change RN5117 to 0 ohm resistor.
A00
20110112
20
EE
Change C2007,C2008 to 15pF from 12pF base on vendor's report.
A00
20110112
41
EE
Change PT4104 to 100uF.
A00
20110113
8,9
EE
Change RN801,RN902 to 100 ohm 1% (66.10156.04L).
A00
20110113
5,8,9
17,18,21
42,82
EE
Swap RN502,RN801,RN902,RN1703,RN1804,RN2101,RN4201,RN8201 base on swap report.
A00
20110118
51
EE
Remove RN5117 for PCH_HDMI_CLK and PCH_HDMI_DATA.
<Core Design>
A
Wistron Corporation
Title
Size
A3
Date:
5
Change History
Document Number
Rev
Nirvana 13
A00
Sheet
1
104
of
104

8230e DELL Vostro 3350 Wistron Nirvana 13

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5

Nirvana 13 UMA Schematics Document

Nirvana 13 UMA Block Diagram

Project Code: 91.4ID01.001

DDRIII 1066/1333 Channel B

(On Daughter Board)

SATA ports (6)

PCIE ports (8)

High Definition Audio

14 USB 2.0/1.1 ports

Free Fall Sensor

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Huron River Schematic Checklist Rev.1_0

Reboot option at power-up

GNT[3:0]# functionality is not available on Mobile.

Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K5% pull-up

This Signal has a weak internal pull-up.

Signal has a weak internal pull-down.

On-Die PLL Voltage Regulator Voltage Select

Huron River Schematic Checklist Rev.1_0

Configuration (Default value for each bit is

DMI and FDI Tx/Rx Termination Voltage

Deep S4/S5 Well On-Die Voltage Regulator Enable

This signal enables the internal Deep Sleep 1.05 V regulators.

15 -> 0, 14 -> 1, ...

PEG DEFER TRAINING

1: PEG Train immediately following xxRESETB de assertion

ON for supporting Deep Sleep states

Powered by Li Coin Cell in G3

AC Brick Mode only

On-Die PLL Voltage Regulator

Disabled - No Physical Display Port attached to

This signal has a weak internal pull-down.

Integrated 1.05 V VRM Enable / Disable

LAN (I/O Board)

ESATA / USB COMBO

Mini Card2 (WWAN)

Mini Card1 (WLAN)

HURON RIVER ORB

Signal Routing Guideline:

Signal Routing Guideline:

PCI EXPRESS* - GRAPHICS

Stuff to disable internal graphics

Tuesday, January 18, 2011

Connect EC to PROCHOT# through inverting OD buffer.

Signal Routing Guideline:

JTAG & BPM

Buffered reset to CPU

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

Tuesday, January 18, 2011

Display Port Presence Strap

0: Enabled; An external Display Port device is

PCIE Port Bifurcation Straps

1: Disabled; No Physical Display Port

CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

1: Normal Operation; Lane #

PEG Static Lane Reversal

PEG DEFER TRAINING

1: PEG Train immediately following xxRESETB de assertion

W ednesday, December 22, 2010

VCCIO Output Decoupling Recommendation: