VLSI Technology and Design

UNIT-2

ASSIGNMENT SHEET-1

1) What is the difference between verilog and VHDL?

2) How HDL is different from software languages such as c, c++?
3) What is the difference between = = and = = =?
4) What is the difference between inter statement and intra statement delay?
5) What is the difference between continuous assignment and procedural assignment?
6) Explain verilog data types.
7) Write Verilog code for Full Adder using
a. Gate Level Modelling
b. Data-flow Modelling
8) What is the difference between wire and net?
9) Discuss the port connection rules that need to be followed to avoid simulation error.
10) Write verilog code for 41 multiplexer using conditional operator.
11) Explain with example
a. Reduction operator
b. Logical operator
c. Bitwise operator
12) Write verilog code to generate clock signal with 75% duty cycle.
13) Define the term instantiation. Give an example how instances can be used in gate
level modelling.
14) Discuss the components of a verilog module.
15) Let A=1b1 and B=2b00 then what is the value of Y if Y = {4{A},2{B}}?

Abhay Sharma

Department of ECE, GEHU

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