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Delta Products Corporation

Power Electronics Laboratory

P.O. Box 12173, 5101 Davis Drive

Research Triangle Park, N.C. 27709, U.S.A.

cost-sensitive applications due to its simplicity and low component count. It

is widely employed in mobile phone chargers and as the stand-by power

source in off-line power supplies for data-processing equipment. However,

the optimization of this circuit is almost exclusively performed by a cutand-try approach since its operation is generally not well understood. This

paper presents a detailed steady-state analysis of the self-oscillating flyback

converter along with its small-signal model. Design guidelines of the

control circuit and loop compensation are presented and verified on an offline, stand-by, 5-V/ 2-A power supply.

I. INTRODUCTION

The self-oscillating flyback converter, often referred to as

the ringing choke converter (RCC), is a robust, lowcomponent-count circuit that has been widely used in lowpower off-line applications. Since the control of the circuit

can be implemented with very few discrete components

without loss of performance, the overall cost of the circuit is

generally lower than the conventional PWM flyback

converter that employs a commercially available integrated

control .

Generally, the operation of the circuit is not well

understood. This is primarily due to the fact that existing

literature deals with the circuit in a very superficial manner

[1]-[2]. Therefore, the design of this converter usually

follows a cut- and-try approach, which is a time consuming

process and which usually doesnt lead to an optimized

design.

The purpose of this paper is to present a complete designoriented steady-state analysis and small-signal model of the

self-oscillating flyback converter that can be used in the

optimization of this circuit. In addition, a step-by-step design

procedure of the control circuit is presented and verified on

an off-line, 5-V/2-A, stand-by power supply.

applications with a wide range of input voltage and load

current, an error amplifier is often implemented.

The circuit diagram of an isolated self-oscillating flyback

converter with output voltage control is shown in Fig. 1.

Transformer T1 consists of 2 secondary windings: output

winding NS1 and positive-feedback winding NS2. Main output

VO1 is isolated, and tightly regulated by error amplifier E/A,

whereas auxiliary output VO2 is not isolated, and is loosely

regulated by main output VO1 through transformer T1. Output

voltage VO1 is sensed through a resistor divider consisting of

resistors Rd1 and Rd2, and compared at the input of a

transconductance type amplifier (TL431) to a stable voltage

reference located within the TL431 device. Components

CEA1, CEA2, and REA1 are used as compensation to stabilize the

voltage control loop. The difference between the sensed

output voltage and the voltage reference is amplified by

TL431 and reflected to the primary side through optocoupler

IC1 as error current ie, which in turn develops error voltage Ve

across (the sum of) resistors RS and RF. Error voltage Ve is

summed with a voltage proportional to switch current iS1 and

compared at the PWM modulator, which is implemented with

bipolar junction transistor (BJT) Q1, to a fixed voltage

threshold, which, in this case, is cut-off voltage V of

transistor Q1. Zero-current detect components CZCD and RZCD,

along with winding NS2, sense, with some delay, the

continuous/discontinuous conduction mode (CCM/DCM)

boundary of transformer T1, and delivers charge to main

switch S1 to initiate switch turn-on. Finally, circuit start-up is

D1

T1

NP

LF

NS1 i 1

CO1

i01

RL1

CF

Rd1

VO1

Rd2

RST

The self-oscillating flyback converter operates at the

boundary of continuous/discontinuous conduction mode

(CCM/DCM) and utilizes peak current mode control.

Therefore, the circuit operates with a variable switching

frequency. The implementation of the control is done

discretely, which is simple and cost effective since the pulsewidth modulator (PWM) and switch driver are implemented

with a single transistor, a positive-feedback winding, and a

resistor divider network. In applications which do not require

tight regulation, a simple feedback control consisting of a

single zener diode may be implemented. However, in

VIN

S1

NS2

VDS

ZD1

CO2

V2

VG i S1

RL2

VO2

D2

i2

i02

R ZCD

RS

V ZCD C ZCD

IC1

RF

Vd

RA

Q1

PWM

MOD

IK

VQbe

ie

RB

CEA2

CEA1

VKA

REA1

TL431

E/A

capacitance CISS of main switch S1 from input voltage VIN.

A.

Steady-State Operation

In order to simplify the explanation of the converter shown

in

Fig. 1

during

steady-state

operation,

several

approximations have been made. The first approximation is

to neglect the leakage inductance of transformer T1. This

eliminates the need to consider the action of a voltage clamp

across primary winding NP which is implemented to protect

main switch S1 from voltage ringings. The second

approximation is to model error current ie as a constantcurrent source, i.e., to replace compensated error amplifier

TL431, opto-coupler IC1, capacitor CF, and resistors Rd1, Rd2,

RA, and RB with constant-current source ie. The final

approximation is to neglect the capacitance CGD between the

gate and drain terminals of main switch S1 and to model the

terminal capacitances between the gate and source CGS and

between drain and source CDS as input capacitance CISS and

output capacitance COSS respectively. In addition to these

approximations, it is assumed that CO1>>CO2, and RL1<<RL2.

The assumption CO1>>CO2 implies that the ripple voltage of

output VO2 is greater than the ripple voltage of main output

VO1. Another assumption is that time constant RSTCISS is

much greater than switching period TS, i.e., RSTCISS>>TS.

With this assumption, it is possible to ignore start-up resistor

RST during steady-state operation. Finally, it is assumed that

rectifiers D1 and D2 are ideal i.e., have zero forward voltage

drop while conducting.

To facilitate the explanation of the converter operation,

Fig. 2 shows eleven topological stages of the circuit in Fig. 1

during a switching cycle, including the reference directions of

currents and voltages, whereas Fig. 3 shows key waveforms

of the power and control stage.

Prior to t = t0, current iQce and voltage VCZCD is positive,

and switch S1 is turning off because charge is drawn from

input capacitance CISS of main switch S1 by transistor Q1. As

a result, drain-source voltage VDS increases towards

VIN + NVO. When, at t = t0, voltage VDS reaches VIN + NVO,

rectifiers D1 and D2 start conducting. During this stage, which

is shown in Fig. 2(a), magnetizing current iM is

instantaneously commutated from switch S1 to output

rectifiers D1 and D2 since it is assumed that leakage

inductance Llkg of the transformer is zero. In the presence of

winding resistances (not shown in Fig. 2), the selection of

output capacitors CO1>>CO2 causes voltage VO1 to be

approximately constant while voltage VO2 increases, which

results in a faster decrease of current i2 with respect to current

i1, as shown in waveforms (d) and (e) of Fig. 3. Because

during this topological stage rectifier D2 is conducting,

voltage VRZCD across resistor RZCD is equal to

(VGS + VS + VCZCD ) (VGS + VCZCD ) since VS << VGS + VCZCD . This

voltage induces current iZCD through resistor RZCD which

discharges capacitors CISS and CZCD. At the same time,

transistor Q1 is off and current ie flows through the loop

consisting of resistors RF, RS, and RL2. It should be noted that

voltage VQbe is below its cut-off voltage V. Since, from

because

Fig. 2(a),

VQbe = i e R F + iS1R S i e R F

iS1R S << i e R F ,

transistor Q1 is off during t0 < t < t1 if i e R F < V . The stage in

Fig. 2(a) ends at t = t1 when voltage VGS has decreased to the

voltage level which is approximately one diode voltage drop

below voltage VQbe of transistor Q1 so that its base-collector

pn junction becomes forward biased.

After base-collector diode Dbc starts conducting at t = t1,

current ie is divided between resistor RF and the base of Q1.

Because collector-emitter voltage VQce is negative, transistor

Q1 operates in the inverse-constant-current region and current

iQce flows from the emitter to collector, as shown in Fig. 2 (b).

During this stage, capacitor CZCD continues to discharge by

the sum of currents iQce and iQbc. As a result, voltage VQbe

increases exponentially as illustrated in waveform (f) of

Fig. 3. At the same time, currents i1 and i2 continue to

decrease. This stage ends at t = t2 when rising voltage VO2

reaches the winding voltage V2 and rectifier D2 turns off.

Meanwhile, capacitor CZCD continues to discharge through

winding NS2, as shown in Fig. 2(c). During this stage, current

i1 continues to decrease. This stage ends at t = t3 when current

i1 reaches zero, i.e., when magnetizing energy of the

transformer is completely discharged.

Since at t = t3, drain-source voltage VDS of switch S1 is

higher than input voltage VIN, capacitor COSS starts to

resonantly discharge through magnetizing inductance LM, as

can be seen in waveform (b) of Fig. 3. As a result, primary

voltage VP decreases, causing a proportional decrease in

secondary voltage V2. As the secondary voltage decreases,

the voltage across resistor RZCD also decreases which

decreases current iZCD. This topological stage ends at t = t4

when current iZCD reaches zero.

After t = t4, current iZCD starts flowing in the opposite

direction so that capacitors CZCD and CISS start to charge, as

shown in Fig. 2(e). Since the increase of voltage VGS leads to

the increase of collector-emitter voltage VQce, diode Dbc turns

off, causing the turn-off of transistor Q1. At the same time,

capacitor COSS continues to resonantly discharge, which

further decreases secondary winding voltage V2. As a result,

the voltage across resistor RZCD increases which causes a

further increase of current iZCD. This topological stage ends at

t = t5 when the voltage across the windings of the transformer

become equal to zero. After t = t5, capacitor COSS continues to

discharge and the winding voltages change polarity, as shown

in Fig. 2(f). Because in this topological stage voltage

VO2 + V2, which drives current iZCD, continues to increase,

current iZCD also continues to increase. This increased current

iZCD causes an increase of voltage VGS, which in turn

produces a further discharge of capacitor COSS and

consequently a further increase in the sum of voltages VO2

and V2. This positive feedback continues until voltage VGS

reaches voltage VTH at t = t6 and switch S1 is turned on by

entering its constant-current region.

After t = t6, gate-source voltage VGS continues to increase

T1

N S1

V1

NP

LM

VIN

iM

S1

V DS

R L2

D2

VRZCD

RZCD

VCZCD

CZCD

RF

iQb

NP

COSS

CISS

S

ie

VQbe

NP

S1 D

G

COSS

C ISS

RS

Dbc

D1 C

O1

RCO1

RL1

NP

C ISS

NP

ie

D1 CO1

RCO1

RL1

NP

NS2

CO2

RCO2

V IN

RL2

C ISS

Q1

ie

t9

D

S

RF

e

(j) t 8

S1

RS

C ISS

D1 C

O1

RCO1

NS1

RL2

(k) t 9

ie

t8

RL1

NP

D1 CO1

RCO1

RL1

CO2

RCO2

RL2

NS2

LM

V IN

S1

D

S

RF

b

ie

Q1 b

(i) t 7

RZCD

CZCD

c

RF

t7

CISS

RL2

RZCD

CZCD

NS2

CO2

RCO2

NS2

CO2

RCO2

Q1

RS

ie

LM

RL1

LM

Q1 b

D1 C

O1

RCO1

V IN

S1

V IN

RZCD

CZCD

NS1

RL2

ie

t5

RL1

NP

NS1

Q1 b

e

(f) t 4

RF

(h) t 6

LM

t6

NS1

ie

RZCD

CZCD

RS

RL2

RF

D1 C

O1

R CO1

CO2

RCO2

RZCD

CZCD

RS

t4

CISS

RL1

NS2

C ISS

NS2

D1 C

O1

RCO1

LM

RF

Q1 b

ie

V IN

CO2

R CO2

Q1 b

(g) t 5

RL2

RF

t2

S1 D

G

LM

S1

Q1 b

NS1

COSS

V IN

RF

RL2

RZCD

CZCD

S1 D

G

Dbc

NS1

NS2

CO2

RCO2

RS

RL1

RZCD

CZCD

(e) t 3

LM

RS

ie

V IN

RS

t3

NS1

COSS

CISS

Dbc

NP

V IN

RF

Q1 b

D1 C

O1

RCO1

NS2

S1 D

G

(c) t 1

CO2

RCO2

COSS

RS

t1

LM

RZCD

CZCD

(d) t 2

NP

RL2

C ISS

ie

t 10

RS

RL2

RZCD

CZCD

S1 D

G

COSS

Q1 b

NS1

NS2

V IN

S1

RL1

CO2

D2 RCO2

V IN

RF

RL1

NS2

LM

CZCD

(b) t 0

LM

RL2

D1 CO1

RCO1

NS1

NP

RS

CO2

RCO2

CO2

RCO2

RZCD D2

S1 D

G

D1 CO1

RCO1

RL1

NS2

V IN

(a)

NS1

D1 CO1

RCO1

LM

V02

iRf

VQbc

Q1

i2

VZCD

iQce

RS

CO2

NS1

V01

NP

V2

VGS

VS

R L1

NS2

VP

iS1

D1 i1 CO1

RZCD

CZCD

C ISS

Q1

RF

b

ie

e

(l) t 10

t 11

Fig. 2 (a) Simplified circuit diagram of self-oscillating flyback converter which contains voltage and current designators. (b) (l) Topological stages of

self-oscillating flyback converter.

shown in Fig. 2(g). This stage ends at t = t7 when gate-source

voltage VGS reaches the level where switch S1 begins

operating in the ohmic region, i.e., when switch S1 is fully

turned on. After switch S1 is fully turned on at t = t7, drainsource current iS1 starts increasing linearly with slope

diS1 dt = VIN L M . As a result, voltage drop VS = iS1RS across

sensing resistor RS also increases with the same slope. This

t0

VGS

t1

t2

t3 t5

t4

t6

t7

t8

t 9 t11

t10

(a)

VTH

t

VIN +NVO1

VDS ,

VIN+NVO1

VIN

(b)

VDS

t

(c)

S1

t

(d)

1

t

(e)

t

VQbe

(f)

t

(g)

iRF

t

(h)

iQce

t

VCZCD

(i)

t

which also increases the potentials of the gate terminal of S1

and the base terminal of Q1, as shown in waveforms (a) and

(f) of Fig. 3. When, at t = t8, base-emitter voltage VQbe

reaches its cut-off voltage V, transistor Q1 starts conducting,

as shown in Fig. 2(i). It should be noted that to prevent the

gate voltage of switch S1 of exceeding the maximum rated

voltage, a voltage clamp (such as a zener diode) should be

connected between the gate terminal of S1 and ground. Once

the gate voltage is clamped, current is diverted from input

capacitance CISS to the voltage clamp until the gate voltage

falls below the clamp voltage level.

Since after t = t8 voltage VQbe continues to increase because

voltage VS = iS1RS increases, base current iQbe of Q1 increases

causing the increase of current iQce. This topological stage

ends at t = t9 when current iQce becomes equal to current iZCD

and gate-source capacitance starts discharging, as shown in

Fig. 2(j). As voltage VGS decreases, switch S1 is turning off.

At t = t10, voltage VGS decreases to threshold voltage VTH of

switch S1 so that S1 is turned off. After switch S1 is turned off

at t = t10, output capacitance COSS of switch S1 begins to

charge so that voltage VDS begins to increase. This

topological stage shown in Fig. 2(k) ends when voltage

VDS + VS VDS reaches VIN + NVO . At the same time, secondary

rectifiers D1 and D2 start conducting and transistor Q1 turns

off, which completes a switching cycle.

A.

amplifier compensation requires knowledge of the smallsignal transfer functions in the control loop. Since the selfoscillating flyback converter operates with a variable

switching frequency, the small-signal block diagram model

differs from that of the conventional, constant-frequency type

PWM converter, as discussed in [3].

To facilitate the design optimization of the control loop, the

self-oscillating flyback circuit in Fig. 1 has been simplified to

include only circuit elements which plays a role in the

feedback control, as shown in Fig. 4. Zero-current-detect

components RZCD and CZCD, which are related to the

switching transitions, and zener diode ZD1, which clamps the

potential of the gate terminal of switch S1, are neglected.

Also, since small-signal error current ie is not a function of

output voltage VO2, but rather is a function of small-signal

error amplifier current iEA , auxiliary winding NS2, capacitor

CO2, resistor RL2, and rectifier D2 can be neglected. Smallsignal error current ie can, therefore, be represented as a

dependent current source, as shown in Fig. 4. Finally, start-up

resistor RST is neglected.

Based on this equivalent circuit, the small signal block

diagram is derived, as shown in Fig. 5. The block diagram

consists of control-to-output voltage transfer function

V

, output voltage sensing gain K = V

V

, error

G VeVo (s) = V

O

e

d

1

O

amplifier transfer function G EA (s) = VEA V1 , transconductance

gain G1 = iEA VB , opto-coupler gain G 2 = ie iEA , and

transresistance gain G 3 = Ve ie . The transfer function

expressions are summarized in Table 1. The block diagram is

further simplified by incorporating transfer function blocks

GVeVo(s), G1, G2, and G3 into block G VEA VO (s) = VO VEA to

form a single loop system, where

G VEA VO (s) =

V

G 1G 2 G 3 G VeVo (s)

TINNER

O

=

=

1

+

1

+

G

G

G

G

(

s

)

TINNER

V

1

2

3

VeVo

EA

N : 1

D1

LF

S1

Kd

CO1

CF IO

RCO1

RCF

Rd2

G1

^

VB

RS

RB

^

iEA

G3

RF

GEA(s)

Q1

^

ie

Small-Signal Model

Rd1

VO

Gvevo (s)

dynamic performance while ensuring system stability,

compensation components CEA1, CEA2, and REA1 need to be

determined. However, the design optimization of the error

R LF

LM

VIN

, (1)

VQbe

^

V

=^

EA VKA

CEA2

CEA1

REA1

TL431

i e = iEA

^

Ve = (RS + RF )^i e

G2

Fig. 4 Simplified circuit diagram of self-oscillating flyback converter for

small-signal modeling and analysis

GV

(s)

continuous conduction mode and discontinuous conduction

mode (CCM/DCM), and is out of the scope of this paper.

However, the selection of zero-current-detect components

RZCD and CZCD, as well as the components related to the

feedback loop, is generally not well understood, and is

therefore discussed below in detail.

EAVO

^

VO

GVEVO (s)

^

Ve

Kd

^

V1

TINNER

G3

^i

e

G2

G1

^i

EA

^

VB

+

_

A.

GEA(s)

^

VEA

As can be seen from Eq. (1), transfer function G VEA VO (s)

has a low frequency gain which is less than 1. Also, poles of

transfer function G VEA VO (s) , which are within the bandwidth

of inner loop TINNER, are shifted to higher frequencies with

respect to power stage transfer function GVeVo(s), whereas the

location of power stage transfer function zeroes are

unaffected by the existence of the inner loop. Assuming that

only the first pole, i.e., sp1, of power stage transfer function

GVeVo(s), is within the bandwidth of inner loop TINNER (i.e.,

that second stage LC filter resonant frequency O > INNER,

where TINNER(@ INNER) = 0 dB), transfer function G VEA VO (s)

can be written in pole-zero form as

G VEA VO (s) =

G 1G 2 G 3 M dc

(s s z1 + 1)(s s z2 + 1)

1 + G 1G 2 G 3 M dc s s *p1 + 1 s 2 2O + s QO + 1

) , (2)

)(

By defining transfer function G VEA VO (s) , the system is

reduced to a single loop system with loop gain

T1 = K d G EA (s)G VEA VO (s) .

(3)

The design of the power stage of the self-oscillating

flyback converter follows the well established design rules

Steady-State Considerations

To achieve good output voltage regulation during steadystate operation, ramp voltage iS1RS summed with dc voltage

ie(RF+RS) must fit within the regulation window throughout

the line and load range, as illustrated in Fig. 6. The upper

limit of the regulation window is the cut-off voltage V of

transistor Q1, which is inherent to the transistor selected,

whereas the lower limit of the regulation window is defined

by the full load current. To achieve output voltage regulation,

resistors RB, RS, and RF must be carefully selected to limit the

error current within this regulation window.

Maximum error current iemax occurs at minimum load, as

shown in Fig. 6. At minimum load, less energy is needed to

maintain the output voltage which is why the on time of

switch S1 is very short. Conversely, minimum error current

occurs at full load because a longer on time is needed to store

the required energy. It should be noted that unlike the

standard PWM, whose on time is determined at the moment

the ramp voltage reaches the control voltage, the on time of

this control circuit is determined once sufficient charge is

removed from input capacitance CISS by transistor Q1, which

is turned on the moment base voltage VQbe reaches its

intrinsic cut-off voltage V.

The design constraints for the selection of the control

circuit components for steady state operation are based on the

operating range of the circuit as well as on component

ratings. Specifically, cathode-anode voltage VKA and cathode

current IK of error amplifier TL431 are limited to

VREF<VKA<36 V and 1 mA<IK<100 mA. Voltage VKA can be

expressed as

TABLE 1

SMALL-SIGNAL TRANSFER FUNCTIONS

G VeVo (s)

sz2

M dc

1

C F R CF

1 RB

(s s z1 + 1)(s s z2 + 1)

p1

)(

+ 1 s 2 2O + s QO + 1

sp1

LF

G1

(s s

Kr

C O1 + C F

Mdc

O

VIN

2R S I O

L F (1 C O1 + 1 C F )

1

C F + C O1

G2

GEA(s)

A s s zcomp1 + 1

s s s pcomp 2 + 1

R d1 + R d 2

R d1R d 2 (C EA1 + C EA 2 )

1

CO1R Co1

sz1

Kr

IO N

VIN (1 + N VO VIN )

Kd

R d2

R d1 + R d 2

G3

R F + RS

*

s p1

(1+G1G2G3Mdc)sp1

szcomp1

1

R EA1C EA1

spcomp2

1 C EA1 + 1 C EA 2

R EA1

TABLE 2

STEP-BY-STEP DESIGN PROCEDURE

I1

Imax

1

I1min

REGULATION

WINDOW

VQbe

i emax RF

i eminRF

t

S1

ON

OFF

at minimum and maximum load current

(4)

VKA = VO Vd I K R B .

Since at minimum load, current IK is maximum, as seen from

Fig. 5, where IK = ie/, and, therefore, voltage VKA is at a

minimum. Resistor RB can be expressed as

RB <

min

VO Vd VKA

max

IK

(5)

power dissipation, which, if set to 0.1% of circuits maximum

input power PINmax , is

RS =

max

0.001 PIN

i pk D max 3

S1

(6)

maximum error current i emax , sense resistor RS, and cut-off

voltage V,

i emax (R F + R S ) V ,

(7)

where resistor RF should be selected much greater than

resistor RS, i.e., RF >> RS. At full load, the selection of

resistors RF and RS are further limited by minimum error

current i emin and maximum switch current iSpk1 ,

i emin (R F + R S ) + iSpk1 (max) R S > V

(8)

where i

=V D

L f

.

Finally, error current ie is related to cathode current IK

through dc current transfer ratio of optocoupler IC1,

(9)

ie = IK .

The design procedure for the selection of the control circuit

components RF, RS, and RB for steady state operation can be

broken down to five design steps, summarized in Table 2. It

should be noted that resistor RB, whose value also affects the

voltage loop dc gain, should be chosen as low as possible

while adhering to step 5 in order to maximize the loop gain.

Generally, a 20- resistor serves as a good first iteration for

output voltage VO1 less than 35-V. Later, when system

stability is considered, the value of resistor RB will be reevaluated.

The design of components RA, CZCD, and RZCD can be

determined independently from steps 1-7 of Table 2. For

example, the role of resistor RA is to reduce power loss PIC1

of the phototransistor within optocoupler IC1, where PIC1 is

PIC1 = VCE i emax = (VO 2 i emax R A VQbe )i emax < device power rating (10)

pk (max)

S1

max

IN

max

min

M S

Step 1

Choose I max

based on TL431 current limits

K

Step 2

Step 3

Step 4

Step 5

Step 6

Check I min

from Eq. 8 to ensure within TL431 limits

K

Step 7

max

using Eq. 4 at i K = i min

Check VKA

K

The role of capacitor CZCD is to block dc current during startup, allowing charge to be delivered from the input voltage

through start-up resistor RST until switch S1 turns on for the

first time. Otherwise, capacitor CZCD merely delays the full

turn-on of switch S1 by increasing the length of time spent by

switch S1 in the constant-current region, which is undesirable

from a power conversion efficiency point of view. Therefore,

it is recommended that capacitor CZCD be set ten times greater

than input capacitance CISS. Since capacitors CZCD and CISS

form a voltage divider at the gate of switch S1, steps should

be taken to clamp the gate voltage with zener diode ZD1 to

avoid exceeding the terminal voltage rating. The role of

resistor RZCD is to limit power PZD1 dissipated by zener diode

ZD1,

R ZCD =

max

VIN

(NS2 N P ) VZD1 V .

ZD1

PZD1

(11)

drive switch S1 into its ohmic region (e.g., VO2 = 12-V to 15V is often sufficient).

The value of start-up resistor RST is limited by its power

dissipation, since a high voltage (approximately equal to

input voltage VIN) is across it at all times. As a good rule of

thumb, its power dissipation should be less than 1% of the

converters maximum output power.

B.

Compensation Calculations

amplifier TL431 are determined so that the control loop

achieves the desired regulation accuracy and dynamic

response of the output voltage while maintaining an

acceptable phase margin (typically >45o) in the entire line

and load range. Generally, a good regulation accuracy and

fast transient response requires that closed loop T1 has a high

dc gain and high bandwidth. Typically, a dc gain of 20 to 60

dB is sufficient for good regulation accuracy, whereas a

crossover frequency (fC) of less than one-fourth of the

minimum switching frequency is usually designed for.

The optimum compensation of the voltage control loop

consists of an error amplifier with 2 poles and 1 zero. Error

amplifier transfer function GEA(s), given in Table 1, can be

realized with capacitors CEA1 and CEA2 and resistor REA1. For

a desired crossover frequency fC of loop T1, the selection of

compensation zero fzcomp1 should equal pole frequency f p*1 ,

greater than 4fC, i.e., fzcomp1= f p*1 and fpcomp2 > 4fC. Using this

criteria, compensation components CEA1, CEA2, and REA1 are

then expressed as

(12)

C EA1 = 0.73 2f C R d1 ,

R EA1 = 1 C EA1s *p1 ,

(13)

C EA 2 = C EA1 10 .

(14)

The small-signal block diagram model was verified by

comparing it to measurements made on a 5-V, 2-A selfoscillating flyback converter operating from a 400-V nominal

dc voltage under full load conditions, as shown in Fig. 7. As

can be seen, both the measured and calculated Bode plots

show an excellent agreement up to one-tenth of the minimum

switching frequency, i.e., up to 4 kHz, where the minimum

switching frequency is equal to 40 kHz. Beyond one-tenth of

the switching frequency, the compared phase plots are shown

to diverge, possibly due to a right-half-plane RHP zero which

is not described by either the small-signal model presented in

Table 1, or by the small-signal model presented in [3].

complete small-signal model of the self-oscillating flyback

converter were presented. It was found that the steady-state

operation of the converter can be described by eleven

topological stages. Based on this analysis and the smallsignal model, a step-by-step design procedure for a feedback

control of the circuit was defined. This design procedure was

verified on a 5-V/2-A, off-line experimental circuit. The

measured and calculated loop gain of the experimental

converter are in a very good agreement.

REFERENCES

[1] K. Billings, Switchmode power supply handbook, New York, N.Y.:

McGraw-Hill, Inc., 1989.

[2] L. Hayes and J. Spangler, Pair of controller ics provide critical

conduction switching power supply with voltage and current limiting,

Power Conversion and Intelligent Motion (PCIM) Magazine, pp. 42-50,

Nov. 2000.

[3] J. Lempinen and T. Suntio, Small-signal modeling for design of robust

variable-frequency flyback battery chargers for portable device

applications, IEEE Applied Power Electronics Conf. (APEC) Proc., pp.

548-554, March 2001.

30

III. SUMMARY

20

10

Gain [dB]

10

20

30

40

50

10

100

3

1 .10

frequency [Hz]

1 .10

1 .10

1 .10

1 .10

Calculated Gain

Measured Gain

Breaking the Loop at T1

200

150

phase [deg]

100

50

50

100

10

100

1 .10

frequency [Hz]

Calculated Phase

Measured Phase

Fig. 7 Calculated and measured Bode plots of loop gain T1 of off-line, 5V/ 2-A self-oscillating flyback converter

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