MMIC Design Course Overview

MMIC Design
Device Introduction
Introduction to S-Parameters
RF System Consideration
Amplifier Design Consideration
Power Amplifier Design
1-2
Device Introduction
1-3
Device Introduction
Passive Elements
Introduction to HBT
Introduction to PHEMT
Device Model for RF Circuit
1-4
Device Introduction
Passive Elements
Introduction to HBT
1-5
Overview of MMIC Passive

Elements (1)
Inductor
Type
Value
High
0.01~
impedance 0.5nH
line
Spiral
inductor
0.5~
10 nH
Q-Factor
(10GHz)
30-60
Dielectric
(Metal)
Application
plated gold matching
20~40 plated gold matching,

RF choke
1-6

Elements (2)
Capacitor
Type
Value
Interdi- 0.001~
gitated 0.05pf
MIM
0.1~
100pf
Q-Factor
(10GHz)
Dielectric
(Metal)
Application
coupling,
matching
high
~50
~50
~25
Si3N4
SiO2
Polyimide
1-7
coupling,
matching,
bypass

Elements (3)
Resistor
Type
Value
Dielectric
(Metal)
Thin film
5 ~ 1K
Bulk
10 ~ 10K Implanted
GaAs
NiCr, TaN,
TiWN
1-8
Application
dc biasing,
feedback,
matching
dc biasing

What is high Q?
How to get the high Q inductor?
Resonant frequency
Current density
Accuracy!?
In band
Low frequency
1-9

Limitations
Maximum current density
Maximum voltage drop
Variation
Exact value of resistor
Bias stability
High frequency effects

Transmission line effect
Parasitic inductor
Coupling
1-10
Device Introduction
Passive Elements
Introduction to HBT
1-11
Device Structure of HBT

E
P+-GaAs
C
N+-GaAs
N-AlGaAs
N- -
B
C
GaAs
N+- GaAs
SI GaAs Sub
1-12
Doping Profile of HBT
E
Ne b
exp( )
Pb e
kT
1-13
HBT High Frequency Performance (1)

Cut off frequency, unity current gain, ft
ft = 1/(2*tec)=1/2*(tee+ tb + tc + tcc)
tec=emitter to collector transit time

tee=emitter-base charge time (Kt/q*IC)*Cbe
tb=base transit time (wb2/2*Dn) + Wb/ve
tc=collector depletion layer transit time
tc=collector charge time (KT/q*IC+Re+Rc)*Ccb
1-14
HBT High Frequency Performance (2)

Maximum oscillation frequency,
unity power gain, fmax
fmax=(ft/8*Rb*Cbc)1/2
Rb=base resistance
Cbe=basecollector capacitance
1-15
Advantages of HBTs Over BJTs (1)

Wide-band gap emitter
High base doping
Decreasing base resistance
Low emitter doping

Reducing B-E junction capacitance
High electron mobility & velocity overshoot

Reducing electron transit time
Collector design for higher gain-breakdown
product
1-16
Advantages of HBTs Over BJTs (2)

Semi-insulating substrate
Reducing parasitic capacitance
Better RF performance
High base doping

Less emitter crowding effect
larger emitter width is used for power application
Less high injection effect

high early voltages
1-17
Device Introduction
Passive Elements
Introduction to HBT
1-18
Device Structure of PHEMT

/

S
D
n+-GaAs
n-AlGaAs
AlGaAs
InGaAs
n-AlGaAs
AlGaAs
GaAs
1-19
Material Structure & Energy Band of

HEMT
The sheet charge Qs is controlled by VG

2
(VG VT )
QS =
d2
1-20
Device Introduction
Passive Elements
Introduction to HBT
1-21
Device Model for RF Circuit Simulation (1)

Device model for circuit simulation
S-parameters
Small signal model
Large signal model
Noise model
1-22
Device Model for RF Circuit Simulation (2)

Model verification
ICCAP
DC-IV relationship
S-parameters
Load-pull measurement
Power
Noise
1-23
The Limitations of Gummel-Poon Model (1)

Self-heating Effect
1-24
The Limitations of Gummel-Poon

Model (2)
Transistor Breakdown
Designers need to take care not to exceed the
voltage allowed by the HBTs to ensure the operation
of the circuits.
Emitter Resistance Inaccuracy

Designers should increase the RE specified in the
model by 50% and re-simulate to ensure the circuit
is designed to the specification under self-heating
condition
1-25
Challenges of PHEMT Model

Bias-Dependent Noise Model
Scale Rules
Small signal & large signal model
Parameters scaling
Linearity Consideration
Curtice
EEHEMT
Angilove
1-26
Device Introduction
RF System Consideraton
Introduction
S-parameters
Power & S-Parameters
S-parameters for N-Ports Network
Introduction
S-parameters
Low Frequency and High Frequency

V0
V1
V2
V3
At low frequency
V0V1 V2 V3
At high frequency
V0V1 V2 V3
Incident wave
Reflection wave
The Lump Element Circuit for a

Transmission Line (TEM Wave)
Zs
Ae-jx
Zl
Bejx
Vs
X=0 l
x=l
l
Rx Lx
Gx
Cx
The length of the

transmission line is
divided into many
identical sections x.
Characteristic Impedance
V(z) = Ae
+ Be
+z
= V (z) + V (Z)
A z B +z +
I(z) =
e
e
= I (z) I (z)
Z0
Z0
complex propagation constant
= + j = (R + jL)(G + jC)
characteristic impedance
+ jL
R
Z0 =
G + jC
Input Impedance for

Maximum Power Transfer
Zg
Iin
+
Vg
-
Vin
Z0 ,
ZL
Z in = R in + jX in
Z g = R g + jX g
Zin
2
R in
1
1
*
P = Re[Vin I in ] P = Vg
2
2
(R in + R g ) 2 + (X in + X g ) 2
To maximize P
Conjugate matcing
P
P
= 0,
=0
R in
X in
R in = R g
X in = X g
Z in = Z g * => Pmax =
1 Vg
8 Rg
Introduction
S-parameters
S-Parameters (1)
Short and open circuits for AC signal are difficult to
implement over a broadband range at microwave
frequencies.
The S parameters are defined in terms of traveling
waves.
Termination is easier implemented.
An active two-port might oscillate under short or open
circuit conditions.
S-Parameters (2)
Introducing the normalized notation
a(x)
b(x)
=
=
(x)
Z 0
Z0 is the characteristic impedance

of the transmission line connected
to the port.
(X)
Z 0
a1
b1
a2
b2
Z0
Port1
two port
network
Z0
Port2
S-Parameters (3)
a1
b1
Z01
port1
a2=0
b2
Zout
Z02
port2
b1
S11 =
|a 2 = 0
a1
ZL=Z02
The length of the Z01 & Z02

transmission line is zero
b1=S11a1+S12a2
b2=S21a1+S22a2
impedance of the transmission line produce a2=0. Terminating the

output port with an impedance equal to the characteristic
The output impedance of the network does not have to be

matched to Z02.
S-Parameters (4)
a1
b1
input
Two port
network
a2
b2
output
b1=S11a1+S12a2
b2=S21a1+S22a2
input reflection coefficient with output terminated

b1
S11 = | a 2 = 0
a1
b1
reverse transmission coefficient with input
S12 = | a 1 = 0
terminated
a2
b2
forward transmission coefficient with output
S 21 =
|a 2 =0
terminated
a1
b2
output reflection coefficient with input terminated
S 22 =
| a1 =0
a2
S-Parameters (4)
a1
b1
input
Two port
network
a2
b2
output
b1=S11a1+S12a2
b2=S21a1+S22a2

b1
S11 = | a 2 = 0
a1
b1
S12 = | a 1 = 0
terminated
a2
b2
S 21 =
|a 2 =0
terminated
a1
b2
S 22 =
| a1 =0
a2
S-Parameters (4)
a1
b1
input
Two port
network
a2
b2
output
b1=S11a1+S12a2
b2=S21a1+S22a2

b1
S11 = | a 2 = 0
a1
b1
S12 = | a 1 = 0
terminated
a2
b2
S 21 =
|a 2 =0
terminated
a1
b2
S 22 =
| a1 =0
a2
S-Parameters (4)
a1
b1
input
Two port
network
a2
b2
output
b1=S11a1+S12a2
b2=S21a1+S22a2

b1
S11 = | a 2 = 0
a1
b1
S12 = | a 1 = 0
terminated
a2
b2
S 21 =
|a 2 =0
terminated
a1
b2
S 22 =
| a1 =0
a2
S-Parameters (4)
a1
b1
input
Two port
network
a2
b2
output
b1=S11a1+S12a2
b2=S21a1+S22a2

b1
S11 = | a 2 = 0
a1
b1
S12 = | a 1 = 0
terminated
a2
b2
S 21 =
|a 2 =0
terminated
a1
b2
S 22 =
| a1 =0
a2
Introduction
S-parameters
Power and S Parameters (1)

Z01
V1 (0) = E 1 Z o1 I 1 (0)
1
E1
[V1 (0) + Z o1 I 1 (0)] =
a 1 (0) =
2 Z o1
2 Z o1
I1(0)
+
E1
V1(0)
(Z01)*

Z01
V1 (0) = E 1 Z o1 I 1 (0)
1
E1
[V1 (0) + Z o1 I 1 (0)] =
a 1 (0) =
2 Z o1
2 Z o1
2
PAVS
I1(0)
+
E1
V1(0)
(Z01)*
E1
1
2
1
= P1 (0) = a1 (0) =
= Re[ I 1 ( 0 )* V * 1 ( 0 )]
2
8Z o1
2
+

Z01
V1 (0) = E 1 Z o1 I 1 (0)
1
E1
[V1 (0) + Z o1 I 1 (0)] =
a 1 (0) =
2 Z o1
2 Z o1
I1(0)
+
E1
V1(0)
(Z01)*
PAVS
E1
1
2
1
= P1 (0) = a1 (0) =
= Re[ I 1 ( 0 )* V * 1 ( 0 )]
2
8Z o1
2
+
Available power (PAVS) represents the power available from the

source. It is also the power delivered to the matched load. (Maximum
power delivered to the load)

If load impedance is not equal to (Zo1)*
1
b 1 (0)
2
a 1 (0) =
= P1 (0)
reflected power
1
[V1 (0) + Z o1 I 1 (0)]
2 Z o1
1
b 1 (0) =
[V1 (0) Z o1 I 1 (0)]
2 Z o1
1
a 1 (0)
2
1 b 1 (0)
2
= 1 Re[I 1 (0)V 1 * (0)] = P1 (0)

2
P1(0) represents the power delivered to the load

b1
S11 = | a 2 = 0
a1
S11
b1
a1
2
2
Z01
E
V1
P1
P
avs
|a2 = 0 =
Pavs
Two port
V
network 2
Z02
(P1 is the input power to the

two port network)
S11 represents the ratio of the power reflected from port1

to the power available at port 1.
If S11>1, the power reflected is large than the power

available at port 1. Therefore, port 1 acts as a source of
power and oscillations can occur

Z01
b2
|a 2 =0
S 21 =
a1
V1
Two port
V
network 2
S21
V2
= 2Z 022 = PL = G T
Pavs
E
8Z 01
.
GT represents
the transducer power gain
PL is the power delivered to the load Z02
Z02
Introduction
S-parameters
Generalized Scattering Matrix

for n-Port Network
V1 Z11 Z12 ...

V2 Z 21 Z 22
M = M

VN Z N1 ...
Z1N V1
+
V2
M M
+
Z NN V
N
+
Generalized Scattering Matrix

for n-Port Network
V1 Z11 Z12 ...

V2 Z 21 Z 22
M = M

VN Z N1 ...
Z1N V1
+
V2
M M
+
Z NN V
N
Sii is the reflection coefficient seen looking into port I when all
other ports are terminated in matched loads.
Sij is the transmission coefficient from port j to port i, when all
other ports are terminated in matched loads.
Device Introduction
3-1
Spectral Regrowth
The System Gain Concept
Noise Consideration
Distortion Consideration
Phase Noise Consideration
3-2
Spectral Regrowth
Noise Consideration
3-3
Emission Mask
The signal radiated by the transmitter must
meet the wireless standard.
Modulation mask in IEEE 802.11b DSSS

3-4
Spectral Regrowth (1)

Any signal whose peak envelope power exceeds
the power level which gain compression or AM-PM
occurs will cause signal regrowth.
3-5

The spectrum grows when a variable-envelope signal
passes through a nonlinear system.
Abrupt phase changes in a digitally modulated waveform,
results in envelope variations if a filter limits the bandwidth
Unfiltered
QPSK
Filtered
QPSK
3-6

Modulation
Type
QPSK
Phase
Change
900
1800
Baseband
Filtering
Raised
Cosine
OQPSK
900
/4-DQPSK
450
1350
Raised
Cosine
Raised
Cosine
GMSK
No
Gaussian
3-7
Peak to
Spectral
Average Regrowth
6dB
Highest
5dB
High
3.2-3.4dB
Medium
Low
Spectral Regrowth
Noise Consideration
3-8

dB may be based on power or voltage ratios
P2
V2
dB = 20log(
) = 10log(
)
V1
P1
dBm is a comparison to a reference power of
1mW, and the dBW uses 1W as a reference
dBm = 10log(PmW )
dBW = 10log(PW )
3-9
Spectral Regrowth
Noise Consideration
3-10
Noise Source
Shot noise
Thermal noise
I0
E = 4kTRB
2
n
Available Power
I 2n = 2qI 0 B
E 2n
= kTB
4R
= 4 10 18 mw
= 174dBm (noise floor)
noise power
kT = 1.38 10 23 290
Flicker (1/f) noise
-10dB/octave
fc
3-11
fm
Noise Figure Definitions

The NF is defined as the ratio of the total available
noise power at the output of the amplifier to the
available noise power at the output due to the thermal
noise from the input termination R
P
P
Ni
P
F = No
PNi G A
+ PNa
P
G
Ni
A
F=
PNi G A
PSi
( S / N ) input
PSo
P
PNa
Ni
=
=
+
=
)
F
(G A
1
PSo
( S / N ) output
PSi
PNi
PNo
FdB = 10logF
3-12
Noisy
two-port
GA , PNa
No
ZL
Cascaded Noise Figure

R
PNI
Noisy
two-port
GA1, PN1
GA1PNI+ PN1
Noisy
two-port
GA2, PN2
PNo
G (G P + PN1 ) + PN2
= A2 A1 Ni
F=
PNi G A1G A2
PNi G A1G A2
For the case of n stage

F = F1 +
F2 1 F3 1
F4 1
+
+
+ .......... .
G A1 G A1G A2 G A1G A2 G A3
3-13
PNO
ZL
F2 1
F = F1 +
G A1
Receiver Sensitivity
The minimum detectable signal level is defined:
PMDS = KTB(dBm) + NF(dB) + SNR(dB)
= -174dBm + 10logB (dB ) + NF(dB) + SNR(dB)
K: Boltzmann constant
T: Absolute temperature
B: Bandwidth
NF: Noise figure
SNR: Required signal to noise ratio of the system
3-14
Receiver Sensitivity(2)
sensitivity
S/N
NF
10 logB
noise floor
-174dBm
3-15
Spectral Regrowth
Noise Consideration
3-16
Harmonics
In
fc
Out
fc 2fc 3fc
y(t) = 1Acost + 2 A 2cos 2t +3cos 3t + ....

33 A 3
3 A 3
2 A 2
2 A 2
)cost +
cos2t +
=
+ (1A +
cos3t + .....
2
4
2
4
The term with the input frequency is called the fundamental and the highorder terms are called the harmonics.
3-17
Gain Compression
y(t) = 1Acost + 2 A 2cos 2t + 3cos 3t + ....
2 A 2
33 A 3
2 A 2
3 A 3
=
+ (1A +
)cost +
cos2t +
cos3t + .....
2
4
2
4
As the input signal increases,

the gain term of the
fundamental
output will compress, due to
the sign of a3 is negative.
POUT
P1dB
1dB
PIN, 1dB
3-18
PIN(dBm)
Blocking
y(t) =1x(t) +2x2(t) +3x3(t) +......(x(t ) = A1cos1t + A2cos2t)
3
3 3
2
y(t) = (1A1 + 3A1 + 3A1A2 )cos1t +..........
4
2
for A1 << A2, reduces to
3
2
y(t) = (1 + 3A2 )A1cos1t +..........
2
Strong unwanted signal reduces the gain of a stage for

a small signal in the pass band due to nonlinearities.
3-19
Intermodulation (1)
Input spectrum
In
w1 w2
Output spectrum
w2- w1
2w1- w2 w1 w2 2 w2- w1
2w1 w1+ w2 2w2
3w1 2w1+ w2 w1+2w2 3w2
3-20
Out
Intermodulation (2)
When two signals with different frequencies are applied to a
nonlinear system, the most critical one is the third-order
products. Since it falls right near the desired signal and is
difficult to be filtered out.
In
Out
2w1- w2 w1 w2 2 w2- w1
w1 w2
3-21
Intermodulation (3)
Input signal x(t) = A 1 cos1 t + A 2 cos2 t
y(t) = 1 (A 1 cos1 t + A2 cos 2 t) +2 (A 1 cos1 t + A2 cos 2 t) 2
+3 (A 1 cos1 t + A 2 cos2 t) 3 + ....
= 1 , 2 :
3
33 A 1 3
2
+ 3 A 1 A 2 )cos1 t
(1 A 1 +
4
2
3
33 A 2
3
2
(1 A 2 +
+ 3 A 2 A 1 )cos2 t
4
2
2
33 A 1 A 2
= 21 2 :
cos(21 2 )t
4
2
33 A 1 A 2
= 21 2 :
cos(21 2 )t
4
3-22
Intermodulation (4)
OIP3
A2
21- 2 1 2 2 2- 1
IIP3dBm
m=1
A6 m=3
PdB
=
+ Pin dBm
2
IIP3
3-23
Pin(dBm)
Cascade IP3 Calculation

Pin
G1 , I1 , O1
G2 , I2 , O2
Total OIP3 is :
G3 , I3 , O3
Pout
Gain : G1 G2 G3
IIP3 : I1 I2 I3
OIP3: O1 O2 O3
1
1
1
1
=
+
+
OIP3 t G 2 G 3 O1 G 3 O 2 O 3
The passive components such as filter can have a output IP3

been set to a very large. e.g. 1000dBm
The total IP3 is determined primarily by the stages nearest
the output.
3-24
Spectral Regrowth
Noise Consideration
3-25
Effect of Phase Noise in RF

Communications (1)
Interference
LO
Output
Wanted
Signal
f0
Downconverter
Signals
Improving the phase noise clearly improves the S/N ratio of

the desired signal.
3-26
Effect of Phase Noise in RF

Communications (2)
Q
The downconversion of a QPSK waveform by a mixer

that is driven by a noisy LO results in the constellation.
Thus the bit error rate may increase.
3-27
Device Introduction
4-1
System Consideration
Stability Consideration
Transducer power gain
Avariable Power Gain Circle
Power Gain Circle
Noise Figure Circle
Amplifier design for conditional stability
conditions
Multi-stage Design
4-2
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-3
Noise figure
Gain
Input and output VSWR
Reverse isolation
Stability
IIP3 requirement
DC bias and power consumption
Frequency and bandwidth
Chip size
4-4
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-5
Stability Considerations (1)

ZS
IN
OUT L
Two-port
network
IN = S 11
OUT
S 12 S 21 L
+
1 S 22 L
= S 22
4-6
S 12 S 21 S
+
1 S 11 S
ZL
Stability Considerations (2)

The conditions for unconditional stability
at a given frequency, for passive load and
source termination ( S < 1 , L < 1 )
S12 S21L
<1
IN = S11 +
1 S22L
OUT
S12 S21S
= S22 +
<1
1 S11S
4-7
For stability circles
IN = 1 => L
(S22 S*11)*
OUT = 1 => S
S22
(S11 S 22 )
2
S11
4-8
=
=
S12S21
2
S22
S12S21
2
S11
Stability Circles (1)

Smith chart illustrating stable and
unstable regions in the L plane
IN = 1
IN < 1
IN > 1
S11 < 1
IN = 1
IN > 1
IN < 1
IN = S11 for L = 0
4-9
S11 > 1

Smith chart illustrating stable and
unstable regions in the S plane
OUT = 1
OUT = 1
OUT < 1
OUT > 1
S22 < 1
OUT < 1
OUT > 1
OUT = S 22 for S = 0
4-10
S22 > 1

The conditions for unconditional stability
for all passive sources and loads
CL rL > 1 for
S11 < 1
CS rS > 1 for
S 22 < 1
rL
rS
CL
CS
L plane
S plane
4-11
Stability Condition
The another way for unconditional stability
2
K=
1 S11 S 22 + S11S 22 S12 S 21

2 S12 S 21
>1
= S11S 22 S12 S 21 < 1
OR
K >1
B 1 = 1 + S 11
S 22
4-12
22
2
2
>0
||
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-13
Transducer power gain (1)

M1
PAVS
Two
Port
Network
PIN
M2
PAVN
PL
GT = Transducer power gain = PL/PAVS

(Power delivered to the load) / (power available from the source)
2
1 - S
1 - L
PL
2
=
GT =
S 21
2
2
Pavs
1 S 22L
1 INS
4-14
Transducer power gain (2)

If the network is unconditionally stable, the
conditions for maximum transducer power
gain are
S = IN L = OUT
*
G T,max =
S 21
S12
(K K 2 1)
When the network is conditionally stable, the

maximum can be safely achieved is called the
maximum stable gain (MSG)
S 21
MSG =
S12
4-15
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-16
Available power gain

M1
PAVS
Two
Port
Network
PIN
M2
PAVN
GA = Available power gain = PAVN/PAVS

(Power available from the network)/(power available
from the source)
2
1 - S
Pavn
2
1
GA =
=
S 21
2
Pavs 1 S11S
1 out
4-17
PL
Available Power Gain Circle

GA is the function of
S and [S].
For a given GA , S is
selected from the
constant power gain
circles.
For given S , the maximum output power is obtained

with a conjugate match at the output. The value of L
produces the transducer power gain GT=GA.
4-18
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-19
Power gain
M1
PAVS
Two
Port
Network
PIN
M2
PAVN
PL
GP = Power gain = PL/PIN

(Power delivered to the load)/(power input to
the network)
2
PL
1
2 1 L
Gp =
=
S21
2
2
Pin 1 in
1 S22L
4-20
Power Gain Circle

Gp is the function of L and
[S].
For a given Gp , L is
selected from the constant
power gain circles.
For the given L , the maximum output power is
obtained with a conjugate match at the input. The
value of S produces the transducer power gain
GT=Gp.
4-21
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-22
Noise Figure Circle

The noise figure of a two port amplifier is given by
F = Fmin + 4R n
S opt
(1 S ) 1 +opt
2
Rn is the equivalent noise

resistance of the device.
A small Rn means the NF is
less sensitive to the input
matching
4-23
opt
Low noise amplifier simulation
4-24
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-25
Amplifier design for conditional

stability conditions (1)
Rsmin
Unstable source region
Gpmin
Unstable load region
Source
stability
circle
Gpmin
Rsmin
4-26
Load
stability
circle

Parallel feedback
Resistive feedback will
degrade the noise figure.
Series feedback It can be used to move source

matching and noise matching
closer together.
The feedback inductance will
decrease the gain.
The noise figure improved at
the expense of the gain
4-27

R1
R2
C1
Vdd
C2
R1 can improve the stability for all frequency with no

DC change
R2 can improve low frequency stability with no DC
change and no RF performance degrade
4-28
Power Gain Circle
Noise Figure Circle
conditions
Multi-stage Design
4-29
Multi-stage Design for Stability

Consideration
M1
Q1
M2
Q2
M3
Q1, Q2: Active device

M1, M2, M3: Matching network
The overall stability factor of the two-stage
amplifier does not guarantee overall stability.
The two port stability of the two stage
amplifier muse be considered separately.
4-30
Multi-stage Design for Wide

Band Amplifier
Device
IM
Device
ISM
OM
The interstage matching network can be

designed to given a positive gain slope
which counteracts the gain roll-off of the
transistors.
The input and output matching networks are
designed to 50ohm match over the desired
frequency range.
4-31
4-32
Device Introduction
5-1
Power Amplifier
Gain Match & Power Match
Load Pull System
Load Line Theory
Design Theory of Power Amplifier
Simulation for Power Amplifier

5-2
Power Amplifier
Load Pull System
Load Line Theory

5-3
Single Tone Analysis

1dB gain compression point & output power
Collector efficiency (c) or drain efficiency (d)

c= d=Po/PDC
Power added efficiency (PAE)

PAE=(Po-Pin)/ PDC
Total efficiency (total)

total=Po/(PDC+ Pin)
5-4
Two Tone IMD Analysis

Pout(dBm)
OIP3
P1dB
1dB
Pf1
P2f1-f2
Pf1
P2f1-f2
Pin(dBm)
5-5
Pf2
P2f2-f1
Digital Modulation Analysis
5-6
Power Amplifier
Load Pull System
Load Line Theory

5-7
Gain Match
Power Match
Output tuning for maximum power gives typically

2dB more power than small signal gain match.
Output tuning for maximum power gives typically

0.5~1dB less gain than small signal gain match.
5-8
Power Amplifier
Load Pull System
Load Line Theory

5-9
Load Pull System
Can be used for both power and noise load pull

measurements
5-10
Power Amplifier
Load Pull System
Load Line Theory

5-11
Load Line Theory

Imax
R<Ropt
Bias Point
R>Ropt
Vmin
Vmax
Ropt=(Vmax-Vmin)/Imax
Output Maximum Power
0.25*(Imax)2*Ropt
5-12
R>Ropt
=>Voltage Clipped
R<Ropt
=>Current Clipped
Packaged Effects & Reference

Plane to Load Line Theory
A Ropt
Out
In
Package
A
ZL
5-13
Power Amplifier
Load Pull System
Load Line Theory

5-14
Design Theory
of Power Amplifier
Types of Power Amplifier
Classical Modes of Operation
Fourier Analysis of the Waveforms
Output Termination
PA Stability Issues
Current Gain Collapse in Multifinger HBT
5-15
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-16
Types of Power Amplifiers (1)

Linear operation: Transistor acts as a
current source and the RF power is
proportional to the RF input power.
class A : 100% duty cycle, poor efficiency,
excellent linearity
class B : 50% duty cycle, moderate efficiency,
moderate linearity
class C : <50% duty cycle, excellent efficiency,
poor linearity
class AB: 50%~100%, intermediate
linearity/efficiency between class A and B
5-17
Types of Power Amplifiers (2)

Constant-envelope operation: Transistor
operates as a switch.
Class D: ideal 100% efficiency
Class E: ideal 100% efficiency
Class F: ideal 100% efficiency
Linear modulation(e.g.: QAM) cannot normally be
obtained from constant-envelop amplifiers.
Modulation strategies that are immune to nonlinearity
(e.g.: GMSK) can be obtained from constant-envelop
amplifiers.
5-18
Bias Conditions
Imax
Class A
Class AB
Vknee
Class B
Class C
5-19
Vmax
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-20
Classical Modes of Operation (1)

Vq is the normalized quiescent bias point, defined
by Vt=0,V0=1
Imax
V0
Iq
Vq
Vt
Mode Bias Point(Vq)
A
AB
B
C
0.5
0-0.5
0
<0
Quiescent current Conduction Angle
0.5
0-0.5
0
0
5-21
2pi
pi-2pi
pi
0-pi
Class B operation
Class A operation
5-22
Class AB operation
Class C operation
5-23
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-24
Fourier Analysis
of the Waveforms (1)
i d () = I q + I p k cos
=0
i d () =
- /2 < < /2
- < < - /2; /2 < <
Im a x
[cos - co s(/2)]
1 - co s(/2 )
The dc current is given by

Idc
1
=
2
/2
I m ax
[cos cos(/2 )]d
1
cos(
/2)
/2
The magnitude of nth harmonica is

1
In =
/2
Im ax
[cos cos( /2)]c osnd
1 cos( /2 )
/2
5-25
Fourier Analysis
of the Waveforms (2)
Conduction
angle
(CLASS)
AB
B
5-26
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-27
Output Termination (1)

Under no knee region condition
The RF fundamental output power
P1 =
Vdc I1
2 2
The DC supply power

Pdc = VdcIdc
The power added efficiency

PAE =
P1 Pin
Pdc
The optimum value of load resistor

R opt =
Vdc
I1
5-28
Output Termination (2)
5-29
Input Drive Requirements

In theory, 6dB more
drive power is
needed to achieve
the class B
conditions compare
to class A condition.
Out
Power
(2dB/div)
Through the I-V

characteristic of its
input diode junction
in HBT. The
reduction in class B
power gain may be
as little as 2 dB.
Input power (2dB/div)
5-30
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-31
PA Stability Issues (1)

The circuit must show a k factor great
than unity from low frequency to high
frequency where the gain rolls off to lower
than 1.
But deep class AB or B operation, it is
necessary to increase the quiescent
current to perform the stability analysis
with a representative amount of gain.
5-32

Bias oscillations occur
at very low frequencies,
in the MHz or VHF range.
5-33
5-34
Design Theory
of Power Amplifier
Output Termination
PA Stability Issues
5-35
Current Gain Collapse in

Multifinger HBT
The collapse occurs when suddenly one finger of
the HBT draws most of the collector current,
leading to an abrupt decrease of current gain.
Common emitter I-V curve

of a 2 finger HBT having
a total emitter area of
2*60um2. The base current
is fixed constant each scan
of curve.
5-36
Thermal Effects & Ballasting

Resistor
Emitter
Ballasting
Resistor
Base
Ballasting
Resistor
Used primarily for stability factor

Value can range be around 3 to 5 Ohm total
5-37
Power Amplifier
Load Pull System
Load Line Theory
5-38
Design Steps
of Power Amplifier1
a. Calculate maximum power & current
b. Select Bias Point, Determine Ropt
c. Stability in design frequency
d. Select the input matching circuit
e.
Load pull by output power & gain

compression point
f.
AC load line and DC current when input

power sweep
5-39
Design Steps
of Power Amplifier2
g. Input matching circuit by non-ideal model
h. Repeat step e and step f
i.
Output matching circuit by non-ideal model
j.
Check the stability, sweeping the frequency

all the way down to DC
k.
Make sure the stability to the bias insertion

points
5-40
Calculate Maximum Power

& Current(Q2p8*15*20)
Q2p8*15*20 includes 7ohm per finger emitter
ballasting resistance and 167ohm per base
finger of base ballasting resistance.
Emitter Area
2.8*15*20=840um2
Maximum Current
20KA/cm2*840um2*10-8=168mA
Maximum Output Power
31KW/cm2 *840um2*10-8=260.4mW
5-41
Select Bias Point,

Determine Ropt
Select the bias point by maximum current density

VC=3V
IC=160ma & Ib=1.35ma
Ropt
(3-0.7)/160mA=14.3ohm
Predict output power

0.5*160ma*2.3V=184mW=22.6dBm
5-42
Predict the Output Power

& Gain by Ropt
5-43
Get the Final Ropt

by Load Pull
Set harmonic impedance
Power contour for Pin=7dBm

P1dB=>Pin=7dBm Pout=22dBm
PAE=32%
5-44
Stability Consideration (1)
5-45
Stability Consideration (2)
5-46
Appendix 1
Mixer Design
Mixer Design Consideration
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Image Rejection Mixer
Dual Gate Mixer & Gilbert Cell Mixer
Example
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Mixer Downconverter System (1)
fIF= fLO-fRF
LNA
RF IF
LO
Antenna
LO
fIF=mfLO+nfRF
(m,n=0, 1, 2)
Mixer Downconverter System (2)

LO
Amplitude
IF
RF
Image
Frequency
(Lower side-band RF)
LO
Amplitude IF
Image
RF
Frequency
(Upper side-band RF)
Mixer Upconverter System
Antenna
PA
RF IF
LO
fRF= fLO+fIF fRF=mfLO+nfIF

(m,n=0, 1, 2)
fIF
LO
MMIC Mixers
Mixer category (by mixing device)
Diode mixer
Passive (resistive) FET mixer
Active mixer
Active dual-gate mixer
Mixer topology
Single-ended mixer
Single-balanced mixer
Double-balanced mixer
Doubly double-balanced mixer
Image Rejection mixer
Subharmonic pumped mixer
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Mixer Design Consideration(1)
Conversion gain ( or loss) and noise figure

port to port isolations
Spurious rejection
IP3 requirement
Frequency and Bandwidth
Chip size
LO power
DC bias and power consumption
Input & output VSWR
Mixer Design Consideration(2)

Conversion gain ( or loss)
10 log10 (IF output power/ available RF input power) (dB)
Noise Figure
Ratio of signal to noise at mixer input to signal to noise at
mixer output
Double side band + 3dB Single side band
Port to port isolation (LO->IF, LO->RF, RF->IF)

LO to RF isolation =>
10 log10 (RF port LO output power/ available LO input power)
(dB)
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Single Ended Mixer

RF
IF
LPF
g(t) =
jnw LO t
g
e
n
n =
LO
t
I
Diode is tuned on/off by LO
V
VLO
t
VRF = Vme jmwRF t
i d = VRFg(t) =
g V ej
m = n =
(mw RF + nw LO )t
180-Deg Hybrid Mixer (1)

D1
RF
LO
00
00
00
IF
LPF
1800
D2
IF
VLO VRF
D2
D1
IF
VRF VLO
IF current summation
VLO Vn
D2 D1
Vn VLO
AM noise cancellation
180-Deg Hybrid Mixer (2)

Good isolation, bad match
LO AM noise rejection
Spurious rejection (fIF=mfRF+nfLO)

All (m,n) spurious responses, where m and n are
even, are eliminated.
The (m,n) spurious response is eliminated, if m is
even and n is odd, but not if m is odd and n is even.
Interchanging the LO and RF ports, the (m,n)
response with m odd and n even is rejected.
90-Deg Hybrid Mixer

RF
LO
D1
900
00
00
LPF
IF
900
D2
Good match, bad isolation.

LO noise rejection identical to those of the 180-deg
mixer.
It has the same (m,n) spurious response rejection as
the 180-deg mixer if both m and n are even.
It does not work as a upconverter.
90-Deg Hybrid
0.707 00
100
S11A
Vincident
0.5 S11A00
Vreflect + 0.5 S11B1800
= 1/2(S11A-S11B)
0.707 S11A00
0.707 900
S11B
50
ohm
0.5 S11A900
+ 0.5 S11B900
0.707 S11B900
= 1/2(S11A+S11B) 900
Double Balanced Mixer (1)

R
D3
L
D1
LO
D4
Good port to port

isolation
Broad band width
D2
IF
Rejection of LO AM
noise
Rejection of all
spurious responses
RF
that include an even
harmonic of either of
both the RF or LO
frequencies.
Double Balanced Mixer (2)

RF
LO
IF
L
+
D1
L
+
D3
VLO
VLO
D2
VRF
L -
D4
+
VRF
L -
Since the conductance of D3 and D4 are reverse of Diodes

D1 and D2. So the IF current in diodes D3 and D4 are reverse
from the RF signal.
Microwave Passive Hybrid (1)

1
3
3
Branch line coupler
Rate race coupler
Microwave Passive Hybrid (2)
Wilkinson combiner
Lange coupler
Lumped Element Passive

Hybrid
1
L = 1
= 1.414R
C
Branch line coupler
C0 = 1 2 C1
C1 = 1
R
L
L= R
1 + C1R
Rate race coupler
Active Balun
Out +
Out +
Out-
IN
IN
Out-
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Single Device FET Resistive

Mixer (1)
LO
LO Filter and
Matching
RF Filter and
Matching
IF Filter and
Matching
RF
IF
The LO is applied to the gate with zero DC drain bias. The gate
bias is usually near pinch off.
The time varying channel resistance is used for frequency
mixing. The channel resistance at low signal levels is very
linear, so low distortion results.
In diode or active FET mixers , the strong onlinearity is needed
for efficient mixing, but causes distortion at the same time
Single Device FET Resistive

Mixer (2)
LO
LO Filter and
Matching
RF Filter and
Matching
IF Filter and
Matching
RF
IF
RF applied to drain, IF filtered from drain, LO must

be decoupled so as not to appear at drain.
The FETs channel is purely resistive, its noise is
almost thermal noise.
FET Resistive Ring Mixer

The nodes of the ring are all
virtual grounds to the LO.
LO
IF
The IF connection nodes are all

virtual ground for the RF
The RF connection points are
virtual ground for the IF.
balun
And the gates are virtual ground

for both.
RF
The RF, LO and IF are inherently

isolated.
The mixer has the same IM rejection properties as a diode

ring mixer, all even order IM products are rejected.
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Transistor Gate Mixer Design (1)

LO LO Filter and
Matching
Output Filter
IF
and Matching
RF RF Filter and
Matching

Bias class B for maximum transconductance
component at LO.
Short circuit output at LO and harmonics.
Maximize the fundamental LO frequency component

of the gm(t), and minimize the time-variation of other
circuit elements, especially the gds(t). => Minimize
the mixers noise figure and maximize its gain.
Short circuit input or output at all undesired

frequencies for stability and spurious rejection.
Short circuiting the gate at the IF frequency can

prevent amplifying IF frequency noise.

Effect of the HEMT
Gm profile on mixer
performance
Gm
Vgs
The value of the maximum conversion gain depends on

the maximum value of the transconducdance (Gm).
i d = VRFg(t) =
(mw RF + nw LO )t
g
V
ej
n m
m = n =

Bias class B for maximum transconductance
component at LO.
Short circuit output at LO and harmonics.
Maximize the fundamental LO frequency component

of the gm(t), and minimize the time-variation of other
circuit elements, especially the gds(t). => Minimize
the mixers noise figure and maximize its gain.
Short circuit input or output at all undesired
frequencies for stability and spurious rejection.
Short circuiting the gate at the IF frequency can
prevent amplifying IF frequency noise.
Balanced FET Mixers (1)
(a)
LO
RF
FET
MIXER
1800
RF
Hybrid
Hybrid
IF
FET
MIXER
FET
MIXER
(b)
LO
1800
900
Hybrid
1800
Hybrid
FET
MIXER
IF
Balanced FET Mixers (2)

In (a) case, pumping the devices out of phase,
rejects the odd harmonics of the RF mixing with
even harmonics of the LO. If the LO were applied to
the sigma port, the opposite would occur.
In both (a) and (b) case, they would reject even
harmonics of both RF and LO.
However, FET cannot be reversed as diodes,
balanced FET mixers require an extra hybrid at the
IF.
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Image Rejection Mixer (1)

RF
0
LO 90
HYB
00
D
900
900
HYB
00
00
00
fU fLO fL
00
f Ui fLi
IF
-900 -900
-900-900
00
fLi fUi
900
f L fLO fU
900 900
900
fU fLO fL
fLi fUi
f L fLO fU
900
f Ui fLi
RF and IF spectrum at point A & C RF and IF spectrum at point B & D
Image Rejection Mixer (2)

A
RF
900
900
900
LO
HYB
00
00
fU fLO fL
IF
HYB
00
fLi fLi
00
00
fLi fUi
00
900
fLi fUi
f L fLO fU
00
f Ui fLi
RF and IF spectrum at point A & C
1800
1800
00
fUi fLi
Point D after 900 HYB
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Dual Gate Mixer (1)

IF Bypass
LO
LO
G2
Matching
RF
RF
G1
Matching
Id
0 Vgs2
IF
IF
Matching
LO & RF
Bypass
Vgs1
0
-1
-1
-2
-2
0 1.0 2.0 3.0 4.0 5.0 Vds1
5.0 4.0 3.0 2.0 1.0 0 Vds2
Dual Gate Mixer (2)
D
G2
Vgs2
Vg2s
Id
Vds2
0
Vds
Vg2s G1
Vgs1
-1
S
Vds1
Vgs1
0
-1
-2
-2
0 1.0 2.0 3.0 4.0 5.0 Vds1
5.0 4.0 3.0 2.0 1.0 0 Vds2
Dual Gate Mixer (3)

The LO and RF signals are applied to separate gates,
because the cap between the gate is low, the mixer
have good LO-to RF isolation.
The maximum conversion transconductance gm
occurs when an upper gate fed LO, and the RF
signal fed into the lower gate.
The pumping of these two parameters-gds and gmprovides frequency mixing in the lower FET, and
only gm provides significant mixing.
The dual-gate mixer is worse than the single-gate
mixer in gain and NF.
Dual Gate Mixer (4)

The linearity of dual-gate mixers is better than the
single-gate mixer.
The upper FET is in current saturation over most of
the LO cycle. It operates as a source follower
amplifier for the LO and a common gate amplifier for
the IF.
The upper gate should be grounded at the IF
frequency.
Double-balanced Dual Gate

Mixer
IF
Balun
LO
Balun
RF
Balun
+
+IF
IF
-
+IF
-IF
-IF
+VLO
-VLO
-VLO
+VLO
+VRF
-VRF
+VRF
-VRF
Gilbert Cell Mixer

VCC
IF Load
IF+
IF-
LO+
MIXER
CORE
LO+
LO-
RF+
RFRF STAGE
Iee
The mixer core devices are biased

near cutoff.
The RF stage devices are usually
biased at active region.
The LO signal at the drain of the
differential pair is zero.
Provide good port-to-port
isolation

Mixer & Gilbert Cell Mixer (1)
LO and RF short at the IF load in a dual gate mixer
and a Gilbert cell mixer.
In a Gilbert cell mixer, the LO signal at the drain of
the differential pair is zero.
In a dual gate mixer, the LO signal must exist at the
drain of the lower FET to induce mixing action.
The principle mixing of a dual gate mixer is caused
by modulating the gm by switching the lower FET
between the linear and active region.

Mixer & Gilbert Cell Mixer (2)
The mixing of the switching core of a Gilbert mixer
is caused by modulating the RF current by
switching the FET between cutoff and the active
region.
The nonlinearity is much greater between the cutoff
and active region than between the linear and active
region.
The dual gate mixer has lower conversion gain,
require a larger LO power and usually have better
intermodulation performance.
Introduction
Diode Mixer
Passive Mixer
Active Mixer
Example
Appendix 2
Conclusion
Layout Consideration
Via hole
RF connection line
Coupled line section
Bypass capacitors
Phase symmetry
Current handling
Device direction

Thermal Stability
Power & Linearity
Bias & Stability
Noise Consideration
Matching Consideration
How to be a good RF designer

Know the system spec
Know the performance and model
of device
Know the limitations of different topology
Know the parasitic effect of layout
Know the effect of measurement
and assembly

MMIC Design Course Overview

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MMIC Design

Overview of MMIC Passive

plated gold matching

20~40 plated gold matching,

Overview of MMIC Passive

Overview of MMIC Passive

High frequency effects

Device Structure of HBT

Doping Profile of HBT

HBT High Frequency Performance (1)

tec=emitter to collector transit time

HBT High Frequency Performance (2)

Advantages of HBTs Over BJTs (1)

Low emitter doping

High electron mobility & velocity overshoot

Advantages of HBTs Over BJTs (2)

High base doping

Less high injection effect

Device Structure of PHEMT

Material Structure & Energy Band of

The sheet charge Qs is controlled by VG

Device Model for RF Circuit Simulation (1)

Device Model for RF Circuit Simulation (2)

The Limitations of Gummel-Poon Model (1)

The Limitations of Gummel-Poon

Emitter Resistance Inaccuracy

Challenges of PHEMT Model

Low Frequency and High Frequency

The Lump Element Circuit for a

The length of the

complex propagation constant

Input Impedance for

Z0 is the characteristic impedance

The length of the Z01 & Z02

impedance of the transmission line produce a2=0. Terminating the

The output impedance of the network does not have to be

input reflection coefficient with output terminated

input reflection coefficient with output terminated

input reflection coefficient with output terminated

input reflection coefficient with output terminated

input reflection coefficient with output terminated

Power and S Parameters (1)

Power and S Parameters (1)

Power and S Parameters (1)

Available power (PAVS) represents the power available from the

Power and S Parameters (2)

= 1 Re[I 1 (0)V 1 * (0)] = P1 (0)

P1(0) represents the power delivered to the load

Power and S Parameters (3)

(P1 is the input power to the

S11 represents the ratio of the power reflected from port1

If S11>1, the power reflected is large than the power

Power and S Parameters (4)

Generalized Scattering Matrix

Generalized Scattering Matrix

Modulation mask in IEEE 802.11b DSSS

Spectral Regrowth (1)

Spectral Regrowth (2)

Spectral Regrowth (3)

The System Gain Concept

Flicker (1/f) noise

Noise Figure Definitions

Cascaded Noise Figure