Design for Low Power

Barry Pangrle, Ph.D.

Director, R&D
Power Management
October 21, 2004

Power Management Approaches

Architectural
Hardware vs. Software
Hardware / Software Allocation

System Level
Multi-threshold
Multi-voltage
Clock, data gating
Low-power circuits
Retention latches
Power aware memories

Algorithm/
Implementation
Tradeoffs

Software

Hardware & IP
Multi-threshold, Multi-voltage, SOI, High-K,
Body bias, Copper interconnect, SiGe substrates

Process
2004 Synopsys, Inc. (2) Interoperability Forum

Compilers
Power aware OS
Hibernation modes
Memory Access

CONFIDENTIAL

Galaxy Power Management

Power Management Throughout the Design Flow
Power Compiler

Galaxy

Dynamic and leakage power optimization

DFT
Compiler

Power
Compiler

Module
Compiler

JupiterXT
JupiterXT
Physical
Physical Compiler
Compiler
Astro,
Astro-Rail
Astro, Astro-Rail
Star-RCXT
Star-RCXT

Hercules
Hercules

within DC & PC
RTL power analysis

PrimePower
Milkyway

PrimeTime SI, PrimePower

Design
Design Compiler
Compiler

Gate-level peak and average power analysis

Vector-Free Capability

JupiterXT
Design planning, power network analysis

Astro-Rail
Voltage-drop and electromigration analysis

2004 Synopsys, Inc. (3) Interoperability Forum

CONFIDENTIAL

Power Dissipation In CMOS Designs

Dynamic Power

Pdyn = a f * C * V2
VDD

Switching Power
Load Capacitance
Charge/Discharge

Internal Power
Short Circuit between Power and
Ground during transition
Internal Capacitance within a
Gate

Static Power

Isw
(Gate)

(Subthreshold)

Cload
Ileak

Subthreshold Leakage
Isub = I0(e[-Vth/S] [1-e-qVds/kT]) (at Vgs = 0)

Iint

Gate Leakage

2004 Synopsys, Inc. (4) Interoperability Forum

CONFIDENTIAL

Gnd

90 nm Leakage vs Delay
1000

Ioff (nA/m)

100
10
Ioffn
Ioffp

1
0.1
0.01
0.001
5

10

15

20

Gate Delay (ps)

2004 Synopsys, Inc. (5) Interoperability Forum

CONFIDENTIAL

25

30

90nm Low Vth & High Vth Cells

100000

10000

1000

nW
100

10

0
16
32
48
64
80
96
11
2
12
8
14
4
16
0
17
6
19
2
20
8
22
4
24
0
25
6
27
2
28
8
30
4
32
0
33
6
35
2
36
8
38
4
40
0
41
6
43
2
44
8
46
4
48
0
49
6
51
2
52
8

2004 Synopsys, Inc. (6) Interoperability Forum

CONFIDENTIAL

Multi-Vth Optimization Results

Case Study: 210K instances, 300MHz, initial leakage ~20uW

Pre-route
1-pass
Physical Opt.

Post-route
Cell Swap

Leakage (W)

10.8

11.1

High-Vth (%)

87.5%

89.7%

Meets timing same slack as before Multi-Vth Opt

Checks DRC for better design QoR and closure
2004 Synopsys, Inc. (7) Interoperability Forum

CONFIDENTIAL

Multi-Voltage Design Styles

Voltage Island
Monitor

Voltage Island

Voltage Island

1.2 V, 350 MHz

1.0 V, 250 MHz

Programmable

Voltage Island

Mode
Control

Voltage
Regulators

Multiple Supply
Multi-Voltage Islands

Mode
Control

Voltage
Regulators

Voltage Island
Monitor

Adaptive Voltage Scaling

- Voltage areas with variable Vdd

Dynamic Voltage Scaling

- Voltage areas with fixed,
multiple voltages
- Software controlled modes

- Voltage areas with fixed, single

voltages

2004 Synopsys, Inc. (8) Interoperability Forum

Voltage Island

C
1.5 V, 500 MHz

Monitor

Voltage Island

Voltage Island

Voltage Island

CONFIDENTIAL

- Software controlled modes

IEM Partnership

Multi-VDD Design

Isolation cells and level

shifters for routing
across voltage areas
Timing Constraints

VA

VB

Clock Frequency
Power

VE

VD

VC

Automatic insertion,
optimization & power
routing of special cells
Isolation cells
level shifters
retention registers

2004 Synopsys, Inc. (9) Interoperability Forum

CONFIDENTIAL

Power Gating

Shut down non-active blocks

Reduces leakage power

Savings can be > 99%

State Options:
1) Throw away
2) Scan out to memory
3) Retain locally in retention registers

States are restored or re-initialized when the

blocks are reactivated
Requires isolation cells at the boundaries

2004 Synopsys, Inc. (10) Interoperability Forum

CONFIDENTIAL

Leakage (Gated Ground or VDD)

VDD
cell

Virtual VDD

Virtual VSS

cell
Header

2004 Synopsys, Inc. (11) Interoperability Forum

VSS

CONFIDENTIAL

Footer

Leakage (Gated Ground or VDD)

cell
Enable

1 Transistor / Cluster

2004 Synopsys, Inc. (12) Interoperability Forum

Gate Transistor in Cell

CONFIDENTIAL

Example Retention Register

HVth
LVth

HVth

B2

B2_b

HVth

B1_b

B1

Q
LVth

2004 Synopsys, Inc. (13) Interoperability Forum

CONFIDENTIAL

Retention Register Insertion in Synthesis

Same functionality, different styles

Additional restrictions on cell swapping

Styles on HDL blocks

Set power gating style on named always blocks in Verilog or
VHDL processes

Control pins (save & restore)

Specially handled in synthesis

Additional features supported

Scan Cells
Compile with gate level design
Incremental compile
Physopt

2004 Synopsys, Inc. (14) Interoperability Forum

CONFIDENTIAL

Power Compiler RTL Clock Gating

Synchronous-load-enable Implementation
always
always @
@ (posedge
(posedge CLK)
CLK)
ifif (EN)
(EN)
D_OUT
D_OUT == D_IN
D_IN
D_OUT

Register
Bank

D_IN
EN
CLK

Standard Non Clock Gating Implementation

D_OUT

D_IN

Register
G_CLK
Bank

EN

Latch
CLK

2004 Synopsys, Inc. (15) Interoperability Forum

Power Compiler Gated Clock Implementation

CONFIDENTIAL

Challenge:
Concurrent Placement, Timing, Power & Clocking
Peak &
Average

Power
Slew

IR Drop
Skew

Clocking
Max. Frequency

IR Drop

Placement
IR Drop

Skew
2004 Synopsys, Inc. (16) Interoperability Forum

Timing

CONFIDENTIAL

Path Delays
& Slew

Synopsys Multi-Voltage Flow

Multi-Supply, Multi-Voltage Islands, Multi-Threshold Design
Design
Design Compiler
Compiler
Synthesis
Synthesis

JupiterXT
JupiterXT
Design
Design Planning
Planning

Support throughout
implementation & sign-off flow
Multi-Voltage & Multi-Threshold
synthesis in DC
Power plan synthesis in JupiterXT

Physical
Physical Compiler
Compiler
Implementation
Implementation

Astro
Astro
Implementation
Implementation

PrimeTime
PrimeTime SI
SI
Sign-off
Sign-off

2004 Synopsys, Inc. (17) Interoperability Forum

Multi-Voltage placement & MultiThreshold optimization in PC

Multi-Voltage clock-tree synthesis
& routing in Astro
Sign-off with PrimeTime
CONFIDENTIAL

AMBA DesignWare for AHB & APB Subsystems

2004 Synopsys, Inc. (18) Interoperability Forum

CONFIDENTIAL

Synopsys supplies:

Low Power IEM Design Methodology

Multi-voltage Galaxy Implementation Flow
AMBA DesignWare IP
Low Power
Design Services

2004 Synopsys, Inc. (19) Interoperability Forum

CONFIDENTIAL