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Overload protection
Current limitation
Short-circuit protection
Thermal shutdown
Overvoltage protection
(including load dump)
Fast demagnetization of inductive loads
Reverse battery protection1)
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
Open drain diagnostic output
Open load detection in ON-state
CMOS compatible input
Loss of ground and loss of Vbb protection
Electrostatic discharge (ESD) protection
Product Summary
Overvoltage Protection
Operating voltage
active channels:
On-state resistance RON
Nominal load current IL(NOM)
Current limitation
IL(SCr)
Vbb(AZ)
43
V
Vbb(on)
5.0 ... 34
V
two parallel four parallel
one
200
100
50
m
1.9
2.8
4.4
A
4
4
4
A
Application
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
5
7
9
18
17
14
13
4
8
2
6
1)
Symbol Function
Positive power supply voltage. Design the
Vbb
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
IN1
Input 1 .. 4, activates channel 1 .. 4 in case of
IN2
logic high signal
IN3
IN4
OUT1
Output 1 .. 4, protected high-side power output
OUT2
of channel 1 .. 4. Design the wiring for the
OUT3
max. short circuit current
OUT4
ST1/2
Diagnostic feedback 1/2 of channel 1 and
channel 2, open drain, low on failure
ST3/4
Diagnostic feedback 3/4 of channel 3 and
channel 4, open drain, low on failure
GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2)
GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vbb
Vbb
OUT1
OUT2
Vbb
Vbb
OUT3
OUT4
Vbb
Vbb
With external current limit (e.g. resistor RGND=150 ) in GND connection, resistor in series with ST
connection, reverse load current limited by connected load.
Semiconductor Group
06.96
BTS 711 L1
Block diagram
Four Channels; Open Load detection in on state;
Voltage
source
Overvoltage
protection
Current
limit 1
+ V bb
Gate 1
protection
Leadframe
Channel 1
V Logic
IN1
IN2
ST1/2
Voltage
Level shifter
sensor
Rectifier 1
Logic
ESD
Signal GND
Chip 1
Current
limit 2
Level shifter
Rectifier 2
GND1/2
OUT1
18
Temperature
sensor 1
Open load
Short to Vbb
detection 1
Charge
pump 1
Charge
pump 2
Limit for
unclamped
ind. loads 1
Gate 2
protection
Limit for
unclamped
ind. loads 2
Channel 2
OUT2
Load
Temperature
sensor 2
Open load
Short to Vbb
detection 2
Chip 1
17
R
O1
O2
GND1/2
Load GND
+ V bb
Leadframe
Channel 3
OUT3
14
(equivalent to chip 1)
7
IN3
IN4
ST3/4
Channel 4
OUT4
13
Load
GND3/4
PROFET
Signal GND
Chip 2
R
O3
O4
GND3/4
Chip 2
Load GND
Symbol
Vbb
Vbb
Semiconductor Group
Values
Unit
43
34
V
V
BTS 711 L1
Maximum Ratings at Tj = 25C unless otherwise specified
Parameter
Symbol
Values
Unit
IL
VLoad dump4)
self-limited
60
A
V
Tj
Tstg
Ptot
-40 ...+150
-55 ...+150
3.6
1.9
EAS
150
320
800
mJ
VESD
1.0
kV
V
mA
16
44
35
K/W
VIN
IIN
IST
Thermal resistance
junction - soldering point5),6)
junction - ambient5)
2)
3)
4)
5)
6)
each channel:
one channel active:
all channels active:
Rthjs
Rthja
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a
150 resistor in the GND connection and a 15 k resistor in series with the status pin. A resistor for input
protection is integrated.
RI = internal resistance of the load dump test pulse generator
VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 15
Soldering point: upper side of solder edge of device pin 15. See page 15
Semiconductor Group
BTS 711 L1
Electrical Characteristics
Parameter and Conditions, each of the four channels
Symbol
Tj =-40...+150C:
Tj =-40...+150C:
Tj =-40...+25C:
Tj =+150C:
Undervoltage restart of charge pump
Tj =-40...+150C:
see diagram page 14
Undervoltage hysteresis
Vbb(under) = Vbb(u rst) - Vbb(under)
Tj =-40...+150C:
Overvoltage shutdown
Tj =-40...+150C:
Overvoltage restart
Tj =-40...+150C:
Overvoltage hysteresis
)
8
Tj =-40...+150C:
Overvoltage protection
I bb = 40 mA
7)
8)
Values
min
typ
max
--
165
320
200
400
1.7
2.6
4.1
83
42
1.9
2.8
4.4
100
50
--
--
--
10
mA
ton
toff
80
80
200
200
400
400
dV/dton
0.1
--
V/s
-dV/dtoff
0.1
--
V/s
Vbb(on)
Vbb(under)
Vbb(u rst)
5.0
3.5
--
----
V
V
V
Vbb(ucp)
--
5.6
34
5.0
5.0
7.0
7.0
Vbb(under)
--
0.2
--
Vbb(over)
Vbb(o rst)
Vbb(over)
Vbb(AZ)
34
33
-42
--0.5
47
43
----
V
V
V
V
IL(NOM)
IL(GNDhigh)
At supply voltage increase up to Vbb = 5.6 V typ without charge pump, VOUT Vbb - 2 V
see also VON(CL) in circuit diagram on page 8.
Semiconductor Group
Unit
BTS 711 L1
Parameter and Conditions, each of the four channels
Symbol
Values
min
typ
max
Unit
----
28
44
--
60
70
12
---
2
8
3
12
mA
Protection Functions
Initial peak short circuit current limit, (see timing
diagrams, page 12)
---
5.5
4
---
ms
--
47
--
150
--
-10
---
C
K
---
-610
32
--
V
mV
VON(CL)
Tjt
Tjt
Reverse Battery
Reverse battery voltage 11)
Drain-source diode voltage (Vout > Vbb)
IL = - 1.9 A, Tj = +150C
-Vbb
-VON
9)
10)
Semiconductor Group
BTS 711 L1
Parameter and Conditions, each of the four channels
Symbol
Values
min
typ
max
Diagnostic Characteristics
Open load detection current, (on-condition)
10
-200
each channel, Tj = -40C: I L (OL)
10
-150
Tj = 25C:
10
-150
Tj = 150C:
twice the current of one channel
two parallel channels
four times the current of one channel
four parallel channels
)
12
Open load detection voltage
Tj =-40..+150C: VOUT(OL)
2
3
4
Internal output pull down
Tj =-40..+150C: RO
4
10
30
(OUT to GND), VOUT = 5 V
1
Tj =-40..+150C:
Tj =-40..+150C:
Input turn-off threshold voltage
Tj =-40..+150C:
Input threshold hysteresis
VIN = 0.4 V:
Off state input current
Tj =-40..+150C:
VIN = 5 V:
On state input current
Tj =-40..+150C:
Delay time for status with open load after switch
off (other channel in off state)
Tj =-40..+150C:
(see timing diagrams, page 13),
Delay time for status with open load after switch
off (other channel in on state)
Tj =-40..+150C:
(see timing diagrams, page 13),
Status invalid after positive input slope
Tj =-40..+150C:
(open load)
Status output (open drain)
Zener limit voltage Tj =-40...+150C, IST = +1.6 mA:
ST low voltage
Tj =-40...+25C, IST = +1.6 mA:
Tj = +150C, IST = +1.6 mA:
12)
13)
mA
V
k
RI
2.5
3.5
VIN(T+)
1.7
--
3.5
VIN(T-)
1.5
--
--
-1
0.5
--
-50
V
A
20
50
90
td(ST OL4)
100
320
800
td(ST OL5)
--
20
td(ST)
--
200
600
5.4
---
6.1
---
-0.4
0.6
VIN(T)
IIN(off)
IIN(on)
VST(high)
VST(low)
External pull up resistor required for open load detection in off state.
If ground resistors RGND are used, add the voltage drop across these resistors.
Semiconductor Group
Unit
BTS 711 L1
Truth Table
Channel 1 and 2
Channel 3 and 4
(equivalent to channel 1 and 2)
Chip 1
Chip 2
Normal operation
Channel 1 (3)
Open load
Channel 2 (4)
Channel 1 (3)
Channel 2 (4)
both channel
Overtemperature
Channel 1 (3)
Channel 2 (4)
Undervoltage/ Overvoltage
L = "Low" Level
H = "High" Level
IN1
IN3
IN2
IN4
OUT1
OUT3
OUT2
OUT4
ST1/2
ST3/4
ST1/2
ST3/4
L
L
H
H
L
L
H
L
H
X
L
L
H
L
H
X
L
X
H
L
H
X
X
X
L
H
L
H
L
H
X
L
L
H
L
H
X
L
L
H
L
H
X
X
X
L
H
X
L
L
H
H
Z
Z
H
L
H
X
H
H
H
L
H
X
L
L
L
L
L
X
X
L
L
H
L
H
L
H
X
Z
Z
H
L
H
X
H
H
H
L
L
L
X
X
L
L
L
BTS 711L1
H
H
H
H
H(L14))
H
L
H(L14))
H
L
L15)
H
H(L16))
L15)
H
H(L16))
H
L
L
H
L
H
L
H
BTS 712N1
H
H
H
H
L
H
H
L
H
H
L15)
H
H
L15)
H
H
H
L
L
H
L
H
L
H
X = don't care
Z = high impedance, potential depends on external circuit
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
V
Ibb
bb
V
ON1
V
ON2
Leadframe
I IN1
I IN2
I ST1/2
V
IN1 VIN2 VST1/2
Vbb
IN1
OUT1
5
4
IN2
PROFET
Chip 1
OUT2
ST1/2 GND1/2
I L1
17
I L2
I IN4
I ST3/4
V
OUT1
2
I
GND1/2
R
18
VON3
V
ON4
Leadframe
I IN3
V
IN3 VIN4 VST3/4
Vbb
IN3
OUT3
9
8
IN4
PROFET
Chip 2
OUT4
ST3/4 GND3/4
IGND3/4
R
GND1/2
I L3
13
I L4
V
OUT3
VOUT2
14
VOUT4
GND3/4
14)
15)
Semiconductor Group
BTS 711 L1
Input circuit (ESD protection), IN1...4
R
IN
+ V bb
ESD-ZD I
RI
IN
Z2
IN
Logic
GND
R ST
ST
Z1
GND
R GND
Signal GND
+5V
R ST(ON)
ST
- Vbb
+ 5V
GND
ESDZD
R ST
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of the zener voltage (increase of up to 1 V).
IN
RI
OUT
ST
Power
Inverse
Diode
Logic
GND
RGND
Signal GND
Power GND
+Vbb
VZ
V ON
OUT
PROFET
Power GND
Semiconductor Group
RL
BTS 711 L1
Open-load detection, OUT1...4
ON-state diagnostic condition:
VON < RONIL(OL); IN high
+ V bb
Vbb
IN2
PROFET
OUT1
IN1
V
VON
ON
IN1
OUT2
IN2
ST
GND
OUT
Open load
detection
Logic
unit
V
bb
ST
GND
Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
EXT
PROFET
OUT1
Open load
detection
ST
GND
Signal GND
bb
GND disconnect
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load the whole load
current flows through the GND connection.
Vbb
IN2
PROFET
ST
GND
OUT1
OUT2
IN2
OUT2
OUT
Vbb
high
OFF
Logic
unit
IN1
V
V
IN1 IN2 ST
V
GND
Semiconductor Group
BTS 711 L1
Inductive load switch-off energy
dissipation
E bb
E AS
ELoad
Vbb
IN
PROFET
OUT
L
ST
GND
ZL
EL
{
R
ER
EL = 1/2LI L
While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS=
IL L
(V + |VOUT(CL)|)
2RL bb
ln (1+ |V
ILRL
OUT(CL)|
100
10
1
1
1.5
2.5
IL [A]
Semiconductor Group
10
BTS 711 L1
Typ. on-state resistance
RON [mOhm]
500
Ibb(off) [A]
60
450
50
400
350
Tj = 150C
40
85C
30
300
250
200
25C
150
20
-40C
100
10
50
0
-50
0
0
10
20
30
40
50
100
150
Vbb [V]
200
Tj [C]
IL(OL) [mA]
toff(SC) [msec]
6
140
-40C
120
5
25C
100
80
60
40
4
85C
3
Tj = 150C
2
20
0
0
10
15
20
25
0
-50
30
Vbb [V]
Semiconductor Group
11
50
100
150
200
Tj,start [C]
BTS 711 L1
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
Figure 1a: Vbb turn on:
IN1
IN
IN2
V bb
t d(ST)
ST
*)
V
V
OUT1
OUT
V
OUT2
I L(OL)
ST open drain
IN
IN1
ST
I
V
L1
OUT
L(SCp)
I
L(SCr)
t
ST
off(SC)
t
t
The initial peak current should be limited by the lamp and not by
the initial short circuit current IL(SCp) = 7.5 A typ. of the device.
Semiconductor Group
12
BTS 711 L1
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
IN1/2
IN2
I
+I
L1
L2
I L(SCp)
VOUT1
I L(SCr)
channel 1:
open
load
I L1
off(SC)
t d(ST OL1)
ST1/2
open
load
normal
load
t d(ST OL2)
t d(ST OL1)
d(ST OL2)
ST
t
t
td(ST OL1) = 30 s typ., td(ST OL2) = 20 s typ
IN
IN1
IN2
ST
V
OUT1
OUT
L1
t
d(ST)
t
d(ST OL4)
t
d(ST)
d(ST OL5)
ST
t
The status delay time td(STOL4) allows to distinguish between the
failure modes "open load in ON-state" and "overtemperature".
Semiconductor Group
13
BTS 711 L1
Figure 5c: Open load: detection in ON- and OFF-state
(with REXT), turn on/off to open load
IN1
IN2
V on
channel 2: normal operation
I L1
on-state
off-state
OUT1
bb(over)
bb(u rst)
V
ST
off-state
t d(ST)
d(ST)
t d(ST OL5)
bb(o rst)
bb(u cp)
bb(under)
V bb
t
td(ST OL5) depends on external circuitry because of high
impedance
bb(under)
Vbb
Vbb(u cp)
Vbb(u rst)
V ON(CL)
Vbb(over)
V bb(o rst)
V OUT
OUT
ST open drain
ST
t
t
Semiconductor Group
14
BTS 711 L1
Ordering Code
Q67060-S7000-A2
Pin 15
Semiconductor Group
15