Lokender Singh Shekhawat

50, Fozdar New Park,

Ahmedabad-382345, Gujarat

shekhavl123@gmail.com

+91-8141924263

M.Tech Electronics and Communication Engineer from Nirma University with excellent academic record and keen
interest and practical exposure in the field of SOC Verification, Signal and Power Integrity and Automation.

Internship/training (1 Year- Full Time)

Technical Intern at STMicroelectronics India Ltd.

June15- June16

Project: Building a Testbench for Ethernet Switch

Case study on design which is going to be verified.
Building class based Testbench components such as packet generator, packet driver etc.
Connecting all Testbench component using mailboxes.
Building the top Testbench with Device Under Test (DUT) and then compiling it and simulating it.

Project: System Verilog Assertion and Coverage

Writing immediate assertion which checks whether read_en and write_en signal for SRAM are mutually
exclusive.
Creating coverage for various hit and miss condition.

Project: Building and Simulating Advanced Peripheral Bus (APB) Testbench

Creating APB Transaction and Interface.
Creating APB Driver and Sequencer.
Creating APB Monitor.
Creating APB Agent and Env.
Building Test, Top module and simulating it.

Project: Power Integrity Analysis for Designs and its Automation

Parasitic extraction for PCB, Package, and substrate level interconnects using EM solver tools (Cadence
Sigrity Tool POWERSI).
Power Delivery Network (PDN) optimization for meeting the target impedance requirement in Keysight
ADS
System modeling for High Speed links with integrated board, package, I/O pad ring models, CPM, Output
buffer SPICE netlists and then doing the transient simulations in integrated environment with ADS.
Obtained current profile of buffers under worst case scenario in order to observe the effect of SSN
(Simultaneous Switching Noise).
Co-Simulation of obtained system level models and the total variation in power supply was extracted in
ADS. The extracted power supply profile is then used to obtain the clock jitter.
Done the automation of importing design (i.e. netlist file such as SPICE file), Template design
(Schematic/Layout design) and DDS (Data Display Window) handling for PDN Optimization (Power
Integrity Analysis) in ADS.

Project: Python Interface with Keysight ADS

Within ADS Data Display, it is challenging to write extensive data processing equations for complicated
functionality such as multiple loops and dealing with multi-dimensional data array. We can use AEL
(Application Extension Language: Programming Language of ADS) for data processing, but for large data,
AEL expressions can be slower than other programming languages. So, to overcome this, data is exported
from ADS to python, python will do various computation and then data will read back into the ADS.

Project: S-Parameter Extraction from VNA

Calibration of VNA using SOLT technique.
Extraction of S-Parameters of a differential transmission line using VNA.
Analysis of the co-efficient of S-Parameters.

Technical Skills
Programming Languages

Application Extension Language (Keysight ADS), C, System

Verilog, Verilog

Scripting Languages

TCL, Python, Bash Shell scripts in Linux/VNC

Technical Software Tools

Keysight ADS, Cadence PowerSI, Synopsys HSPICE, ANSYS

Apache RedHawk, ANSYS Apache Sentinel, Network
Simulator, XILINX ISE, HFSS, MATLAB

Technical Skill -Set

Web Development Languages/Skills

Signal Integrity, Power Integrity, SOC Verification,

Physical Design Flow, SPICE Simulation, OVM, UVM
PHP, MySQL, HTML 5, CSS 3, Javascript, JQuery, Bootstrap
4, Wordpress, APIs, Mobile Apps (HTML based), Twitter
Clone using MVC

Trainings and MOOCs Online course

Did an summer internship with Reliance communications:

Exposure to Networking, Switches, IP addressing/sub-netting.
Optical Time Domain Reflectometer (OTDR), E1 carrier systems,
MNP.
UDEMYs Course: VLSI Academy Signal Integrity
UDEMYs Course: Clock Tree Synthesis Part 1
UDEMYs Course: SOC Verification Using System Verilog
UDEMYs Course: Learn System Verilog Assertion and Coverage Coding in Depth
UDEMYs Course: Learn to Build OVM and UVM Test benches from Scratch
UDEMYs Course: The Complete Web Developer Course 2.0

Education
M.Tech EC- (Communication Engineering)
IT-NU, CGPA 8.0/10

2014-16

B.E, Electronics and Communication Engineering

BMIT Jaipur RTU, 72.26%

2009-13

Web Presence

LinkedIn Profile: https://in.linkedin.com/in/lokender-singh-shekhawat-47ab6732 .

Blog Link: www.therakshak.blogspot.in

Extra-curricular Activities

Recently, done a volunteering in Tech Week 2016, STMicroelectronics.

Sports: Snooker, Pool, Table Tennis and Cricket.
Hobbies included programming, reading, travelling and writing blogs.

Declaration

I hereby declare that the above written particulars are true and correct to the best of my knowledge and
belief.

Date & Place

(Lokender Singh Shekhawat)