.8041c Quanta ZQR Aspire-4349

5
=45%/2&.',$*5$0
CHARGER
intel
<MCH Processor>
3/5V SYS PWR

P29
rPGA 988
(37.5mm X 37.5mm)
P14, 15
FDI
CLK
DMI
5GT/s
P4~P7
FDI interface
X4 DMI interface
P20
P0
CLK
FDI
SATA0
DMI
SATA Gen3
ODD (SATA)
P20
intel
SATA Gen2
SATA1
P1
P1
USB 2.0
USB
AU6435-GDL
Int. MIC
Azalia
P17
X'TAL
32.768KHz
P12
P23
HPA00835RTER
CRT
P16
LVDS
P16
HDMI
PCI-Express Gen2
5GT/s
HDA
1RWH
+0QRWVXSSRUW86%
+0QRWVXSSRUW6$7$
RTC
P9
X'TAL
25MHz
P8~P13
P1
X'TAL
25MHz
P6
Mini Card-1
Atheros AR8158L
LPC
SPI
P26
P19
P21
NPCE971
P9
Int. Speaker
P10
Transformer
10/100M
EC
Dual SPI ROM

4Mbit x1 (Basic ME+Braidwood)
P18
P25
RJ45
P22
P34
USB 2.0
ALC271X-VB3
AUDIO CODEC
MIC JACK
Thermal protect
P34
P17
tp
P8
CardReader
+1.8V
(25mm X 25mm)
P24
ht
USB CCD
P4
P34
INT_HDMI
PCI-E
mBGA 989
USB Bluetooth
CougarPoint 0.7
:/
/m
D/B USB*2 P23
P3,P9
discharger
P32
RT8207A
INT_LVDS
yc
<PCH>
M/B USB*1 P23
P31
RT8238
INT_CRT
iGFX Interfaces
HDD (SATA)
5GT/s
CPU +1.05V_VTT
DDR3 PWR
om
p.
2.7GT/s
P30
ISL95835
/x
DDR III - SODIMM 1
CPU CORE PWR

PCI-E
X16
su
Dual Channel DDR III

1066 MHz
DDR III - SODIMM 0
DDR SYSTEM MEMORY
RT8206
SandyBridge
QC /DC 35W
P28
ISL88731
P18
HP
P22
P22
SPI ROM Touch Pad

P25
Keyboard
P24
P24
Fan Driver
Quanta Computer Inc.
(D/A Type) P24
PROJECT : ZQR
Size
Document Number
Rev
1A
Block Diagram
5
www.teknisi-indonesia.com
3
Date:
2
Sheet
Monday, May 09, 2011

1
of
35
POWER PLANE
VOLTAGE
DESCRIPTION
CONTROL
SIGNAL
ACTIVE IN
VIN
+10V~+19V
MAIN POWER
ALWAYS
ALWAYS
+VCCRTC
+3V~+3.3V
RTC POWER
ALWAYS
ALWAYS
+3VPCU
+3.3V
EC POWER
ALWAYS
ALWAYS
+5VPCU
+5V
CHARGE POWER
ALWAYS
ALWAYS
+15V
+15V
CHARGE PUMP POWER
ALWAYS
ALWAYS
+3V_S5
+3.3V
LAN/BT/CIR POWER
S5_ON
S0-S5
+5V_S5
+5V
USB POWER
S5_ON
S0-S5
S0
MAINON
S0
+1.5VSUS
+1.5V
CPU/SODIMM CORE POWER
SUSON
S0-S3
+0.75V_DDR_VTT
+0.75V
SODIMM Termination POWER
MAINON
S0
+VGFX_AXG
variation
Internal GPU POWER
GFX_ON
S0
+1.8V
+1.8V
CPU/PCH/Braidwood POWER
MAINON
S0
MINI CARD/NEW CARD POWER
MAINON
S0
CPU VTT POWER
MAINON
S0
+1.05V
+1.05V
PCH CORE POWER
MAINON
S0
+VCC_CORE
variation
CPU CORE POWER
VRON
S0
LCDVCC
+3.3V
LCD POWER
LVDS_VDDEN
+5V_GPU
+5V
SWITCHABLE PWM IC POWER
dGPU_PWR_EN#
PM_THRMTRIP#
SYS_SHDN#
WIRE-AND
3V/5 V
SYS PWR
SML1ALERT#
PCH
FAN Driver
FAN
SM-Bus
EC
S0
Discrete enable
+0.9V~+1.1V
GPU CORE POWER
+3V_D
Discrete enable
+0.9V~+1.1V
GPU I/O POWER
PG_GPUIO_EN
Discrete enable
+1.5V_GPU
+1.5V
VRAM CORE POWER
PG_1.5V_EN
Discrete enable
+1.8V_GPU
+1.8V
GPU_CRE/LVDS/PLL POWER
+1.5V_GPU
Discrete enable
+1V
+1V
DP/PEG POWER
PG_1V_EN
Discrete enable
CPUFAN#
:/
/m
+GPU_CORE
+GPU_IO
ht
tp
CPU
H/W Throttling
yc
+1.5V
+1.05V or +1.1V
H_ORICHOT#
MAINON
PCH/GPU/Peripheral component POWER
CPU
CORE PWR
/x
HDD/ODD/Codec/TP/CRT/HDMI POWER
+3.3V
NTC
Thermal
Protection
su
+5V
+1.1V_VTT
om
p.
+5V
+3V
+1.5V
Thermal Follow Chart
Power States

PROJECT : ZQR
4
Size
Document Number
Date:
PWR Status & GPU PWR CRL & THRM

7
Sheet
8
of
35
Rev
1A
03
D
+3V_S5
+3V_S5
2.2K
2.2K
SMB_ME0_CLK
+3V_S5
+3VPCU
+3VPCU
+3V_S5
C
<PCH>
2.2K
2.2K
10K
G
SMB_ME1_CLK
SMB_ME1_DAT
NMOS
MBCLK
MBDATA
(25mm X
25mm)
EC
WPCE
791/FLASH
yc
mBGA 989
+3V_S5
+3V_S5
:/
/m
CougarPoint 0.7
NMOS
10K
om
p.
intel
su
+3V_S5
/x
SMB_ME0_DAT
+3V
+3V
+3V_S5
2.2K
2.2K
4.7K
4.7K
Slave ADDRESS :A0H

DDR3 DIMM-0-STD
(5.2H)
Slave ADDRESS :A4H

DDR3 DIMM-1-STD
(9.2H)
WLAN
Mini 3G
SMB_RUN_CLK
SMB_RUN_DAT
tp
SMB_PCH_CLK
NMOS
ht
SMB_PCH_DAT
NMOS

PROJECT : ZQR
Size
Document Number
Date:
Rev
1A
SMBus Address
5
Sheet
1
of
35
Sandy Bridge Processor (DMI,PEG,FDI)
8
8
8
8
8
8
8
8
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
8
8
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
H20
FDI_INT
8
8
FDI_LSYNC0
FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
eDP_COMP
INT_eDP_HPD_Q
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
C15
D15
eDP_AUX
eDP_AUX#
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
AN33
EC_PECI
R26
27,30 H_PROCHOT#
56_4
11 PM_THRMTRIP#
H_PROCHOT#_R
AL32
PM_THRMTRIP#
AN32
PM_SYNC
R24
C34
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
11 H_PW RGOOD
AM34
+1.05V_VTT
R277
PECI
PROCHOT#
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
R273
AP33
V8
43_4 CPU_PLTRST#_R AR33
CLOCKS
CLK_DPLL_SSCLKP
CLK_DPLL_SSCLKN
R8
CPU_DRAMRST#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
AK1 SM_RCOMP_0 R151

SM_RCOMP_1 R358
A5
SM_RCOMP_2 R363
A4
AP29
AP27
XDP_PRDY#
XDP_PREQ#
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCLK
XDP_TMS
XDP_TRST#
PM_SYNC
UNCOREPWRGOOD
TDI
TDO
AR28
AP26
XDP_TDI
XDP_TDO
SM_DRAMPWROK
RESET#
DBR#
140/F_4
25.5/F_4
200/F_4
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
CPU-989P-rPGA
+3V_S5
R153
200/F_4
U7
PM_DRAM_PW RGD_Q
R152
130/F_4 PM_DRAM_PW RGD_R
10,18,19,23,27
PLTRST#
3
74AHC1G09
*39_4
ht
R155
NC VCC
GND OUT
6,34
Q2
R306
10K_4
HPD disable
62_4
51_4
51_4
51_4
*51_4
51_4
51_4
INT_eDP_HPD_Q
R75
1K_4
PEG_ICOMPO signals should

be routed within 500 mils
typical impedance = 14.5 mohms
+1.05V_VTT
eDP Hot-plug
FDV301N
R39
R57
R285
R283
R55
R286
R56
CPU_PLTRST#
*2N7002K
MAINON_ON_G
+1.05V_VTT
H_PROCHOT#
XDP_TDO
XDP_TMS
XDP_TDI
XDP_PREQ#
XDP_TCLK
XDP_TRST#
IN
74LVC1G07GW
Q10
PM_THRMTRIP#
Q3
3 MMBT3904
PROJECT : ZQR
SYS_SHDN#
29,34
Size
Document Number
Rev
1A
Sandy Bridge 1/4

Date:
5
C366
0.1U/10V_4
U12
Processor pull-up(CPU)
PEG_ICOMPI and RCOMPO signals should

be routed within 500 mils
typical impedance = 43 mohms
XDP_DBRST# 8
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
+1.5V_CPU
8 SYS_PW ROK
C168
0.1U/10V_4
8 PM_DRAM_PW RGD
24.9/F_4 PEG_COMP
TP81
AL35 XDP_DBRST#
+1.05V_VTT
R70
10
10
+3V_S5
8,30 IMVP_PW RGD
eDP_COMPIO and ICOMPO signals should

be shorted near balls and routed with
typical impedance <25 mohms
A16
A15
10
10
THERMTRIP#
75_4
CPU_PLTRST#
+1.05V_VTT
24.9/F_4 eDP_COMP
CLK_CPU_BCLKP
CLK_CPU_BCLKN
CATERR#
10K_4
0.1U/10V_4
DP & PEG Compensation
R300
DPLL_REF_CLK
DPLL_REF_CLK#
PRDY#
PREQ#
PM_DRAM_PW RGD_R
CPU-989P-rPGA
+1.05V_VTT
A28
A27
DDR3
MISC
DMI
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
AL33
SKTOCC#
BCLK
BCLK#
JTAG & BPM
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
tp
A21
H19
E19
F18
B21
C20
D18
E17
PCI EXPRESS* - GRAPHICS
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
Intel(R) FDI
8
8
8
8
8
8
8
8
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
TP_CATERR#
TP14
11,27
AN34
MISC
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
8
8
8
8
SKTOCC#
TP73
PROC_SELECT#
THERMAL
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
G22
D22
F20
C21
C26
H_SNB_IVB#
PWR MANAGEMENT
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
G21
E22
F21
D21
SNB_IVB# N.A at SNB EDS #27637 0.7v1
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
/x
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
su
8
8
8
8
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
B28
B26
A24
B23
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
U14B
om
p.
8
8
8
8
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
04
PEG_COMP
yc
B27
B25
A25
B24
J22
J21
H22
:/
/m
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
eDP
8
8
8
8
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
Sandy Bridge Processor (CLK,MISC,JTAG)
U14A
3
Sheet
1
of
35
05
Sandy Bridge Processor (DDR3)

U14C
14
14
14
14
14
14
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CAS#
M_A_RAS#
M_A_WE#
M_A_CLKP1 14
M_A_CLKN1 14
M_A_CKE1 14
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
M_A_CS#0 14
M_A_CS#1 14
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
M_A_ODT0 14
M_A_ODT1 14
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C4
G6
J3
M6
AL6
AM8
AR12
AM15
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA5
AB5
V10
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
/x
SA_CAS#
SA_RAS#
SA_WE#
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
15 M_B_DQ[63:0]
su
AE8
AD9
AF9
M_A_CLKP0 14
M_A_CLKN0 14
M_A_CKE0 14
om
p.
SA_BS[0]
SA_BS[1]
SA_BS[2]
AB6
AA6
V9
M_A_DQSN[7:0] 14
yc
AE10
AF10
V6
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
M_A_DQSP[7:0] 14
M_A_A[15:0] 14
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
15
15
15
M_B_BS#0
M_B_BS#1
M_B_BS#2
15
15
15
M_B_CAS#
M_B_RAS#
M_B_WE#
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
AE2
AD2
R9
M_B_CLKP0 15
M_B_CLKN0 15
M_B_CKE0 15
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
M_B_CLKP1 15
M_B_CLKN1 15
M_B_CKE1 15
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
M_B_CS#0 15
M_B_CS#1 15
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
M_B_ODT0 15
M_B_ODT1 15
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DDR SYSTEM MEMORY B
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
:/
/m
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
tp
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
ht
14 M_A_DQ[63:0]
DDR SYSTEM MEMORY A
U14D
M_B_DQSN[7:0]
15
M_B_DQSP[7:0] 15
M_B_A[15:0] 15
+1.5V_SUS
CPU-989P-rPGA
CPU-989P-rPGA
R160
1K/F_4
R162
1K/F_4
CD_DRAMRST#
14,15 DDR3_DRAMRST#
CPU_DRAMRST#
Q11
2N7002K
10 DRAMRST_CNTRL_PCH
C181
0.047U/10V_4
3
PROJECT : ZQR
R161
4.99K/F_4
Size
Document Number
Rev
1A
Sandy Bridge 2/4

Date:
2
Sheet
1
of
35
Sandy Bridge Processor (POWER)CPU VTT

Spec
C398
*22U/6.3V_8
C397
C396
C395
C384
C332
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
B23 Mount C70, C71 for +Vcc_core overshoot issue. 5/18
+
C70
470u/2V_7343
C71
470u/2V_7343
C321
10U/6.3V_8
C315
*470u/2V_7343
B45 Remove C315 for cost issue. 5/19
C319
10U/6.3V_8
C368
*330U/2V_7343
C405
C410
C413
C412
C109
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
C107
C106
C105
C374
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
C411
C123
C124
C127
C126
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
/x
C59
C373
C57
C58
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
su
C103
C102
C128
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
C418
C417
C404
C416
4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8
C401
*22U/6.3V_8
R65
*short_4
C391
*22U/6.3V_8
C381
*22U/6.3V_8
C370
*22U/6.3V_8
+1.05V_VTT
C67
*22U/6.3V_8
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DATA
C66
*22U/6.3V_8
C87
*22U/6.3V_8
C89
*22U/6.3V_8
B54 Del C442. 5/20
CPU VCCPL
VIDALERT#
VIDSCLK
VIDSOUT
C392
330U/2V_7343
+1.8V
SNB 45W:1.5A
B6
A6
A2
Spec
C439
4.7U/6.3V_6
330uF/7mohm x 1
C422
1U/6.3V_4
VCCPLL1
VCCPLL2
VCCPLL3
C438
1U/6.3V_4
10uF x 1
1uF x 2
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
100/F_4
R248
100/F_4
R315
10/F_4
R317
10/F_4
B10
A10
SENSE
LINES
+VCC_GFX
VCC_AXG_SENSE
VSS_AXG_SENSE
330uF/6mohm x 1
SM_VREF
AL1
10uF x 6
+VDDR_REF_CPU
+VDDR_REF_CPU
Real
CAD Note: +VDDR_REF_CPU should

have 10 mil trace width
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
C171
C165
C166
C153
C159
4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8 4.7U/25V_8
C154
4.7U/25V_8
C155
10U/6.3V_8
+ C156
330U/2V_7343
C161
10U/6.3V_8
CPU SA
SNB 45W: 6A
330uF/7mohm x 1
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
M27
M26
L26
J26
J25
J24
H26
H25
VCCSA_SENSE
H23
FC_C22
VCCSA_VID1
+VCCSA
10uF x 3
C44
4.7U/25V_8
C62
4.7U/25V_8
VCCSA_SENSE
C359
4.7U/25V_8
+ C335
*330U/2V_7343
33
10K_4
C22 H_FC_C22 R72
C24
VCCSA_SEL 33
B
VCCP_SENSE
VSSP_SENSE
31
31
4.5A
+1.5V_SUS
R157
R158
SVID CLK
VR_SVID_CLK
+1.5V_CPU
*short_1206
*short_1206
8
7
6
5
30
Place PU resistor
close to CPU
+1.05V_VTT
MAIND
1
2
3
+1.05V_VTT
Q8
*AO4496
C164
*470P/50V_4
R231
130/F_4
R156
*220_8
SVID DATA
VR_SVID_DATA
VR_SVID_DATA
30
4,34 MAINON_ON_G
R359
*short_8
CPU-989P-rPGA
Place PU resistor
close to CPU
MAIND
Q17
*2N7002E
+1.05V_VTT
R43
75_4
R357
*100K_4
H_CPU_SVIDALRT# R42
43_4
VR_SVID_ALERT#
SVID ALERT
PROJECT : ZQR
VR_SVID_ALERT#
30
Size
Document Number
Rev
1A
Sandy Bridge 3/4

Date:
Q9
*DMN601K-7
+VDDR_REF_CPU
1
+SMDDR_VREF
10uF x 6
+1.5V_CPU
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
CPU-989P-rPGA
+VCC_CORE
VCCSENSE 30
VSSSENSE 30
29,32,34
30
30
Spec
VR_SVID_CLK
R249
10/F_4
Spec
Layout note: need routing

together and ALERT need
between CLK and DATA
AJ35
AJ34
10/F_4
R246
SNB 45W: 5A
VREF
C407
*330U/2V_7343
R247
AK35
AK34
CPU MCH
DDR3 -1.5V RAILS
VCCIO40
VAXG_SENSE
VSSAXG_SENSE
C399
*22U/6.3V_8
C318
C327
C375
C376
C377
C325
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
J23
C409
*330U/2V_7343
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
C326
*22U/6.3V_8
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
+
C110
330u/2V_7343
om
p.
C53
C54
C84
C73
C380
C379
C378
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
yc
C323
C324
C310
C314
C30
C31
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
22uF x 12
:/
/m
C313
*22U/6.3V_8
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
tp
10uF x 10
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
ht
22uF x 16
PEG AND DDR
470uF/4mohm x 4
SVID
Spec
SENSE LINES
SNB 45W:52A
CORE SUPPLY
CPU Core Power
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
SA RAIL
+VCC_GFX
470uF/4mohm x 2
U14G
Spec
+1.05V_VTT
+VCC_CORE
POWER
CPU VGT
SNB 45W:21.5A
22uF x 7 (Non-stuff)
MISC
330uF/6mohm x 2
GRAPHICS
POWER
22uF x 12
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
06
Sandy Bridge Processor (GRAPHIC POWER)
SNB 45W:8.5A
U14F
1.8V RAIL
Sheet

1
of
35
Sandy Bridge Processor (GND)

U14H
U14E
TP18
TP79
TP82
TP17
TP80
TP77
CPU-989P-rPGA
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
AJ31
AH31
AJ33
AH33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ26
RSVD5
B4
D1
RSVD6
RSVD7
TP88
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
J20
B18
A19
RSVD24
RSVD25
VCCIO_SEL
J15
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
L7
AG7
AE7
AK2
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
AR35
AT34
AT33
AP35
AR34
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
B34
A33
A34
B35
C35
RSVD51
RSVD52
AJ32
AK32
VCC_DIE_SENSE
AH27
RSVD54
RSVD55
AN35
AM35
RSVD56
RSVD57
RSVD58
AT2
AT1
AR1
KEY
B1
CPU-989P-rPGA
The CFG signals have a default value of '1' if not terminated on the board.
CFG2
1
A
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
07
CPU-989P-rPGA
Processor Strapping
CFG2
(PEG Static Lane Reversal)
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
RESERVED
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
/x
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
su
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
om
p.
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
yc
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
:/
/m
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
tp
Sandy Bridge Processor (RESERVED, CFG)
U14I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
ht
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
R52
1K/F_4
Normal Operation
Lane Reversed
CFG4
(DP Presence Strap)
Disable; No physical DP attached to eDP
Enable; An ext DP device is connected to eDP
CFG7
(PEG Defer Training)
PEG train immediately following

xxRESETB de assertion
PEG wait for BIOS training
CFG7
R30
*1K/F_4
CFG[6:5] (PCIE Port Bifurcation Straps)

11:
10:
01:
00:
(Default) x16 - Device 1 functions 1 and 2 disabled

x8, x8 - Device 1 function 1 enabled ; function 2 disabled
Reserved - (Device 1 function 1 disabled ; function 2 enabled)
x8,x4,x4 - Device 1 functions 1 and 2 enabled

PROJECT : ZQR
Size
Document Number
Rev
1A
Sandy Bridge 4/4

Date:
5
Sheet
1
of
35
08
+3V
Cougar Point (DMI,FDI,PM)
R10
R12
2.2K_4 INT_LVDS_EDIDCLK
2.2K_4 INT_LVDS_EDIDDATA
Cougar Point (LVDS,DDI)
U13C
U13D
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
4
4
4
4
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AW 24
AW 20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
4
4
4
4
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AY24
AY20
AY18
AU18
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
4
4
4
4
4
4
4
4
FDI_INT
AW 16
FDI_INT
FDI_FSYNC0
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSW VRMEN
A18
DSWVREN
DPW ROK
E22
ICH_RSMRST#
W AKE#
B9
PCIE_WAKE#
PCIE_WAKE# 18,19
CLKRUN# / GPIO32
N3
CLKRUN#
CLKRUN# 27
SUS_STAT# / GPIO61
G8
SUS_STAT#
SYS_PW ROK
PWROK_EC
L22
PW ROK
L10
APW ROK
+3V_S5
SUSCLK / GPIO62
N14
PM_DRAM_PWRGD
B13
DRAMPW ROK
+3V_S5
SLP_S5# / GPIO63
D10
ICH_RSMRST#
C21
RSMRST#
SLP_S4#
H4
SUS_PWR_ACK
K16
SUSW ARN#/SUSPW RDNACK/GPIO30 +3V_S5

SLP_S3#
F4
E20
PW RBTN#
SLP_A#
G10
H20
ACPRESENT / GPIO31
SLP_SUS#
G16
PM_BATLOW#
PM_RI#
E10
A10
BATLOW # / GPIO72 +3V_S5
+3V_S5
RI#
PMSYNCH
SLP_LAN# / GPIO29
AP14
K14
PCH Pull-high/low(CLG)
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
INT_TXLCLKOUTN
INT_TXLCLKOUTP
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
INT_TXLOUTN0
INT_TXLOUTN1
INT_TXLOUTN2
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
INT_TXLOUTP0
INT_TXLOUTP1
INT_TXLOUTP2
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
su
R34
R35
PCH_SUSCLK
27
SUSB#
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
27
2.7K_4
2.7K_4
INT_CRT_DDCCLK
INT_CRT_DDCDAT
16 INT_CRT_BLU
16 INT_CRT_GRE
16 INT_CRT_RED
TP34
16 INT_CRT_DDCCLK
16 INT_CRT_DDCDAT
27
R261
R260
16 INT_CRT_HSYNC
16 INT_CRT_VSYNC
33_4
33_4
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
INT_CRT_DDCCLK
INT_CRT_DDCDAT
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
M47
M49
CRT_HSYNC
CRT_VSYNC
DAC_IREF
T43
T42
DAC_IREF
CRT_IRTN
AP43
AP45
SDVO_STALLN
SDVO_STALLP
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
SDVO_CTRLCLK
SDVO_CTRLDATA
TP33
SLP_LAN#
R53
1K/F_4
PM_SYNC 4
SYNC RS
33ohm for
20ohm for
20ohm for
10ohm for
P38
M39
INT_HDMI_SCL
INT_HDMI_SDA
17
17
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
INT_HDMI_HPD
17
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
INT_HDMI_TXDN2
INT_HDMI_TXDP2
INT_HDMI_TXDN1
INT_HDMI_TXDP1
INT_HDMI_TXDN0
INT_HDMI_TXDP0
INT_HDMI_TXCN
INT_HDMI_TXCP
17
17
17
17
17
17
17
17
DDPC_CTRLCLK
DDPC_CTRLDATA
P46
P42
C
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPC_HPD_PU
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
TP38
ht
CougarPoint_R1P0
AF37
AF36
+3V
TP43
SUSC#
150/F_4
150/F_4
150/F_4
om
p.
P12
R259
R258
R257
yc
SYS_RESET#
SYS_PWROK
DSW
16 INT_TXLOUTP0
16 INT_TXLOUTP1
16 INT_TXLOUTP2
:/
/m
K3
AC_PRESENT
2.37K/F_4
R place close to PCH
XDP_DBRST#
27 DNBSWON#
B
System Power Management
27 ICH_RSMRST#
L_CTRL_CLK
L_CTRL_DATA
/x
FDI_FSYNC1
DMI2RBIAS
4 PM_DRAM_PWRGD
L_DDC_CLK
L_DDC_DATA
T45
P39
2.2K_4
2.2K_4
SDVO_TVCLKINN
SDVO_TVCLKINP
INT. DP
DMI_IRCOMP
+3V_S5
T40
K47
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA
R33
R32
16 INT_TXLOUTN0
16 INT_TXLOUTN1
16 INT_TXLOUTN2
BH21
PWROK_EC
L_BKLTCTL
BG25
+3V
P45
16 INT_TXLCLKOUTN
16 INT_TXLCLKOUTP
49.9/F_4 DMI_COMP
SUSACK#
16 INT_LVDS_BRIGHT
TP20
750/F_4
C12
L_BKLTEN
L_VDD_EN
R51
R307
XDP_DBRST#
27
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
DMI_ZCOMP
SUS_PWR_ACK
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BJ24
J47
M45
16 INT_LVDS_EDIDCLK
16 INT_LVDS_EDIDDATA
R302
DMI2RBIAS
16 INT_LVDS_BLON
16 INT_LVDS_DIGON
+3V
tp
+1.05V_VTT
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
4
4
4
4
4
4
4
4
Digital Display Interface
BE24
BC20
BJ18
BJ20
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
LVDS
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
CRT
4
4
4
4
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI
BC24
BE20
BG18
BG20
INT. HDMI
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI
4
4
4
4
DDPD_HPD_PU
+3V
CougarPoint_R1P0
Direct Connect
Dock Support
Switchable Graphics Device Down Topology
Switchable Graphics Dock Support
DDPC_HPD_PU
R48
10K_4
DDPD_HPD_PU
R287
10K_4
Follow PDG eDP disable guide
System PWR_OK(CLG)
+3V_RTC
+3V_S5
+3V_S5
+3V_S5
+3V
R309
330K_4
R326
10K_4
R353
10K_4
PM_BATLOW#
R105
8.2K_4
R337
*1K_4
PCIE_WAKE#
R329
10K_4
C150
*0.1U/10V_4
U6
ICH_RSMRST# R303
10K_4
SLP_LAN#
R91
*10K_4
SYS_PWROK
R111
10K_4
SUS_PWR_ACK
R324
10K_4
AC_PRESENT
R83
10K_4
SYS_PWROK
SYS_PWROK
DSWVREN
U5
IMVP_PWRGD_R
2
4
C142
*2.2U/6.3V_4
R409
0_4
PM_RI#
IMVP_PWRGD 4,30
GFX_PWRGD 30
PWROK_EC
*TC7SH08
TC7SH08
2
4
R310
*330K_4
Low = Disable
R145
100K_4
PM_DRAM_PWRGD R319
On Die DSW VR Enable

High = Enable (Default)
8.2K_4
XDP_DBRST#
R350
CLKRUN#
200/F_4
PROJECT : ZQR
Size
B05
5
3
Date:
2
Document Number
Rev
1A
Cougar Point 1/6
Use R409 to exchange U5, C142 for saving cost 05/17
Sheet

1
of
35
RTC Circuitry(RTC)
+3V_RTC
U13A
C400
1U/6.3V_4
18P/50V_4
*SHORT_ PAD1
RTC_X1
A20
RTC_X2
C20
RTC_RST#
D20
SRTC_RST#
20K_4
SRTC_RST#
+3V_RTC
1M_4
J1
K22
PCH_INVRMEN
C17
C406
1U/6.3V_4
21
SPKR
AAA-BAT-054-K01
bat-23_2-4_2
21
ACZ_BITCLK_R
N34
ACZ_SYNC_R
L34
SPKR
T10
ACZ_RST#_R
K34
E34
ACZ_SDIN0
G34
TP25
ACZ_BITCLK
33_4
ACZ_BITCLK_R
C34
A34
EMI
R64
33_4
ACZ_SYNC_R_1
21
ACZ_RST#
21
ACZ_SDOUT
R58
33_4
ACZ_RST#_R
R288
33_4
ACZ_SDOUT_R
TP83
ACZ_SDOUT_R
A36
PCH_GPIO33
C36
N32
B41 Add a MOSFET Q26,R410,R412 to separate CODE SYNC and PCH Strap signal to avoid leakage issue. 5/19
10K_4
3 ACZ_SYNC_R
1
R412
Q26
2N7002K
1M_4
PCH JTAG Debug (CLG)
Pin Name
B
SPKR
R144
210/F_4
ht
INTVRMEN
R124
100/F_4
R125
100/F_4
GNT1# / GPIO51
GPIO19
PCH Dual SPI (CLG)
K5
PCH_JTAG_TDO
H1
PCH_SPI_CLK
T3
PCH_SPI_CS0#
Y14
R333
*10K_4
PCH_SPI_CS1#
V4
PCH_SPI_SO
U3
W25X32VSSIG: AKE39ZP0N00
HDA_SDO
DF_TVS
R126
R131
R103
*short_4
*short_4
*short_4
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
1
6
5
2
3
+3V
R102
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SYNC
SPKR
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_RST#
HDA_SDIN0
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
HDA_SDO
HDA_DOCK_EN# / GPIO33
+3V
HDA_DOCK_RST# / GPIO13
+3V_S5
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TCK
JTAG_TMS
JTAG_TDI
SATAICOMPO
SATAICOMPI
JTAG_TDO
SATA3RCOMPO
SATA3COMPI
SPI_CLK
SATA3RBIAS
LAD0
LAD1
LAD2
LAD3
D36
SERIRQ
V5
SPI_MOSI
+3V
SATA0GP / GPIO21
SPI_MISO
+3V
SATA1GP / GPIO19
R115
R121
8.2K_4
*10K_4
TP23
TP26
SERIRQ
AM3
AM1
AP7 SATA_TXN0_C
AP5 SATA_TXP0_C
C272
C274
0.01U/25V_4
0.01U/25V_4
AM10
AM8
AP11 SATA_TXN1_C
AP10 SATA_TXP1_C
C101
C112
0.01U/25V_4
0.01U/25V_4
27
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
20
20
20
20
SATA HDD
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
20
20
20
20
SATA ODD
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
TP45
TP41
TP113
TP114
Y11
SATA_COMP
R101
37.4/F_4
AB13
SATA3_COMP
R104
49.9/F_4
AH1
SATA3_RBIAS
R342
750/F_4
Y10
+1.05V_VTT
AB12
R347
SATALED#
+3V
SERIRQ
PCH_ODD_EN
LFRAME# 19,27
E36 PCH_DRQ#0
K36 PCH_DRQ#1
SPI_CS0#
SPI_CS1#
19,27
19,27
19,27
19,27
10K_4
+3V
P3
V14
PCH_ODD_EN
P1
BBS_BIT0
CougarPoint_R1P0
Strap description
Sampled
No reboot mode setting
PWROK
0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode
Top-Block Swap Override
PWROK
Integrated 1.05V VRM enable
ALWAYS
Boot BIOS Selection 1 [bit-1]
PWROK
Configuration
Boot BIOS Selection 0 [bit-0]
PWROK
R116
*1K_4
0 = "top-block swap" mode

1 = Default (weak pull-up 20K)
R264
*1K_4
Should be always pull-up
R304
330K_4
+3V
+3V_RTC
GNT0#
1
0
SPKR
PCI_GNT3# 10
PCH_INVRMEN
R266
*1K_4
Boot Location
R348
*1K_4
SPI
R272
*1K_4
BBS_BIT1 10
R334
*1K_4
BBS_BIT0
+3V
GNT1#
LPC
Flash Descriptor Security

DMI/FDI Termination voltage
RSMRST
0 = Override
1 = Default (weak pull-up 20K)
PWROK
0 = Set to Vss
1 = Set to Vcc (weak pull-down 20K)
RSMRST#
0 = Disable
1 = Enable (Default)
+3V
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
HDA_BCLK
C38
A38
B37
C37
Default weak pull-up on GNT0/1#

[Need external pull-down for LPC BIOS]
MX25L3205DM2I-12G: AKE39FP0Z00
U4
A
T1
PCH_SPI_SI
tp
GNT3# / GPIO55
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TCK
R338
51_4
PCH_JTAG_TDI
PCH Strap Table
+3V_S5
R143
210/F_4
H7
:/
/m
+3VPCU
J3
PCH_JTAG_TMS
yc
ACZ_SYNC_R_1
TP115
R410
SERIRQ
om
p.
PCH_JTAG_TCK
+5V
+3V
INTVRMEN
su
C39
*10p/50V_4
ACZ_SYNC
INTRUDER#
LDRQ0#
LDRQ1# / GPIO23
SATA 6G
1
2
R54
FWH4 / LFRAME#
SRTCRST#
CON1
HDA Bus(CLG)
RTCRST#
*SHORT_ PAD1
20MIL
21
G22
SM_INTRUDER#
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
SATA
C387
1U/6.3V_4
R299
1K_4
R80
RTCX2
IHDA
R305
RTCX1
/x
30mils
C390
JTAG
1
BAT54C
R298
10M_4
LPC
Y2
32.768KHZ
RTC_RST#
J2
RTC
20K_4
SPI
R301
+3V_RTC_1
3
4
+3VPCU
20MIL
18P/50V_4
2
1
C389
D19
21
09
Cougar Point (HDA,JTAG,SATA)
20mils
1
2
PCH2(CLG)
CE#
SCK
SI
SO
VDD
HOLD#
WP#
VSS
GPIO28
8
7 R146
3.3K_4
On-die PLL Voltage Regulator
HDA_SYNC
On-Die PLL VR Voltage Select
RSMRST
0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V
GPIO8
Integrated Clock Chip Enable
RSMRST#
Should be pull-down
(weak pull-up 20K)
SPI_MOSI
iTPM function Disable
APWROK
0 = Default (weak pull-down 20K)

1 = Enable
NV_ALE
Intel Anti-Theft HDD protection
PWROK
0 = Disable (Internal pull-down 20kohm)
+3V
ME_WR#
27
R327
R328
R138
R290
R284
*1K_4
*Short_4
2.2K_4
1K_4
+1.8V
ACZ_SDOUT_R
B06
Change Bottom side 0 R284 to short pad for cost and
SMT cycle time issue. 5/17
DF_TVS
11
H_SNB_IVB# 4
*1K_4
PLL_ODVR_EN
11
A
+3V_S5
R61
1K_4
ACZ_SYNC_R
C144
*22P/50V_4
SPI Flash
3.3K_4
REV: B modify footprint
C151
0.1U/10V_4
3

PROJECT : ZQR
Size
Document Number
Date:
Rev
1A
Cougar Point 2/6

2
Sheet
1
of
35
10
Cougar Point-M (PCI-E,SMBUS,CLK)

U13B
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
+3V
+3V
+3V
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
+3V
+3V
+3V
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
+3V
+3V
+3V
+3V
MPC_PWR_CTRL#
dGPU_PWM_SELECT#
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH
G42
G40
C42
D44
TP44
PCI_PME#
K10
PCI_PLTRST#
C6
H49
H43
J48
K42
H40
CLK_PCI_FB_R
CLK_PCI_LPC_R
CLK_PCI_EC_R
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
C56
C49
PCIE_TXN6_LAN_C
PCIE_TXP6_LAN_C
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
USBP1- 25
USBP1+ 25
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
TP84
TP87
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
25
25
25
25
25
25
J2
AB49
AB47
CLKREQ_WLAN#
V10
Mini - 3G
EXT/B-USB1-1
EHCI1
BlueTooth
PCIE_CLKREQ_3G#
BlueTooth (reserve)
WLAN CLK
19 CLK_PCIE_WLANN
19 CLK_PCIE_WLANP
CLK_PCIE_WLANN
CLK_PCIE_WLANP
19 CLKREQ_WLAN#
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
TP30
TP27
USBP12USBP12+
USBP8- 16
USBP8+ 16
USBP9- 25
USBP9+ 25
USBP10- 19
USBP10+ 19
CCD
EHCI2
USBP12- 23
USBP12+ 23
Y37
Y36
PCIE_CLKREQ_REV0#
Mini Card (WLAN)

Card Reader
R291
22.6/F_4
Card reader CLK
USB_OC0#
USB_OC0# 25
USB_OC2#
USB_OC3#
USB_OC4#
PCIE_CLKREQ5#
PCIE_CLKREQ_LAN#
18 PCIE_CLKREQ_LAN#
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLK_PCIE_REQ7#
tp
1
2
3
4
5
K12
AK14
AK13
TP35
TP37
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
SMB_PCH_DAT
A12
DRAMRST_CNTRL_PCH
C8
SMB_ME0_CLK
G12
SMB_ME0_DAT
C13
SML1ALERT#_R
E14
SMB_ME1_CLK
M16
SMB_ME1_DAT
R355
R330
R112
R89
R140
R137
R106
+3V
USB_OC7#
USB_OC0#
USB_OC6#
USB_OC1_5#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
R22
R25
R27
R38
8.2K_4
8.2K_4
8.2K_4
8.2K_4
5
D
For LAN
R322
*0_4
SML1ALERT# 11,26
For EC
M7
CL_CLK1 19
T11
CL_DATA1 19
P10
CL_RST1# 19
M10 PCIE_CLKREQ_PEG#
TP49
AB37 CLK_PCIE_VGAN
AB38 CLK_PCIE_VGAP
TP22
TP21
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
AU22
CLK_CPU_BCLKN
CLK_CPU_BCLKP
CLKOUT_DP_N
CLKOUT_DP_P
AM12
AM13
CLK_DPLL_SSCLKN 4
CLK_DPLL_SSCLKP 4
4
4
C
CLKIN_DMI_N
CLKIN_DMI_P
+3V
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_GND1_N
CLKIN_GND1_P
+3V_S5
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
+3V_S5
CLKIN_SATA_N
CLKIN_SATA_P
+3V_S5
CLKIN_PCILOOPBACK
REFCLK14IN
BF18 CLK_BUF_PCIE_3GPLLN
BE18 CLK_BUF_PCIE_3GPLLP
BJ30 CLK_BUF_BCLKN
BG30 CLK_BUF_BCLKP
G24 CLK_BUF_DREFCLKN
E24 CLK_BUF_DREFCLKP
AK7 CLK_BUF_DREFSSCLKN
AK5 CLK_BUF_DREFSSCLKP
K45 CLK_PCH_14M
H45 CLK_PCI_FB
C351
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
V47 XTAL25_IN
V49 XTAL25_OUT
27P/50V_4
R255
1M_4
PEG_B_CLKRQ# / GPIO56 +3V_S5
Y1
25MHz
C344
XCLK_RCOMP
Y47 XCLK_RCOMP R31
90.9/F_4
27P/50V_4
+1.05V_VTT
CLKOUT_PCIE6N
CLKOUT_PCIE6P
+3V_S5
CLKOUT_PCIE7N
CLKOUT_PCIE7P
+3V
CLKOUTFLEX0 / GPIO64
K43
+3V
F47
+3V
+3V
+3V_S5
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
SKU_ID1 11
CLK_FLEX1
TP74
H47 CLK_FLEX2
TP76
K49
EXT48MHZ 23
SMBus/Pull-up(CLG)
SMBus(PCH)
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
PCIE_CLKREQ0#
PCIE_CLKREQ_REV0#
PCIE_CLKREQ_REV1#
PCIE_CLKREQ5#
PCIE_CLKREQ_LAN#
CLK_PCIE_REQ6#
CLK_PCIE_REQ7#
27
10K_4
10K_4
PCIE_CLKREQ_3G#
CLKREQ_WLAN#
10K_4
*10K_4
PCIE_CLKREQ_PEG#
+3V
R87
2.2K_4
MBCLK2
SMB_ME1_CLK
R110
SMB_PCH_CLK
4.7K_4
Q5
2N7002K
1
Q7
+3V_S5
SMB_RUN_CLK 14,15,19
2N7002K
+3V
+3V_S5
+3V
R142
R141
R40
PLTRST#
4,18,19,23,27
MPC_PWR_CTRL#
GPIO54
dGPU_PWM_SELECT#
R364
100K_4
10
9
8
7
6
1
2
3
4
5
DGPU_HOLD_RST#
EXTTS_SNI_DRV1_PCH
dGPU_EDIDSEL#
DGPU_SELECT#
R294
R292
10K_4
10K_4
27
MBDATA2
CLK_BUF_PCIE_3GPLLN
CLK_BUF_PCIE_3GPLLP
CLK_BUF_DREFCLKN
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
Low = MPC ON
High = MPC OFF (Default)
R50
SMB_ME1_DAT
SMB_PCH_DAT
Q4
2N7002K
MPC Switch Control
MPC_PWR_CTRL#
R94
R313
R311
R82
R79
R107
R113
R262
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
10K_4
SMB_RUN_DAT 14,15,19
2N7002K
+3V_S5
*1K_4
3
Q6
R321
1K_4
DRAMRST_CNTRL_PCH
R93
R109
R100
R331
R95
R320
10K_4
2.2K_4
2.2K_4
2.2K_4
2.2K_4
10K_4
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R

PROJECT : ZQR
Size
Document Number
Date:
CLOCK TERMINATION for FCIM

4
4.7K_4
A
CLK_BUF_BCLKN
CLK_BUF_BCLKP
10KX8
MPC_PWR_CTRL#
R84
2.2K_4
DRAMRST_CNTRL_PCH
+3V_S5
C440
0.1U/10V_4
CL_DATA1
SMB_PCH_CLK
C9
+3V_S5
R351
R362
PLTRST#
CL_CLK1
CLKOUT_PCIE2N
CLKOUT_PCIE2P
+3V
SML1DATA / GPIO75
SMBALERT#
+3V
10KX8
U16
TC7SH08FU
+3V_S5
+3V_S5
CLK_REQ/Strap Pin(CLG)
+3V_S5
SML1CLK / GPIO58
E12
H14
CougarPoint_R1P0
ht
10
9
8
7
6
T13
V38
V37
R314
USB_OC2#
USB_OC3#
+3V_S5
+3V_S5
CLKOUT_PCIE5N
CLKOUT_PCIE5P
E6
CLK_PCIE_REQ6#
+3V_S5
USB_OC4#
SML1ALERT# / PCHHOT# / GPIO74
CLKOUT_PCIE0N
CLKOUT_PCIE0P
V45
V46
V40
V42
PCI/USBOC# Pull-up(CLG)
SMBUS
PERN6
PERP6
PETN6
PETP6
AB42
AB40
USB_OC1_5# 25
USB_OC6#
USB_OC7#
PCI_PLTRST#
+3V_S5
L12
L14
CLK_PCIE_LANN
CLK_PCIE_LANP
18 CLK_PCIE_LANN
18 CLK_PCIE_LANP
On board LAN CLK
A8
Y43
Y45
PCIE_CLKREQ_REV1#
USB_BIAS
M1
AA48
AA47
TP24
TP19
EXT/B-USB1-2
B33
A14
K20
B17
C16
L16
A16
D14
C14
PCIE_CLKREQ0#
MB/B-USB1-1
SML0CLK
SML0DATA
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
SML0ALERT# / GPIO60
CLOCKS
Y40
Y39
USBP1USBP1+
CougarPoint_R1P0
PLTRST#(CLG)
0.1U/10V_4
0.1U/10V_4
+3V_S5
/
C33
GPIO59
GPIO40
GPIO41
GPIO42
GPIO43
/ GPIO9
GPIO10
GPIO14
PCIE_RX6PCIE_RX6+
PCIE_TX6PCIE_TX6+
AT12
BF3
USBRBIAS#
OC0# /
OC1# /
OC2# /
OC3# /
OC4# /
OC5#
OC6# /
OC7# /
19
19
19
19
WLAN
SMBDATA
Link
TP117
SMBCLK
Controller
NV_ALE
PME#
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
PERN3
PERP3
PETN3
PETP3
BG37
BH37
AY36
BB36
AY5
BA2
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS
BG36
BJ36
AV34
AU34
SMBALERT# / GPIO11
C46
C44
E40
PERN2
PERP2
PETN2
PETP2
+3V_S5
dGPU_EDIDSEL#
DGPU_SELECT#
GPIO54
BE34
BF34
BB32
AY32
BF36
BE36
AY34
BB34
AT8
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
PCI
PIRQA#
PIRQB#
PIRQC#
PIRQD#
D47
E42
F46
22_4
22_4
22_4
RSVD28
RSVD29
K40
K38
H38
G38
TP15
TP13
CLK_PCI_FB R263
R29
R49
RSVD26
RSVD27
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
TP16
19 CLK_PCI_LPC
27 CLK_PCI_EC
RSVD25
PERN1
PERP1
PETN1
PETP1
PCI_GNT3#
AV5
AV10
BG34
BJ34
AV32
AU32
BBS_BIT1
RSVD23
RSVD24
PCIE_TXN1_C
PCIE_TXP1_C
0.1U/10V_4
0.1U/10V_4
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
C42
C41
FLEX CLOCKS
TP12
TP11
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
PCIE_RX1PCIE_RX1+
PCIE_TX1PCIE_TX1+
TP29
TP28
TP31
TP32
:/
/m
AT10
BC8
18
18
18
18
/x
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
RSVD5
RSVD6
On Board LAN
su
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
AY7
AV7
AU3
BG4
om
p.
TP21
TP22
TP23
TP24
RSVD1
RSVD2
RSVD3
RSVD4
yc
B21
M20
AY16
BG46
USB
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD
U13E
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
PCI-E*
Cougar Point-M (PCI,USB,NVRAM)
Rev
1A
Cougar Point 3/6

2
Sheet
1
10
of
35
Cougar Point (GPIO,VSS_NCTF,RSVD)
11
U13F
S_GPIO
C40
TACH1 / GPIO1
+3V
+3V
TACH5 / GPIO69
B41 R280
BOARD_ID1
H36
TACH2 / GPIO6
+3V
+3V
TACH6 / GPIO70
C41 R276
1.5K/F_4
EC_EXT_SCI#
E38
TACH3 / GPIO7
+3V
+3V
TACH7 / GPIO71
A40 R279
1.5K/F_4
G2
GPIO15
dGPU_PWROK
TP10
D40
BIOS_REC
T5
CR_WAKER#
E8
GPIO27
P8
GPIO27
DSW
GPIO28
+3V_S5
GPIO35
TP42
DMI_OVRVLTG
V8
SATA2GP / GPIO36
+3V
+3V
M5
SATA3GP / GPIO37
MFG_MODE
N2
SLOAD / GPIO38
BOARD_ID0
M3
SDATAOUT0 / GPIO39
+3V
SDATAOUT1 / GPIO48
+3V
R148
*short_4
V13
CRIT_TEMP_REP#
+3V
SATA5GP / GPIO49
D6
GPIO57 +3V_S5
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
1K/F_4
*100_4
1K_4
MFG-TEST
THRMTRIP#
P5
EC_A20GATE 27
R325
*0_4
EC_PECI 4,27
EC_RCIN#
EC_RCIN#
27
AY11
TP36
H_PWRGOOD 4
AY10 PCH_THRMTRIP# R323
390_4
PM_THRMTRIP# 4
INIT3_3V#
T14
DF_TVS
AY1
TS_VSS1
AH8
TS_VSS2
AK11
TS_VSS3
AH10
TS_VSS4
AK10
NC_1
P37
VSS_NCTF_15
BG2
VSS_NCTF_16
BG48
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
VSS_NCTF_19
BJ4
VSS_NCTF_20
BJ44
VSS_NCTF_21
BJ45
VSS_NCTF_22
BJ46
VSS_NCTF_23
BJ5
VSS_NCTF_6
VSS_NCTF_24
B3
VSS_NCTF_7
BD49
EC_A20GATE
AU16
BJ6
BE1
+3V_S5
+3V
VSS_NCTF_25
C2
VSS_NCTF_8
VSS_NCTF_26
C48
VSS_NCTF_9
VSS_NCTF_27
D1
VSS_NCTF_10
VSS_NCTF_28
D49
VSS_NCTF_11
VSS_NCTF_29
E1
ht
R135
R118
PROCPWRGD
P4
A6
BD1
+3V
S_GPIO
+3V
+3V
V3
B47
SGPIO
RCIN#
+3V
FDI_OVRVLTG
10K_4
*0_4
Intel ME Crypto Transport Layer

Security (TLS) cipher suite
+3V_S5
K4
High = Strong (Default)
R356
GPIO24 / MEM_LED
STP_PCI# / GPIO34
SV_SET_UP
PCH_GPIO15
+3V
+3V
K1
BOARD_ID2
R136
R120
PECI
SCLOCK / GPIO22
dGPU_VRON
10,26 SML1ALERT#
TEST_SET_UP
TACH0 / GPIO17
A20GATE
+3V
STP_PCI#
TEST_SET_UP
SATA4GP / GPIO16
TP40
Need Check
C
E16
PLL_ODVR_EN
9 PLL_ODVR_EN
+3V_S5
+3V_S5
LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15
DF_TVS 9
/x
C4
U2
su
SMIB#
SKU_ID0
+3V
+3V_S5
yc
check VR_ON GPIO
GPIO8
1.5K/F_4
om
p.
C10
+3V
CPU/MISC
TP111
BMBUSY# / GPIO0
GPIO
EC_EXT_SCI#
TACH4 / GPIO68
A42
NCTF
27
DGPU_PRSNT#
+3V
EC_EXT_SMI#
:/
/m
EC_EXT_SMI#
tp
27
T7
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
DGPU_PRSNT#
(GPIO68)
UMA Only
SKU_ID1
(GPIO64)
SKU_ID0
(GPIO16)
VGA H/W
Signal
UMA
Setup
Menu
Hidden UMA boot
+3V
R281
R282
DGPU_PRSNT#
IV@10K_4
*EV@100K_4
R37
R36
*EV@10K_4
IV@10K_4
R345
R332
*10K_4
IV@10K_4
+3V
GPIO Pull-up/Pull-down(CLG)
SKU_ID1
10
B
+3V_S5
CR_WAKER#
SMIB#
PLL_ODVR_EN
R108
R341
R139
10K/F_4
10K_4
*10K_4
+3V
+3V
+3V
EC_EXT_SMI#
EC_EXT_SCI#
R278
R41
10K_4
10K_4
STP_PCI#
EC_A20GATE
EC_RCIN#
CRIT_TEMP_REP#
R354
R119
R123
R147
*10K_4
10K_4
10K_4
10K_4
dGPU_PWROK
R23
*10K_4
GPIO27
R86
*10K_4
SKU_ID0
+3V
R336
10K_4
BOARD_ID0
R352
*10K_4
R45
10K_4
BOARD_ID1
R46
*10K_4
+3V_S5
CougarPoint_R1P0
Low = Disable (Default)
MFG_MODE
R349
R335
10K_4
*0_4
R353??
R339
GPIO27:
Un-multiplexed. Can be configured as wake input to allow wakes from Deep Sleep.
If not used then use 8.2-k to 10-k pull-down to GND.
High = Enable
100K_4
BOARD_ID2
R340
*10K_4
+3V
FDI_OVRVLTG
FDI TERMINATION
VOLTAGE OVERRIDE
R122
*10K/F_4
LOW - Tx, Rx terminated

to same voltage
+3V
DMI_OVRVLTG
DMI TERMINATION
VOLTAGE OVERRIDE
R128
*200K/F_4
Low = Tx, Rx terminated to

same voltage (DC Coupling Mode)
(DEFAULT)
+3V
BIOS_REC
R134
R117
10K_4
*0_4

PROJECT :ZQR
High = Disable (Default)

BIOS RECOVERY
Size
Low = Enable
Rev
1A
Cougar Point 4/6

Date:
Document Number
Sheet
1
11
of
35
12
PCH5(CLG)
Cougar Point-M (POWER)
COUGAR POINT (POWER)
+1.05V_VCCUSBCORE
+VCCA_DAC_1_2
VccADAC =1mA(8mils)
+1.05V_VTT
U13G
+3V
L22
POWER
U13J
1500ohm/3A
+VCCACLK
TP78
AD49
POWER
VCCACLK
VCCDSW3_3= 3mA
AN27
C81
1U/6.3V_4
C46
4.7U/6.3V_6
AP21
AP23
AP24
+3V
R297
+3V_VCC_EXP
*short_6
TP106
AP16
+1.05V_VCCAPLL_FDI
BG6
+1.05V_VCCDPLL_FDI
AP17
VCC3_3[6]
V33
R28
V34
VCCIO[21]
VCCDMI[1]
*short_6
C36
0.1U/10V_4
+1.1V_VCC_DMI
AT16
+VCCAFDI_VRM
AU20
+VCCAFDI_VRM
VCCCLKDMI = 80mA(8mils)
AT20
VCCIO[26]
VCCDFTERM[1]
VCC3_3[3]
VCCVRM[2]
VccAFDIPLL
VCCDFTERM[2]
VCCDFTERM[4]
VCCDMI[2]
VCCSPI
C37
*10U/6.3V_6
AG16
AG17
+VCCP_NAND
+1.8V
R361
AJ16
VCCPNAND = 190 mA(15mils)
C100
0.1U/10V_4
R344
+3V
*short_6
ht
P26
R60
AA31
R63
VCCAPLLDMI2
VCCSUS3_3[8]
DCPSUS[3]
AD31
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W33
0.1U/10V_4 +VCCRTCEXT
N16
+VCCAFDI_VRM
65mA(10mils)
8mA(8mils)
+VCCAFDI_VRM
Y49
+1.05V_VCCA_A_DPL BD47
+1.05V_VCCA_B_DPL BF47
C60
1U/6.3V_4
VCCDIFFCLKN= 55mA(10mils)
AF17
AF33
AF34
AG34
+V1.05V_SSCVCC
*0_6
C91
*1U/6.3V_4
C111
0.1U/10V_4 +VCCSST
+1.05V_VTT
R316
+V1.05M_VCCSUS
T17
V19
BJ8
C420
4.7U/6.3V_6
C423
0.1U/10V_4
C424
0.1U/10V_4
C82
0.1U/10V_4
T23
+3V_VCCPUSB
T24
R73
*short_6
V23
C75
0.1U/10V_4
V24
+3V_VCCAUBG
VCCIO[34]
+VCCAUPLL
M26
+5V_PCH_VCC5REFSUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
+3V_VCCPSUS
R78
*short_6
+1.05V_VTT
VCC5REFSUS=1mA
10/F_4
+5V_S5
RB500V-40
+3V_S5
C68
0.1U/10V_4
C94
*1U/6.3V_4
V5REF
P34
VCCSUS3_3[2]
N20
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
+5V_PCH_VCC5REF
R59
10/F_4
+5V
D1
RB500V-40
+3V
R81
*short_6
+3V_S5
C43
1U/6.3V_4
N22
P20
+3V_VCCPSUS
VCCSUS3_3 = 119mA(15mils)
P22
C92
1U/10V_4
VCC3_3[1]
AA16
VCC3_3[8]
W16
VCC3_3[4]
T34
+3V_VCCPCORE
R129
*short_6
+3V
VCCPCORE = 28mA(10mils)
+3V
C139
0.1U/10V_4
C63
0.1U/10V_4
VCC3_3[2]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCIO[13]
VCCADPLLA
VCCADPLLB
VCCIO[6]
VCCAPLLSATA
VCCVRM[1]
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCIO[2]
VCCSSC
VCCIO[4]
AJ2
+3V
C431
0.1U/10V_4
AF13
AH13
+V1.05S_SATA3
R360
AH14
C429
1U/10V_4
AK1
+V1.1LAN_VCCAPLL
TP116
VCCVRM= 114mA(15mils)
AF11
+VCCAFDI_VRM
R130
AC16
*short_6
VCCASW[22]
VCCASW[23]
+1.05V_VTT
AC17
C145
1U/6.3V_4
AD17
+1.05V_VCCEPW
DCPSUS[1]
DCPSUS[2]
+1.05V_VTT
*short_8
AF14
DCPSST
V_PROC_IO
R71
V5REF= 1mA
VCCASW[19]
+VTT_VCCPCPU
*short_4
1mA(8mils)
+3V_RTC
V16
T29
T26
VCCIO[3]
AG33
*short_6
D2
VCCSSC= 95mA(10mils)
R77
R76
T27
P24
V5REF_SUS
*short_6
+VCCDIFFCLK
+VCCDIFFCLKN
+3V_S5
P28
VCCSUS3_3[6]
VCCIO[12]
*short_6
+1.05V_VTT
VCCSUS3_3[10]
VCCIO[5]
C113
VCCSUS3_3 = 119mA(15mils)
VCCASW[2]
VCCASW[9]
AC31
VCCSUS3_3[9]
VCCASW[1]
AC27
AC29
USB
VCCIO[14]
VCCASW[8]
AD29
*short_6
C48
1U/6.3V_4
AA29
VCCIO[33]
VCCSUS3_3[7]
*short_8
C69
1U/6.3V_4
VCC3_3[5]
AC26
VCCSPI = 20mA(8mils)
tp
VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1

1.5V (Mobile)
C78
10u/6.3V_6
AA27
W31
C140
1U/6.3V_4
AJ17
V1
C86
1U/6.3V_4
+1.05V_VTT
*short_8
C432
1U/6.3V_4
+VCCAFDI_VRM
*short_6
*short_4
R127
VCCDFTERM[3]
R265
+1.05V_VTT
R44
AB36
C35
1U/6.3V_4
CougarPoint_R1P0
+1.5V
C430
1U/6.3V_4
VCCIO[25]
VCCIO[27]
C93
1U/6.3V_4
+1.05V_VTT
*short_4
:/
/m
+1.05V_VTT
AA26
+1.1V_VCC_DMI_CCI
VCCCLKDMI
FDI
*short_8
AA24
C99
1U/6.3V_4
R346
VCCVRM[3]
AA19
AA21
VCCDMI = 42mA(10mils)
VCC3_3[7]
AL24
VccASW =1.01 A(60mils)
+3V
+3V_VCCME_SPI
R312
+1.05V_VTT
+1.05V_VCCEPW
*short_1206
VCCIO[20]
VCCIO[22]
C95
*1U/6.3V_4
C80
10u/6.3V_6
VCCIO[19]
VCCIO[24]
BH29
+1.05V_VTT
VCCIO[18]
VCCIO[23]
AN33
VCCME(+1.05V) = ??A(??mils)
C363
10U/6.3V_8
VCCIO[17]
AT24
AN34
+VCCAFDI_VRM
VCCIO[16]
AP26
C388
0.1U/10V_4
+VCCAFDI_VRM
VCCIO[15]
N26
VCCIO[30]
VCCIO[32]
PCI/GPIO/LPC
AN26
C365
0.01U/25V_4
AL29
DCPSUSBYP
SATA
AN21
AP37
C364
0.01U/25V_4
+3V_VCC_GIO
HVCMOS
C97
1U/6.3V_4
VCCTX_LVDS[4]
VCCAPLLEXP
DFT / SPI
C98
1U/6.3V_4
AP36
+VCCSUS1
R66
VCCIO
AN17
C74
1U/6.3V_4
AM38
VCCTX_LVDS[3]
+VCCDPLL_CPY
*short_6
0.1uH_8
VCCIO[28]
VccIO =2.925 A(140mils)

AN16
L27
AM37
R68
+1.05V_VTT
+1.8V
BJ22
+VCC_TX_LVDS
T38
BH23
TP89
AK37
VCCTX_LVDS[2]
V12
+3V_SUS_CLKF33
*short_4
AK36
VccTX_LVDS=60mA(10mils)
VCCTX_LVDS[1]
TP39
/x
TP93
+1.05V_VTT
AN19
DMI
+1.05V_PCH_VCCDPLL_EXP
*short_6
R47
C143
0.1U/10V_4
+3V
MISC
VSSALVDS
VccALVDS=1mA(8mils)
PCH_VCCDSW
VCCIO[29]
VCCDSW3_3
VCCIO[31]
+VCCALVDS
U47
T16
VCCME = 1.01A(60mils)
T21
V21
VCCASW[21]
T19
VCCSUSHDA
P32
VCCSUSHDA= 10mA(8mils)
A22
VCCRTC
VCCRTC<1mA(8mils)
C385
1U/6.3V_4
C386
0.1U/10V_4
CougarPoint_R1P0
C393
0.1U/10V_4
+1.05V_VTT
L21
HDA
VCCALVDS
+1.05V_VTT
R85
VSSADAC
U48
+VCCPDSW
Clock and Miscellaneous
VCCADAC
*short_4
CPU
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
R132
+3V_S5
su
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
C339
10U/6.3V_8
om
p.
C45
4.7U/6.3V_6
C346
10u/6.3V_6
yc
C72
1U/6.3V_4
CRT
C79
1U/6.3V_4
LVDS
C85
1U/6.3V_4
VCC CORE
C352
0.1U/10V_4
RTC
C356
0.01U/25V_4
VccCORE =1.3 A(60mils)
+1.05V_VTT
R62
+V3.3A_1.5A_HDA_IO
C64
*1U/6.3V_4
R67
*short_4
+3V_S5
C65
0.1U/10V_4
+1.05V_VCCA_A_DPL
10UH/100mA_8
+ C338
220U/2.5V_3528
C355
1U/6.3V_4
+ C357
*220U/2.5V_3528
C354
1U/6.3V_4
+3V
L24
R251
1/F_4 L23
C349
4.7U/6.3V_6
+1.05V_VCCA_B_DPL
10UH/100mA_8
+3V_SUS_CLKF33
10UH/100mA_8
C350
1U/10V_4

PROJECT : ZQR
Size
Document Number
Date:
Rev
1A
Cougar Point 5/6

5
3
Sheet
1
12
of
35
CougarPoint_R1P0
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
13
D
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
:/
/m
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
tp
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
ht
VSS[0]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
/x
U13H
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
su
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
om
p.
IBEX PEAK-M (GND)
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
yc
PCH6(CLG)
H5
U13I

PROJECT :ZQR
Size
3
Document Number
Rev
1A
Cougar Point 6/6
CougarPoint_R1P0
Date:
Sheet
1
13
of
35
14
DDR RVS 4H
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
5 M_A_DQSP[7:0]
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
5 M_A_DQSN[7:0]
+3V
R176
+3V
5,15 DDR3_DRAMRST#
SMDDR_VREF_DQ0_M1
+SMDDR_VREF_DIMM
JDIM2B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
1
126
VREF_DQ
VREF_CA
10K_4
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
02/23 Remove 0ohm to GND
2.48A
DDR3_DRAMRST#
/x
ODT0
ODT1
11
28
46
63
136
153
170
187
M_A_ODT0
M_A_ODT1
+1.5V_SUS
SMDDR_VREF_DQ0_M1
+SMDDR_VREF_DIMM
su
116
120
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ1
M_A_DQ0
M_A_DQ3
M_A_DQ2
M_A_DQ8
M_A_DQ9
M_A_DQ15
M_A_DQ10
M_A_DQ12
M_A_DQ13
M_A_DQ11
M_A_DQ14
M_A_DQ20
M_A_DQ21
M_A_DQ19
M_A_DQ18
M_A_DQ16
M_A_DQ17
M_A_DQ22
M_A_DQ23
M_A_DQ25
M_A_DQ24
M_A_DQ27
M_A_DQ31
M_A_DQ28
M_A_DQ29
M_A_DQ26
M_A_DQ30
M_A_DQ37
M_A_DQ33
M_A_DQ34
M_A_DQ38
M_A_DQ32
M_A_DQ36
M_A_DQ35
M_A_DQ39
M_A_DQ41
M_A_DQ45
M_A_DQ47
M_A_DQ46
M_A_DQ40
M_A_DQ44
M_A_DQ42
M_A_DQ43
M_A_DQ49
M_A_DQ48
M_A_DQ54
M_A_DQ55
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ61
M_A_DQ60
M_A_DQ62
M_A_DQ63
M_A_DQ56
M_A_DQ57
M_A_DQ59
M_A_DQ58
CAD Note: All VREF traces should

om
p.
5
5
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDR3_DRAMRST#
C180
0.1u/10V_4
yc
10,15,19 SMB_RUN_CLK
10,15,19 SMB_RUN_DAT
DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
VREF DQ0 M1 Solution
+1.5V_SUS
+1.5V_SUS
DDR3-DIMM0_H=4_RVS_LTS
R173
10K/F_4
ht
R183
1K/F_4
+SMDDR_VREF_DIMM
Place these Caps near So-Dimm0.
+1.5V_SUS
DDR3-DIMM0_H=4_RVS_LTS
:/
/m
10K_4
10K_4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
tp
R186
R185
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLKP0
M_A_CLKN0
M_A_CLKP1
M_A_CLKN1
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
PC2100 DDR3 SDRAM SO-DIMM

(204P)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
M_A_DQ[63:0] 5
JDIM2A
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

(204P)
5 M_A_A[15:0]
SMDDR_VREF_DQ0_M1
R177
10K/F_4
R184
1K/F_4
C224
470P/50V_4
+
C221
4.7U/6.3V_6
C190
4.7U/6.3V_6
+3V
C203
4.7U/6.3V_6
C202
4.7U/6.3V_6
C187
4.7U/6.3V_6
C189
4.7U/6.3V_6
C188
*10U/6.3V_6
+0.75V_DDR_VTT
C240
2.2U/6.3V_6
C242
0.1u/10V_4
C235
C236
C227
1U/6.3V_4 1U/6.3V_4 1u/6.3V_4
C205
1U/10V_4
C185
1U/10V_4
C186
1U/10V_4
C204
1U/10V_4
+SMDDR_VREF_DIMM
C226
C229
1U/6.3V_4 4.7U/6.3V_6
C237
*10U/6.3V_6
C196
0.1u/10V_4
C215
2.2U/6.3V_6
C157
C178
*330U/2V_7343 4.7U/25V_8
C184
4.7U/25V_8
SMDDR_VREF_DQ0_M1
C244
0.1u/10V_4
C243
2.2U/6.3V_6
PROJECT : ZQR
Size
Document Number
Rev
1A
DDRIII SO-DIMM-0
5
3
Date:
2
Sheet
1
14
of
35
15
DDR_RVS(DDR)
M_B_ODT0
M_B_ODT1
02/23 Remove 0ohm to GND

5 M_B_DQSP[7:0]
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
5 M_B_DQSN[7:0]
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
2.48A
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
+3V
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
1
126
VREF_DQ
VREF_CA
+3V
5,14 DDR3_DRAMRST#
SMDDR_VREF_DQ0_M1
+SMDDR_VREF_DIMM
JDIM1B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
ODT0
ODT1
/x
116
120
+1.5V_SUS
su
5
5
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ6
M_B_DQ0
M_B_DQ1
M_B_DQ3
M_B_DQ2
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ10
M_B_DQ8
M_B_DQ9
M_B_DQ11
M_B_DQ15
M_B_DQ20
M_B_DQ21
M_B_DQ18
M_B_DQ22
M_B_DQ17
M_B_DQ16
M_B_DQ19
M_B_DQ23
M_B_DQ25
M_B_DQ24
M_B_DQ27
M_B_DQ26
M_B_DQ29
M_B_DQ28
M_B_DQ31
M_B_DQ30
M_B_DQ36
M_B_DQ37
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ39
M_B_DQ38
M_B_DQ44
M_B_DQ40
M_B_DQ42
M_B_DQ43
M_B_DQ45
M_B_DQ41
M_B_DQ46
M_B_DQ47
M_B_DQ49
M_B_DQ48
M_B_DQ54
M_B_DQ55
M_B_DQ52
M_B_DQ53
M_B_DQ51
M_B_DQ50
M_B_DQ61
M_B_DQ57
M_B_DQ62
M_B_DQ63
M_B_DQ60
M_B_DQ56
M_B_DQ59
M_B_DQ58
R163
10K_4
SMDDR_VREF_DQ0_M1
+SMDDR_VREF_DIMM
om
p.
10,14,19 SMB_RUN_CLK
10,14,19 SMB_RUN_DAT
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
CAD Note: All VREF traces should

yc
DIMM1_SA0
DIMM1_SA1
SMB_RUN_CLK
SMB_RUN_DAT
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
DDR3-DIMM1_H=8_RVS_MLX
:/
/m
10K_4
10K_4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
tp
+3V
R169
R172
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CS#0
M_B_CS#1
M_B_CLKP0
M_B_CLKN0
M_B_CLKP1
M_B_CLKN1
M_B_CKE0
M_B_CKE1
M_B_CAS#
M_B_RAS#
M_B_WE#
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78

(204P)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
M_B_DQ[63:0] 5
JDIM1A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

(204P)
5 M_B_A[15:0]
ht
DDR3-DIMM1_H=8_RVS_MLX
+1.5V_SUS
Place these Caps near So-Dimm1.

C253
4.7U/6.3V_6
C254
4.7U/6.3V_6
C218
4.7U/6.3V_6
C220
4.7U/6.3V_6
C222
4.7U/6.3V_6
C251
4.7U/6.3V_6
C217
*10U/6.3V_6
C219
1U/10V_4
C255
1U/10V_4
C252
1U/10V_4
C223
1U/10V_4
C256
4.7U/6.3V_6
C258
4.7U/25V_8
+3V
+0.75V_DDR_VTT
C207
2.2U/6.3V_6
C201
0.1u/10V_4
SMDDR_VREF_DQ0_M1
C193
C192
C210
C211
C191
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 4.7U/6.3V_6
C214
*10U/6.3V_6
C198
0.1u/10V_4
+SMDDR_VREF_DIMM
C197
2.2U/6.3V_6
C195
0.1u/10V_4
C200
2.2U/6.3V_6
PROJECT :ZQR
Size
Document Number
Rev
1A
DDRIII SO-DIMM-1
Date:
5
Sheet
1
15
of
35
CRT Switch
B04
CRT
C61
0_ohm Resistor place close to Joint-Point

INT_CRT_RED
INT_CRT_GRE
INT_CRT_BLU
B02 L5,L8,L10 Change PN to CX8BA470003. 05/11

INT_CRT_RED
INT_CRT_BLU
INT_CRT_DDCDAT
INT_CRT_DDCCLK
SMD1206P110TFT
BLM18BA470SN1/0.3A/47ohm_6
L8
L5
SSM22LLPT
CRTVDD5
16
D16
FB2
L9
0_6
CRT_R1
L7
0_6
CRT_G1
L6
0_6
CN11
CRT-CONN
6
1
7
2
8
3
9
4
10
5
CRT_B1
R92
R88
R74
C125
C114
C77
C121
C96
C76
C394
C403
C408
150/F_4
150/F_4
150/F_4
10p/50V_4
10p/50V_4
10p/50V_4
*22p/50V_4
*22p/50V_4
*22p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
11
CRT_11
12
DDCDAT_1
13
CRTHSYNC
14
CRTVSYNC
15
DDCCLK_1
T1
17
8 INT_CRT_DDCDAT
8 INT_CRT_DDCCLK
FB1
L10
INT_CRT_GRE
INT_CRT_VSYNC
INT_CRT_HSYNC
8 INT_CRT_VSYNC
8 INT_CRT_HSYNC
0.1u/10V_4_X7R
F2
2
+5V
8 INT_CRT_RED
8 INT_CRT_GRE
8 INT_CRT_BLU
Remove for CRT Test 05/17
C1
C2
C3
Note:this video filter is a 2-pole,low-pass filter configuration with a target design cutoff frequency of ~200MHZ
B06 Change R295,R296 to short pad. 5/17
C1: 10pF ,C2 : 22pF , C3 :10pF,

+3V
FB1:47ohm@100MHZ , FB2:47ohm@100MHZ
U15
CRTVDD5
CRT_BYP
7
8
0.1u/10V_4_X7R
C382
.22u/25V_6
+3V
VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
C104
3
4
5
VIDEO_1
VIDEO_2
VIDEO_3
DDC_IN1
DDC_IN2
/x
CRT_R1
CRT_G1
CRT_B1
0.1u/10V_4_X7R
CRT_VSYNC2
CRT_HSYNC2
16
14
*Short_4 CRTVSYNC
*Short_4 CRTHSYNC
R295
R296
INT_CRT_VSYNC
INT_CRT_HSYNC
15
13
CRTVDD5
C88
DDC_OUT1
DDC_OUT2
GND
10
11
INT_CRT_DDCCLK
INT_CRT_DDCDAT
9
12
DDCCLK_1
DDCDAT_1
R293
R308
2.7K_4
2.7K_4
C414
.1u/10V_4
CRTVDD5
C371
10p/50V_4
CRTVSYNC
C372
10p/50V_4
CRTHSYNC
C383
*10p/50V_4
DDCCLK_1
C402
*10p/50V_4
DDCDAT_1
su
CM2009-02QR
LCD Power
om
p.
VIN
C302
C4
4.7u/25V_8
C3
0_ohm Resistor place close to Joint-Point
:/
/m
INT_TXLOUTP0
INT_TXLOUTN0
INT_LVDS_EDIDCLK
INT_TXLOUTP1
INT_TXLOUTN1
INT_LVDS_EDIDDATA
INT_TXLOUTP2
INT_TXLOUTN2
C17
2200p/50V_4
2200p/50V_4
C12
*1u/6.3V_4
+3V
EMI
INT_LVDS_DIGON
INT_LVDS_BLON
C10
*1u/6.3V_4
LCDVCC
INT_TXLCLKOUTP
INT_TXLCLKOUTN
INT_TXLOUTP0
INT_TXLOUTN0
INT_TXLOUTP1
INT_TXLOUTN1
INT_TXLOUTP2
INT_TXLOUTN2
8 INT_TXLCLKOUTP
8 INT_TXLCLKOUTN
8 INT_TXLOUTP0
8 INT_TXLOUTN0
8 INT_TXLOUTP1
8 INT_TXLOUTN1
8 INT_TXLOUTP2
8 INT_TXLOUTN2
R7
*1u/6.3V_4
CCD_PWR
C11
*1u/6.3V_4
USBP8-_R
USBP8+_R
R4
+3V
*SHORT0603
0.8A
VIN
*SHORT0805
R2
*SHORT0805
INVCC0
G_5
GND
ON/OFF
GND
*0_4
R9
0_4
2
C8
C6
C7
C9
*.1u/10V_4
*2.2u/10V_8
0.1u/10V_4_X7R.01u/25V_4
C5
5
22u/6.3V_8
AAT4280-4
R1
100K_4
G_4
Backlight Control
+3VPCU
R233
*100K_4
LID591#
27
G_1
LID591#,EC intrnal PU
+3V
D11
BAS316
R232
R234
10K_4
BL_ON
10K_4
Change 0 R5,R6 to short pad, remove CMC L1. 5/19
R8
LCDVCC
LVDS_BRIGHT
BL#
+3VPCU
USBP8+_R
USBP8-_R
USBP8+
USBP8R5
0.1u/10V_4_X7R
EC_FPBACK#
27
2
R235
100K_4
EMI
2
Q14
DTC144EUA
Q16
2N7002K
C300
INT_LVDS_BLON
*Short_4
2
Q15
2N7002K
1
10
10
*Short_4
R6
CONTRAST
8 INT_LVDS_BRIGHT
R3
OUT
IN
LVDS_CONN
B43
27
CCD +3V-current budget 0.2A
CCD-USB
*SHORT0603
INT_LVDS_DIGON
IN
8 INT_LVDS_DIGON
8 INT_LVDS_BLON
C14
tp
C18
ht
8 INT_LVDS_EDIDDATA
8 INT_LVDS_EDIDCLK
R11
BLM15AG121SS1/0.5A/120ohm_4
INT_TXLCLKOUTP
INT_TXLCLKOUTN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1U/6.3V_4
G_0
yc
INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK
U1
C1
1000p/50V_4
CN8
LVDS_BRIGHT
BL_ON
+3V
C15
0.1u/10V_4_X7R
1000p/50V_4
LVDS
+3V
LID591#
HE1
PT3661-BB
EM-6781-T3 : AL006781000
D10
*VPORT_6
PROJECT : ZQR
AH9249NTR-G1 :AL009249000
Size
Document Number
4
Rev
1A
CRT/LVDS/CAMERA/LID
Lid Switch (Hall sensor)
Date:
7
16
Sheet
8
of
35
TXC_HDMI-
17
TXC_HDMI+
TX0_HDMI-
INT-HDMI
TX0_HDMI+
PLACE AC CAP
CLOSE TO CONNECTOR
TX1_HDMI8 INT_HDMI_TXCN
TX1_HDMI+
D
8 INT_HDMI_TXCP
TX2_HDMI-
8 INT_HDMI_TXDN0
8 INT_HDMI_TXDP0
680/F_4
680/F_4
680/F_4
680/F_4
680/F_4
680/F_4
+3V
680/F_4
680/F_4
TX2_HDMI+
8 INT_HDMI_TXDN1
8 INT_HDMI_TXDP1
R372
R377
R368
R371
R378
R379
Q22
1
2N7002K
R380
R382
8 INT_HDMI_TXDN2
8 INT_HDMI_TXDP2
INT_HDMI_TXCN
C230
IV@0.1U/10V_4
INT_HDMI_TXCP
C231
IV@0.1U/10V_4
TXC_HDMI+
INT_HDMI_TXDN0
C225
IV@0.1U/10V_4
TX0_HDMI-
INT_HDMI_TXDP0
C228
IV@0.1U/10V_4
TX0_HDMI+
INT_HDMI_TXDN1
C233
IV@0.1U/10V_4
TX1_HDMI-
INT_HDMI_TXDP1
C234
IV@0.1U/10V_4
TX1_HDMI+
INT_HDMI_TXDN2
C239
IV@0.1U/10V_4
TX2_HDMI-
INT_HDMI_TXDP2
C241
IV@0.1U/10V_4
TX2_HDMI+
INT_HDMI_SCL
8 INT_HDMI_SCL
/x
R381
R376
+3V
IV@2.2K_4
IV@2.2K_4
su
s
/s
^W
INT_HDMI_SDA
8 INT_HDMI_SDA
PLACE PULL DOWN RESISTORS CLOSE TO

DIFFERENTIAL PAIRS CONNECTED TO SOLID
GROUND FLOOD WHICH IS CONTROLLED
BY THE FET
AVOID STUBS TO ALL DIFFERENTIAL TRACES
TXC_HDMI-
om
p.
+5V
F1
FUSE1A6V_POLY
HDMI CONN
yc
+3V
D20
+5V_HDMIC_R 1
RB501V-40
+5V
2.2K_4
*BAV99W
R370
33_4
HDMI_SCLK
3
2
D21
C451
*22P/50V/NPO
R374
2
RB501V-40
*BAV99W
INT_HDMI_SDA
R375
33_4
HDMI_SDATA
EMI
3
2
R366
10K_4
HDMI_SCLK
HDMI_SDATA
Q18
2N7002K
+5V_HDMIC
2
TX2_HDMI+
R182
D22
C452
*22P/50V/NPO
TX0_HDMITXC_HDMI+
TXC_HDMI-
+5V
2.2K_4
Q21
BSN20
TX1_HDMITX0_HDMI+
+5V_HDMIC
ht
+5V_HDMIC_D
+3V
8 INT_HDMI_HPD
D23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TX2_HDMITX1_HDMI+
R367
10K_4
tp
+3V
TX2_HDMI+
+3V
*100/F_4
1
CN15
C212
0.1U/10V_4
INT_HDMI_SCL
C209
1u/16V_6
Q20
BSN20
:/
/m
R369
+5V_HDMIC
+5V_HDMIC
TX2_HDMI-
Q19
2N7002K
R365
20K_4
SHELL1
D2+
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0GND
CK+
CK Shield GND
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL2
20
23
22
21
HDMI
TX1_HDMI+
R181
*100/F_4
TX1_HDMITX0_HDMI+
HDMI_HPD_EC#
HDMI_HPD_EC#
R179
27
*100/F_4
TX0_HDMI-
TXC_HDMI+
R180
*100/F_4
PROJECT : ZQR
TXC_HDMI-
Size
Document Number
Rev
1A
HDMI
5
3
Date:
2
Sheet
1
17
of
35
LAN (LAN)
<BOM note>
If center tap power come from internal switch
regulator
=>Stuff 52SWR@ (Default)
If center tap power come from internal LDO
=>Stuff 52LDO@
* Why does Pin17 CLKREQn connect to Pin16(LED2) and Pin30(DVDDL)?

<Layout note>
Close to Pin2
76.1mA ; 30mil
+3V_S5
+3V_LAN
TP109
8,19 PCIE_WAKE#
C415
10U/10V_8
20mil
VDDCT
C425
0.1U/16V_4
5
6
20mil
AVDDL
C137
0.1U/16V_4
VDDCT
C141
1U/10V_4
C427
0.1U/16V_4
XTLO_LAN
AVDDH
XTLI_LAN
1
2
C147
1U/10V_4
C146
0.1U/16V_4
Y3
25MHz-LAN
33P/50V_4
TX0N
C172 6.8PF/50V_4
TX1P
C173 6.8PF/50V_4
TX1N
C176 6.8PF/50V_4
<Layout note>
Close to LAN Chip
1nF reserved for EMI
RN2
49.9/F_4P2R
3
1
RN1
49.9/F_4P2R
8
7
6
5
UCLAMP2512T.TCT
1
2
3
4
1
2
3
4
8
7
6
5
C433
*1000P/50V_4
C435
0.1U/16V_4
UCLAMP2512T.TCT
TRANSFORMER (LAN)
TRXP1
15
TRXN1
C436
*1000P/50V_4
B27 L11 change from 0 to short pad. 5/18

C174
0.1U/16V_4
C177
C162
*1000P/50V_4
0.1U/16V_4
C169
*1000P/50V_4
AVDD_CEN
*Short_6
C158
*1U/6.3V_4
TX0N
TX0P
8
7
6
5
4
3
2
1
TDTD+
CT
NC
NC
CT
RDRD+
C183
C179
C167
C163
TXTX+
CT
NC
NC
CT
RXRX+
9
10
11
12
13
14
15
16
RX_N
LED[2]
AR8158-BL1A-RL
VDD33
24/27
AVDDL
ATHEROS
AR8158
DVDDL_REG
LED[0]
31
GND1
33
AVDDL_REG
AVDDH_REG
10
DVDDL_REG
30
VDDCT_REG
LX
VDDCT
LED[1]
32
R149
C152
X-TX1N
X-TX1P
TERM0
PCIE_TX1+ 10
DVDDL
LAN_ACTLED
C130
*0.1U/16V_4
LAN_LINKLED#
R165
75/F_8
C131
0.1U/16V_4
+1.1V regulator output (For all the analog 1.1V supply pins)
+2.7V regulator output
+1.1V regulator output (For all the digital 1.1V supply pins)
+1.8V regulator output (For VDDCT when LDO mode)
+1.7V Switching regulator (For VDDCT when switching mode)
LAN_ACTLED
5.1K/J_8
*0.1U/50V_8
R150
510/J_6
LAN_ACTLED
Del short pad R133,R168, connect to GND.

CN13
9
N27354430
10
X-TX0P
X-TX0N
X-TX1P
TERM9
*0.1U/50V_8
R170
510/J_6
R171
*SHORT0805
11
12
LAN_LINKLED#
LINK LED Pin:

SWR mode=>active low
LDO mode=>active high
D3: CY003100Z06 (2nd ) / CY231T20Z00 ( 1st & non prefer )

U17,U18: BC02512TZ00 (2nd ) / BC02512TZ00 ( 1st )
1
2
3
4
5
6
7
8
*5.1K/J_8
LAN_LINKLED#
C194
75/F_8
20mil
C129
1U/10V_4
X-TX1N
TERM9
TERM1
X-TX0N
X-TX0P
R159
C132
0.1U/16V_4
PCIE_TX1- 10
Active LED Pin:

Non-overclocking=>active high
R154
C135
0.1U/16V_4
CLK_PCIE_LANP 10
NS0014 LF_Bothhand
+3V_S5
YELLOW_N
YELLOW_P
0+
01+
2+
213+
3-
GND2
GND1
14
13
GREEN_N
GREEN_P
RJ45
TERM9
R164
1M_8
D3
B88069X9231T203
C447
220P/3KV_1808
AVDDL
29
30
PCIE_RX1+ 10
CLK_PCIE_LANN 10
B53
*6.8PF/50V_4
*6.8PF/50V_4
*6.8PF/50V_4
*6.8PF/50V_4
ht
U19
L11
TRXN0
PCIE_RX1- 10
RJ45 Connector (LAN)
tp
EMI
X-TX1N
X-TX1P
X-TX0N
X-TX0P
VDDCT
28
TX1N
+1.7V analog power
CX8EG601000: 0.5A/600ohm_6
RX_P
14
+3V_S5
+1.1V analog power
TX1N
TX1P
AVDDL
1/7 swap the pin define for layout
8
7
6
5
.1U/10V_4
26
TX1P
:/
/m
1
2
3
4
C434
0.1U/16V_4
U18
TX1N
TX1P
TX0N
TX0P
8
7
6
5
.1U/10V_4
C136
27
yc
U17
1
2
3
4
C138
PCIE_RXP1_LAN
REFCLK_P
13
1/7 change solution for surge
X-TX1N
X-TX1P
X-TX0N
X-TX0P
PCIE_RXN1_LAN
23
AVDDH_REG
TX0N
4
2
4
2
21
22
25
TRXP0
TP112
TP46
REFCLK_N
RBIAS
only
20
XTLI
12
SMBUS for debug
om
p.
C170 6.8PF/50V_4
TP47
24
TX0P
16
TX0P
TX_P
18
19
AVDDL
11
3
1
C428
TX_N
AVDDL_REG
XTLI_LAN
RBIAS
NC
32Pin QFN
VDDCT
XTLO
2.37K/F_4
TESTMODE
AR8158
4X4mm
VDDCT_REG
10
R343
SMDATA
WAKEn
su
33P/50V_4
PERSTn
XTLO_LAN
20mil
C426
SMCLK
PCIE_CLKREQ_LAN# 10
4,10,19,23,27 PLTRST#
Int. PU in SB
VDD33
17
LX
4.7uH/1A
DCR:0.15ohm
CLKREQn
2
TP92
LX
/x
VDDCT_REG
C419
0.1U/16V_4
40mil
LX
C134
0.1U/16V_4
C133
1U/10V_4
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
<Layout note>
Close to Pin1
L28
B47 Del short pad R114, connect to PCIE_CLKREQ_LAN# 5/20
42
41
40
39
38
37
36
35
34
C421
10U/10V_8
TP48
2.2_6
1
R318
PU in CLK Gen.
Power Sequence:
VDD33 to PERSTn >= 100ms
U3
PROJECT : ZQR
Size
Document Number
Rev
1A
LAN AR8158L
5
3
Date:
Sheet
1
18
of
35
MINI-CARD WLAN(MPC)
Check LED signal. (active high or low)

0_4
0_4
R398
R393
R199
CL_RST1#
CL_DATA1
CL_CLK1
*0_4
*0_4
*0_4
CL_RST1#_WLAN
CL_DATA1_WLAN
CL_CLK1_WLAN
+WL_VDD
10
10
PCIE_TX6+
PCIE_TX6-
10
10
PCIE_RX6+
PCIE_RX6-
10 CLK_PCIE_WLANP
10 CLK_PCIE_WLANN
10 CLKREQ_WLAN#
PCIE_WAKE#_R
+WL_VDD
R193
*SHORT0805 +WL_VDD
LTS_AAA-PCI-046-K01
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
15
13
11
9
7
5
3
1
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
16
14
12
10
8
6
4
2
+WL_VDD
C270
10u/6.3V_8
+1.5V
C271
0.1u/10V_4
C480
*0.1u/10V_4
C248
*0.1u/10V_4
USBP10+ 10
USBP10- 10
SMB_RUN_DAT 10,14,15
SMB_RUN_CLK 10,14,15
+1.5V
+1.5V
+WL_VDD
PLTRST#
PLTRST# 4,10,18,23,27
RF_EN# 27
Debug
LFRAME# 9,27
LAD3
9,27
LAD2
9,27
LAD1
9,27
LAD0
9,27
C477
1000p/50V_4
C450
0.1u/10V_4
C462
10u/6.3V_8
+1.5V
+WL_VDD
Q12
*DTC144EUA
PCIE_WAKE#_R
1
modify 10/19
/x
su
8,18 PCIE_WAKE#
53
+WL_VDD
+3V
H=7.0mm
CN17
GND
10 CLK_PCI_LPC
R392
R197
GND
PLTRST#
10
10
10
54
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA
:/
/m
yc
om
p.
ht
tp

PROJECT : ZQR
Size
Document Number
Date:
Rev
1A
MINI PCI-E card/TV

1
Sheet
19
8
of
35
MAIN SATA HDD
EE RETURN-PATH CAPACITORS
+3V C347,C341,C55,C303,C449,C275,C453,C459 Change VIN

to 100PF
1/10for
addEMI.
for 5/19
plane
+3V
B29
C21
0.1u/25V_4_X5R
CN16
1
2
3
4
5
6
7
GND24
SATA_TXP0 9
SATA_TXN0 9
SATA_RXN0_C
SATA_RXP0_C
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C269
C266
.01u/25V_4
.01u/25V_4
C341 100p/50V_4
C2
0.1u/25V_4_X5R
C13
0.1u/25V_4_X5R
C122
2200p/50V_4
C437 100p/50V_4
A
C460 100p/50V_4
1/11 add by EMI's request
SATA_RXN0 9
SATA_RXP0 9
C55
C369
0.1u/25V_4_X5R
C446
0.1u/25V_4_X5R
C19
0.1u/25V_4_X5R
C358
0.1u/25V_4_X5R

C108 220p/50V_4
C32
0.1u/25V_4_X5R
C337 220p/50V_4
100p/50V_4
C232 100p/50V_4
+1.05V_VTT
C317
+3V
.1u/10V_4
C148
C304 100p/50V_4
2200p/50V_4
+5V_HDD
C449 100p/50V_4
+5V_S5 C489,C289 change 100PF

for EMI. 5/19
+5V_S5
B31
C367 220p/50V_4
C33
0.1u/25V_4_X5R
C279
0.1u/25V_4_X5R
C29
0.1u/25V_4_X5R
C238
0.1u/25V_4_X5R
C499 100p/50V_4
C443
0.1u/25V_4_X5R
C500 100p/50V_4
C20
0.1u/25V_4_X5R
C16
0.1u/25V_4_X5R
C275 100p/50V_4
24
*SHORT0805 +5V_HDD
R373
+5V
C448
MAIN_SATA
C489 100p/50V_4
BOT LAYER +VCC_GFX add 100pf
x 3 C499,C500,C501. 5/19
C453 100p/50V_4
C199
C216
C213
C206
C208
B34
+VCC_GFX
10u/6.3V_6
*.1u/16V_4
*.1u/16V_4
.01u/25V_4
.01u/25V_4
C280
2200p/50V_4
C441
2200p/50V_4
C455
2200p/50V_4
+VCC_CORE C47 change 100PF for EMI.

+VCC_CORE
5/19
B32
C47
yc
CN10
14
GND15
SATA_RXN1_C
SATA_RXP1_C
SATA_DP
C90
C83
R69
.01u/25V_4
.01u/25V_4
*1K_4
B35
BOT layer +1.8V Add 100pF
C502,C503. 5/19
+1.8V
C502 100p/50V_4
C503 100p/50V_4
C504 100p/50V_4
+VCCSA
C505 100p/50V_4
SATA_RXN1 9
SATA_RXP1 9
C149
220p/50V_4
C182
220p/50V_4
C160
220p/50V_4
C175
220p/50V_4
C249
220p/50V_4
C333
*1000p/50V_4
C305
*1000p/50V_4

B36
TOP layer +1.8V Add 100pF X2
C506,C507. 5/19
+1.8V
C506 100p/50V_4
C507 100p/50V_4
+5V
+5V_ODD
C250
220p/50V_4
C362
R289
*SHORT0805
C257
220p/50V_4
*100u/6.3V_3528
C445
220p/50V_4
C444
220p/50V_4

C51
C50
C38
C52
C40
.01u/25V_4
.01u/25V_4
*.1u/16V_4
*.1u/16V_4
10u/6.3V_6
DP
5V
5V
MD
GND
GND
8
9
10
11
12
13
SATA_TXP1 9
SATA_TXN1 9

1/11 add for plane B37
TOP layer +1.5V Add
100pF X2 C504,C505.
5/19 +1.5V
+1.5V_SUS mount C149,C182,C160,C175,C249,C250,C257,C445,C444
Cap for EMI. 5/19
+1.5V_SUS
B28
tp
1
2
3
4
5
6
7
ht
GND
A+
AGND
BB+
GND
:/
/m
ODD (SATA)
100p/50V_4
C501 100p/50V_4
GND14
C289 100p/50V_4
C459 100p/50V_4
+
*100u/6.3V_3528
C454 100p/50V_4
C303 100p/50V_4
/x
GND1
RXP
RXN
GND2
TXN
TXP
GND3
C347 100p/50V_4
su
23
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
B30
VIN
C496 100p/50V_4
GND23
om
p.
+5V C496,C437,C460,C232,C304,C454
change 100PF +5V
for EMI. 5/19
15
SATA_ODD_H=7.7
PROJECT : ZQR
Size
Document Number
Rev
1A
SATA-HDD/ODD
Date:
1
Sheet

4
20
of
35
Mute(ADO)
HP
22
HP-L
22
HP-R
+3V
+5VA
B48
Del short pad R206, connect to MIC1-VREFO-L. 5/20
reverse R441
R204
*0_4
ADOGND
MIC1-VREFO-L
MIC1-VREFO-L 22
MIC1-VREFO-R
D
ADOGND
R218
R205
*10K_4
10K_4
PD#
R203
*BAS316
D7
BAS316
D6
C487
AMP_MUTE# 27
MIC1-VREFO-L
*0_4
BAS316
Codec(ADO)
EAPD#
MIC1-VREFO-R 22
MIC2-VREFO
10u/6.3V_6
C285
D8
ACZ_RST#
ADOGND
Place next to pin 27

+
2.2u/6.3V_6
C288
ADOGND
C286
C284
+5VA
2.2u/6.3V_6 0.1u/10V_4
+5VA
25
26
ADOGND
MIC1-L
22
MIC
20
JDREF
19
Sense-B
18
R200
20K/F_4
ADOGND
1u/16V_6
R198
1K_4
C273
1u/16V_6
R196
1K_4
46
PVDD2
LINE2-R
15
47
SPDIFO2/EAPD
LINE2-L
14
Sense A
13
SENSEA
R194
R195
ANALOG
ALC271X-VB3-GR
1.6Vrms
BEEP_2
C261
0.1u/10V_4
C265
1u/16V_6 BEEP_1
B03
Change netname to BEEP_2
C263
10u/6.3V_6
MIC1_JD
:/
/m
EMI
ACZ_SYNC
47K/F_4
D5
BAS316
D4
BAS316
+5VA
GND
SHDN
OUT
SET
ht
IN
R406
*29.4K/F_4
*G923-330T1UF
R405
*10K/F_4
C490
C493
27
*SHORT0603
C260
C259
0.1u/10V_4
10u/6.3V_6
+3V
Place next to pin 9
R404
R402
R408
R208
C479
C464
INT MIC array

CN7
*Short_4
1
2
*Short_4
*Short_4
*Short_4
*0_4
*1000p/50V_4
*1000p/50V_4
R226
MIC2_INTL1
1
2
C301
INT_MIC
MIC2-VREFO
2.2K_4
*22P_4
A
ADOGND
*10u/10V_3216 *0.1u/10V_4
ADOGND
R222
PCBEEP
*100p/50V_4
C492
C491
+
*0.1u/10V_4
C278 .1U_4
*0_4
Tied at one point only under

the codec or near the codec
*10u/10V_3216
ADOGND
PROJECT : ZQR
ADOGND
Size
ADOGND
cap place close to MIC-connector
C730, C787 close U37 pin3 and L65

5
ACZ_RST# 9
B06 Change R395,R402,R404,R408 to short pad. 5/17

R395
U22
3
*4.7u/10V_6
*22p/50V_4
tp
C245
Power (ADO)
ANALOG
UPB201209T-310Y-N/6A/31ohm_8
C488
ACZ_BITCLK 9
0V : Power down Class D SPK amplifer

3.3V : Power up Class D SPK amplifer
L29
SPKR
R387
B52 Del short pad R386, del netname ACZ_SDIN0_R, connect to ACZ_SDIN0. 5/20
ACZ_SDOUT 9
DIGITAL
HP_MUTE# 22
TC7SH08FU
C247
ACZ_SDIN0 9
+5V
Del short pad R403, connect to HP_MUTE#. 5/20
22
yc
0_4
PD#
B51
HPOUT_JD 22
R187
4.7K_4
R189
Place next to pin 1
MIC1_JD
39.2K/F_4
R188
C246
100p/50V_4
PCBEEP dont coupling any signals if possible

8/17 separate PCBEEP to Digital from Realtek suggestion
DIGITAL
+3V
20K/F_4
U21
4
EAPD#
MIC2_INTL1
om
p.
12
11
10
DVSS2
Spilt by DGND
PGND
SPDIFO
49
0.1u/10V_4
PCBEEP
C276
MIC2_INT_L
RESET#
MIC2_INT_R
16
SYNC
17
MIC2-L
DVDD-IO
MIC2-R
SPK-R+
SDATA-IN
SPK-R-
45
BIT-CLK
44
R_SPK+
SDATA-OUT
R_SPK-
R_SPK+
PD#
R_SPK-
22
AMP_MUTE#
22
MIC1-R
/x
27
VREF
AVSS1
LDO-CAP
30
28
29
MIC2-VREFO
32
33
35
31
MIC1-VREFO-R
MIC1-VREFO-L
AVDD1
MIC1-L
21
PVSS2
48
10u/6.3V_6
27
MIC1-R
22
PVSS1
C470
10u/6.3V_6
MONO-OUT
(Vista Premium Version)
T2
43
10u/6.3V_6 0.1u/10V_4
SPK-L-
T3
42
C466
MIC1-L
C463
SPK-L+
24
23
22
EAPD#
C461
C287
0.1u/10V_4
su
41
*SHORT0603 +5VPVDD2
R389
+5V
L_SPK-
L_SPK-
10u/6.3V_6
22
0.1u/10V_4
LINE1-L
MIC1-R
GPIO1/DMIC-CLK
10u/6.3V_6 0.1u/10V_4
L_SPK+
40
C474
22
L_SPK+
C475
C283
+5V_S5
LINE1-R
PVDD1
C467
39
AVDD2
GPIO0/DMIC-DATA
C468
+5VPVDD1
*SHORT0603
AVSS2
DVDD1
R391
+5V
38
HP-OUT-L
37
Spilt by AGND
HP-OUT-R
ADOGND
ANALOG
CBN
ADOGND
CBP
U9
CPVEE
36
C281
0.1u/10V_4
C282
10u/6.3V_6
34
2.2u/6.3V_6
Rev
1A
REALTEK ALC663&888/MDC
Date:
Document Number
Sheet
1
21
of
35
MIC
21 MIC1-VREFO-R
Internal Speaker
B27 R96,R97,R98,R99 change from 0 to short pad. 5/18
21 MIC1-VREFO-L
Normal OPEN Jack

R215
4.7K/F_4
R214
4.7K/F_4
CN20
21
21
MIC1-L
C291
4.7u/6.3V_6
MIC1_L2
R209
1K/F_4
MIC1_L3
MIC1-R
C290
4.7u/6.3V_6
MIC1_R2
R207
1K/F_4
MIC1_R3
21
L17
L16
BLACK
1
2
6
3
4
MIC1_L
MIC1_R
MIC1_JD
CN4
1/7 swap
21
21
21
21
L_SPK+
L_SPKR_SPKR_SPK+
L_SPK+
L_SPKR_SPKR_SPK+
R99
R98
R97
R96
L_SPK+_1
L_SPK-_1
R_SPK-_1
R_SPK+_1
*Short_6
*Short_6
*Short_6
*Short_6
1
25
36
4
MIC1_JD
5
MIC
C297
470p/50V_4
Max. 100mVrms input for Mic-IN
C119
C120
C118
C117
*0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6
C296
470p/50V_4
MIC1_JD
SPEAKER-CONN
ADOGND
ADOGND
D24
/x
*VPORT_6
ADOGND
HP/SPDIF
HP_MUTE#
om
p.
21
su
B42 Change R216,R221 from 56 to 47 for ACER SPEC.
21
HP-L
HP-L-2 R216
HP-R-2 R221
1
47/F_4
47/F_4
L18
L19
HP-L-2
Q24
FDV301N
R220
R217
*1K_4
*1K_4
*0_6
BLACK
1 CN21
2
6
3
4
HPL_SYS
HPR_SYS
C298
C299
21
8
5
JA6331-0230T3B-8H
HPOUT_JD
2200p/50V_4 2200p/50V_4
yc
R213
HPL-1
HPR-1
ADOGND
ADOGND
:/
/m
HP_MUTE#
B
21
HP-R
HP-R-2
Q23
FDV301N
*0_6
ht
tp
R212
HPOUT_JD
D9
2
*VPORT_6
ADOGND
PROJECT : ZQR
Size
Document Number
Rev
1A
AMP /AUDIO JACK CONN

Date:
5
Sheet
1
22
of
35
2 IN 1 CARD READER (SD/MMC)
CN6
SD_DAT1
SD_DAT0
10
9
8
7
6
5
3
2
1
SD_CLK
VCC_XD
SD_CMD
SD_DAT3
SD_DAT2
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
DATA3
DATA2
U20
C483 *0.47u/10V_6
B50 Del short pad R401, connect to PLTRST#. 5/20
R394
*SHORT0603
+3V
C484
4.7u/10V_6
R399
330_4
+3V_VDD
10
10
USBP12+
USBP12C482
C481
*5p/50V_4
*5p/50V_4
XI
XO
+1.8V_VDD
1
2
3
4
5
6
7
8
9
10
11
12
LED
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
V18
C478
4.7u/10V_6
/x
CTRL0, CRTL 1 trace length shorter ,

and surround with GND.
The trace length difference for each card interfaces should be
smaller than 500 mil
18p/50V_4
VCC_XD
XI
C1_IOP
Y4
12MHz
C485
18p/50V_4
R396
270K_4
XO
+3V
+3V
tp
C486
pin13 output 20mils
ht
crystal trace width needs at least 10 mils.
C1_VDDHM
DATA6
CTRL0
DATA5
CTRL2
DATA4
DATA3
DATA2
XDWPN
XDCEN
EEPDATA
EEPCLK
36
35
34
33
32
31
30
29
28
27
26
25
C465 4.7u/10V_6
R192
33_4
SD_DAT0
C1_IOP
DATA1
R191
33_4
SD_DAT1
DATA2
R383
33_4
SD_DAT2
DATA3
R384
33_4
SD_DAT3
CTRL0
CTRL2
DATA3
DATA2
XD_WP#
XD_CE#
EEPDATA
EEPCLK
T5
T7
T6
T8
Close to connector
2
CLK length should be as short as possible. Shorter than

1200 mil is good.
*0_4
XD_CD#
R388
T9
C456 0.1u/16V_4
SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able
CTRL0
R385
33_4
CTRL1
+1.8V_VDD
C471 2.2u/6.3V_6
DATA0
C458 *4.7u/10V_6
C457 0.1u/16V_4
13
14
15
16
17
18
19
20
21
22
23
24
AU6435-GDL
om
p.
+3V
0.1u/16V_4
Close to CN14 pin 14 & pin23

4.7u CAP close to pin23
yc
*100K_4
:/
/m
R400
4,10,18,19,27 PLTRST#
XTALSEL
HID
NBMD
CTRL1
CTRL3
DATA1
DATA0
*0_4
48
47
46
45
44
43
42
41
40
39
38
37
R397
EXT48MHZ
0.1u/16V_4
VDDHM
GND
VDD
XTALSEL
HID
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
C1_VSSHM
10
0.1u/16V_4
C1_V33
C1_IOP
AVDD5V
AGND5V
V33
VDDHM
VSSA_SYN
GND
VDD
CTRL4
XDCDN
SDWPEN
C476
C268
su
T10
C472
C262
4.7u/10V_6
C708 close PIN48, 47
+3V
VCC_XD
*Short_4 XTALSEL
PIN43=Power saving mode enable.

'1' for enable [Default]
'0' for disable
C743 close PIN46, 47
+1.8V_VDD
R390
13
SD-CARD
PIN45=Clock input selection

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input
11
12
DFHS11FR033
SD_CD#
GND1
Second
SD_WP
14
DFHS11FR011
Main
CD/SW
CARD READER Controller

AU6435-GDL
WP/SW
SW COM
GND
SD_CLK
SD_WP
C264
*10p/50V_4
+3V
C469
CTRL2
0.1u/16V_4
1/12 add by FAE's request

CTRL3
R190
33_4
SD_CMD
SD_CD#
352-(&7=4
4XDQWD&RPSXWHU,QF
Size
C
Document Number
Rev
1A
AU6433 CardReader
Date:
D
Sheet
E
23
of
43
LED
+3V_S5
POWER
100/F_4
LED1
R229
PWRLED#
Bule
/x
27
Amber
*1M_4
R228
*1M_4
Battery
27
BATLED1#
+3VPCU
Amber
LED_B/R
R223
300/F_4
R227
100/F_4
LED2
Blue
:/
/m
yc
27
BATLED0#
+3VPCU
om
p.
R224
su
Blue
ht
tp

PROJECT : ZQR
Size
Document Number
Rev
1A
POWER/MMB/LAUNCH/LED
Date:
5
Sheet
24
1
of
35
USB
BLUETOOTH CONNECTOR for 3.0
+5V_S5
C267
CN19
U8
2
3
27
4
1
USBON#
IN1
IN2
OUT3
OUT2
OUT1
8
7
6
OC#
EN#
GND
+3V_S5
USBPWR1
BT_POWER
C277
C495
0.33u/10V_6
R407
47K_4
1000p/50V_4
+ C497
2.2u/6.3V_6
AO3413
5
4
3
2
1
USBP4+_R
USBP4-_R
Q25
C473
+
1U/6.3V_4
C498
1000p/50V_4
BT_LED
T11
27
R230
BT_ON#
10
10
CN18
1
2
3
4
USBP1-_R
USBP1+_R
B38 USB C.M Chock L14 Phase into BOM list, cancel 0 R201,R202. 5/19
1
2
3
4
8
7
6
5
BlueTooth
8
7
6
5
USBP4+_R
USBP4-_R
USBP4+
USBP4R225
B43
USB_MB_Turbo
MB/B-USB1-1
L14
USBP1-_R
USBP1+_R
Reserve
RV2
RV1
*EGA-0402
*EGA-0402
DLW21HN900SQ2L/300mA/90ohm
2
*Short_4
1
4
/x
1
4
2
3
2
3
C494
.01u/16V_4
*Short_4
10 USB_OC0#
USBP1USBP1+
330u/6.3V_6X5.7
G547F2P81U
10
10
7
6
BT_CONN
+3V_S5
CN5
BT_POWER
B44 Change CMC L14 PN from "DC09004A014" to "CX1HN900000". 5/19
BT_ON#
om
p.
27
R219
*47K_4
su
C292
*0.33u/10V_6
yc
C293
*1000p/50V_4
BT_LED
T4
7
6
*BT_CONN
R210
10
10
BlueTooth
C294
*.01u/16V_4
*Short_4
USBP5+_R
USBP5-_R
USBP5+
USBP5R211
B43
*Short_4
+5V_S5
B07 remove R178 short pad. 5/17
:/
/m
USB/B
*AO3413
+ C295
*2.2u/6.3V_6
5
4
3
2
1
USBP5+_R
USBP5-_R
Q13
tp
USB_DB FFC CONN
ht
B38 USB C.M Chock L12,L13 Phase into BOM list, cancel 0 R166,R167,R174,R175. 5/19
B44 Change CMC L12,L13 PN from "DC09004A014" to "CX1HN900000". 5/19
L13
EXT/B-USB1-1
10
10
USBP3+
USBP3-
2
3
2
3
1
4
10
USB_OC1_5#
USBP3+_R
USBP3-_R
1
4
USBP3-_R
USBP3+_R
USBP9-_R
USBP9+_R
EXT/B-USB1-2
L12
10
10
USBP9+
USBP9-
2
3
2
3
1
4
USBP9+_R
USBP9-_R
1
4
27
USBON#
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
17
1
18
CN14

PROJECT : ZQR
Size
Document Number
Rev
1A
USB/ BT
Date:
5
Sheet
1
25
of
35
CPU FAN
CN2
220p/50V_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MX4
MX5
MX6
MX7
RP1
10
9
8
7
6
G995P1U
C307
C306
C23
2.2U_6
.01U_4
*.01U_4
1
2
3
FAN_CONN
27
28
27
TPDATA
27
TPCLK
+5V
L4
+TPVDD
*SHORT0603
C28
R13
10K_4
R14
10K_4
0.1u/10V_4_X7R
CN1
L2
1
2
3
4
5
6
7
8
9
10
11
12
*SHORT0603
L3
TPDATA_R
TPCLK_R
*SHORT0603
C25
yc
:/
/m
1
HOLE8
*h-c236i185d165p2
C26
RIGHT#
*.01u/25V_4
*.01u/25V_4
LEFT#
13
14
Aces 88501-120N
HOLE9
*h-c236i185d165p2
RIGHT#
tp
Holex1 @ mini card
SW2
3
1
LEFT#
2
4
SWITCH_1.5
SW1
3
1
2
4
SWITCH_1.5
Holex2 @PCH
HOLE18
H-C197D87P2
CN9
30mil
TH_FAN_POWER
ht
1
2
3
1
2
3
1
2
3
HOLE5
*h-c236i185d165p2
FANSIG
FANPWR = 1.6*VSET
HOLE15
*H-O95X134D95X134N
1
2
3
1
2
3
1
2
3
1
2
3
HOLE16
H-C228D142P2
HOLE17
H-C228D142P2

1
1
2
3
HOLE3
HOLE14
HOLE7
HOLE13
HOLE4
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7
6 7
6 7
6 7
6 7
6
8
5 8
5 8
5 8
5 8
5
9
4 9
4 9
4 9
4 9
4
27 CPUFAN#_DAC
+5V
1
2
3
1
2
3
HOLE6
*hg-c315d118p2
7
6
8
5
9
4
VO
GND
/FON GND
GND
VSET GND
3
5
6
7
8
TOUCHPAD & Switch CONN.
HOLE2
*H-C94D94N
HOLE10
HOLE11
HOLE12
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7
6 7
6 7
6
8
5 8
5 8
5
9
4 9
4 9
4
VIN
10,11 SML1ALERT#
10K_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5
27
U2
2
HOLE
HOLE1
*hg-c315d110p2
7
6
8
5
9
4
10K_4
C22
2.2U_6
KB
+3VPCU
MX0
R15
+5V
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
/x
C24
5/19
su
KB Cap CP1,CP2,CP3,CP4,CP5,CP6 change to 220 PF and phase into BOM list.

B33
MX3
7
8
MX2
5
6
MX4
3
4
MX5
1
2
CP6
220PX4
MX6
7
8
MX7
5
6
MY17
3
4
MY16
1
2
CP5
220PX4
MY3
7
8
MY2
5
6
MY1
3
4
MY0
1
2
CP1
220PX4
MY7
7
8
MY6
5
6
MY5
3
4
MY4
1
2
CP2
220PX4
MY11
7
8
MY10
5
6
MY9
3
4
MY8
1
2
CP3
220PX4
MY15
7
8
MY14
5
6
MY13
3
4
MY12
1
2
CP4
220PX4
MX1
C27
220p/50V_4
om
p.
+3V
K/B
PROJECT : ZQR
Size
Document Number
Rev
1A
KB/FAN/TP+FP
Date:
5
Sheet
1
26
of
35
L26
PBY160808T-250Y-N/3A/25ohm_6
SM BUS PU(KBC)
+A3VPCU
+3V
C348
0.1u/10V_4
4.7U/6.3V_6
D12
C334
C331
MBCLK
MBDATA
R19
R18
10K_4
10K_4
4.7U/6.3V_6
0.1u/10V_4
MBCLK2
MBDATA2
R16
R17
10K_4
10K_4
+3V_S5
+3VPCU_EC
121
GPIO85/GA20
11
122
KBRST/GPIO86
29
ECSCI/GPIO54
16 EC_FPBACK#
124
21 AMP_MUTE#
4,10,18,19,23
19
9
TP65
PLTRST#
7
123
RF_EN#
125
SERIRQ
11 EC_EXT_SMI#
26
26
26
26
26
26
26
26
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
54
55
56
57
58
59
60
61
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
28
28
10
10
26
26
9
25
8 PCH_SUSCLK
4,11
+1.05V_VTT
EC_PECI
MBCLK
MBDATA
MBCLK2
MBDATA2
TP69
TP71
MBCLK
MBDATA
MBCLK2
MBDATA2
VGACLK
VGADATA
72
71
10
11
TPCLK
TPDATA
ME_WR#
BT_ON#
R20
*short_4
R243
R242
*short_4
43_4
70
69
67
68
119
120
E775_32KX1
+1.05V_VTT_EC
EC_PECR_R
77
12
13
GPIO94/DA0
GPI95/DA1
GPI96/DA2
101
105
106
GPIO01/TB2
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06/IOX_DOUT/RTS1
GPIO07
GPIO16
GPIO30
GPIO36/CTS1
GPIO41
GPIO42/SCL3B/TCK
GPIO43/SDA3B/TMS
GPIO44/TDI
GPIO
GPO47/SCL4
GPIO50/PSCLK3/TDO
GPIO51
GPIO52/PSDAT3/RDY
GPIO53/SDA4
GPIO70
GPIO71
GPIO72
GPIO75/SPI_SCK
GPO76/SHBM
GPIO77
GPIO81
GPO82/IOX_LDSH/TEST
GPO84/IOX_SCLK/XORTR
GPIO97
64
79
95
96
108
93
94
114
109
15
80
17
20
21
24
25
26
27
28
73
74
75
82
83
84
91
110
112
107
D/A
GPIO11/CLKRUN
TP68
TP9
GPIO10/LPCPD
LREST
GPIO67/PWUREQ
SERIRQ
GPIO65/SMI
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
GPIO56/TA1
KBSOUT7
GPIO20/TA2/IOX_DIN_DIO
KBSOUT8
GPIO14/TB1
KBSOUT9/SDP_VIS
TIMER
KBSOUT10/P80_CLK
GPIO15/A_PWM
KBSOUT11/P80_DAT
GPIO21/B_PWM
KBSOUT12/GPIO64
GPIO13/C_PWM
KBSOUT13/GPIO63
GPIO32/D_PWM
KBSOUT14/GPIO62
GPIO45/E_PWM
KBSOUT15/GPIO61/XOR_OUT
GPIO40/F_PWM/RI1
GPIO60/KBSOUT16
GPIO66/G_PWM
GPIO57/KBSOUT17
GPIO33/H_PWM/SOUT1
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
SMB
GPIO87/CIRRXM/SIN_CR
GPIO34/SIN1/CIRRXL
GPIO46/CIRRXM/TRST
GPO83/SOUT_CR/TRIST
IR
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
GPIO00/32KCLKIN
VTT
PECI
PWRSM_SW
MUTE_KEY
*short_4
TP4
R269
*short_4
ICMNT
CPUFAN#_DAC
VGACLK
VGADATA
DGPU_IDLE#
VGA_THERM#
26
31
117
63
32
118
62
65
22
16
81
66
ACIN
TP58
TP67
5
18
45
78
89
116
113
14
23
111
PROCHOT_EC
HWPG
ODD_POWER
R21
VRON
TP61
TP56
TP2
17
SPI FLASH(KBC)
SUSC# 8
PWROK_EC 8
ICH_RSMRST# 8
MAINON 31,32,34
*short_4
*short_4
TP64
TP62
TP63
TP66
TP7
3G_EN
ODD_EJ#
TP53
TP72
MUTE_LED
SUSLED#
CAPSLED#
R271
SUSON 32
FANSIG 26
ECDB_CLOCK
85
VCC_POR#
SO
SPI_SDO_uR
SI
SPI_SCK_uR
SCK
SPI_CS0#_uR
104
VREF_uR
C330
WP
0.1u/10V_4
VSS
At 11/24 add
Winbond W25X16AVSSIG
AKE38ZP0N01
EON
EN25F16-100HIP
AKE38ZA0Q00
AMIC
A25L016
AKE38ZN0800
BATLED1# 24
R241
22_4
SPI_SDO_uR
R245
22_4
SPI_SCK_uR
R270
HWPG(KBC)
+3V
47K/F_4
*short_4
+3VPCU
+A3VPCU
C316
*56p/4
29
SYS_HWPG
34 HWPG_1.8V
31,33 HWPG_VTT
32 HWPG_1.5V
TP97
TP95
TP91
CN3
TP86
D17
1SS355
D13
1SS355
D18
1SS355
D15
1SS355
D14
1SS355
HWPG
CN12
NBSWON#_TP
+3V_S5_TP
DNBSWON#_TP
SUSON_TP
SUSB#_TP
+3V_TP
+VCC_CORE_TP
PWROK_EC_TP
PLTRST#_TP
1
2
PWR-CONN
R274
10K_4
HWPG
93&893&8
C360
*56p/4
33 HWPG_VCCSA
R90
10K_4
CE
VDD
HOLD
W25X10BVSNIG
H_PWRGOOD_TP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
+3VPCU
S5_ON_TP
ICH_RSMRST#_TP
SUSC#_TP
+1.5V_SUS_TP
MAINON_TP
VRON_TP
HWPG_TP
SYS_PWROK_TP
SUS_STAT#_TP
TP108
TP105
TP103
TP101
TP99
S5_ON
R236
*10K_4
TP96
TP94
TP90

PROJECT : ZQR
TP85
Size
Document Number
Date:
*CON30_DEBUG
+3VPCU
C342
*56p/4
TP51
SW3
DIP:TME-533B-Q-T/R
C116
*1000P/16V/X7R_4
10K_4
TP54
TP3
TP57
R240
+3VPCU
C115
0.1U/10V/X5R_4
*10P/50V_4
PROCHOT_EC
30
1
2
R256
CONTRAST 16
PCBEEP 21
PWRLED# 24
BATLED0# 24
TP110
TP107
TP104
TP102
TP100
TP98
NBSWON#
C329
22_4 SPI_SDI_uR_R
100K_4
+3VPCU
Power sequence
2
4
5
6
*10P/50V_4
TP5
TP60
BACKUP_SW
VCC_POR
PWR/B
*10P/50V_4
C328
U11
SPI_SDI_uR R275
TP75
NUMLED#
C361
DNBSWON# 8
USBON# 25
VGA_THERM#
2N7002K
100K_4
SUSB# 8
TP55
R237
R238
PWROK_EC_uR
RSMRST#_uR
30
D/C#
28
S5_ON 29,34
HDMI_HPD_EC#
TP52
S5_ON
HDMI_HPD_EC#
GPIO55/CLKOUT/IOX_DIN_DIO
PBY160808T-250Y-N/3A/25ohm_6
LID591# 16
TP70
TP8
TP1
TP59
BACKUP_LED#
ACPRN
PWRSAVE_ LED#
SPI_SDI_uR
SPI_SDO_uR_R
SPI_CS0#_uR
SPI_SCK_uR_R
VREF
4,30
Q1
1u/6.3V_4
1
3
2.2K_4
2.2K_4
10K_4
*10K_4
28
E775AGND
NBSWON#
R254
R252
R267
R268
NBSWON#
C308
*10K_4
28
TP6
MUTE_CODEC
86
87
90
92
F_SDI/F_SDIO1
F_SDO/F_SDIO0
F_CS0
F_SCK
PS/2 FIU
ht
NPCE791L
POWER-ON Switch(KBC)
R239
3G_EN
R253
H_PROCHOT#
LPC
GPIO24/LDRQ
L25
WL_SW
DGPU_IDLE#
CPU_ICC
11 EC_A20GATE
11 EC_EXT_SCI#
TEMP_MBAT 28
EC_RCIN#
97
98
99
100
+3V
CLKRUN#
C336
*10p/50V_4
CLK_PCI_EC
0.01u/16V_4
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
A/D
4.7U/25V_8 ICMNT
C343
*22_4
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
GND1
GND2
GND3
GND4
GND5
GND6
R250
3
126
127
128
1
2
C353
yc
9,19 LFRAME#
9,19 LAD0
9,19 LAD1
9,19 LAD2
9,19 LAD3
10 CLK_PCI_EC
E775AGND
/x
U10
su
0.1u/10V_4
*.1u/16V_4
VDD
0.1u/10V_4
:/
/m
*.1u/16V_4
VCORF
0.1u/10V_4
AGND
4.7U/6.3V_6
CLK_PCI_EC
VCORF_uR 44
C340
tp
C312
103
C309
102
C311
AVCC
C320
VCC1
VCC2
VCC3
VCC4
VCC5
C322
19
46
76
88
115
BAS316
+3VPCU
E775AGND
2.2_6
2
om
p.
+3VPCU
R244
1
C345
Rev
1A
WPCE791 & FLASH

2
Sheet
1
27
of
35
VA1
PD3
SBR1045SP5-13
1
PL5
HI0805R800R-00_8
PJ2
VA
1
2
3
4
PR122 B14
0.01_0612
PQ23
AOL1413
1
2
3
VA2
PQ23PQ24 change symbol from N-MOS to P-MOS. 5/17
PC76
0.1u/50V_6
PC8
0.1u/50V_6
PL3
HI0805R800R-00_8
PR7
220K_4
1
2
3
2
B24
PR35 change from 0 to short pad. 5/18
PR35
PC95
*Short_4
0.1u/50V_6
POWER_JACK
PQ24
AOL1413
VIN
PD2
SMAJ20A
PR41
*Short_4
PC94
2200p/50V_6
PR18
33K/F_4
CSIN_1
PC79
2200p/50V_6
1
PD1
SW1010CPT
PR6
220K_4
CSIP_1
B24
PR30
*Short_4
D/C#
PR17
10K_4
27
PC78
0.1u/50V_6
B24 PR30 change from 0 to short pad. 5/18
PQ1
IMD2AT108
CSIN_1
2
PQ2
DMN601K-7
CSIP_1
VIN
PC18
1u/16V_6
PR36
10/F_4
PC22
0.1u/50V_6
PR10
4.7_6
ACOK
PC13
0.1u/50V_6
PL1
HI0805R800R-00_8
MBAT+
ACIN
VREF
BAT-V
C114F3-108A1-L_Batt_Conn
PL2
HI0805R800R-00_8
10 1
2
3
4
5
6
7
9 8
PR112
100_4
TEMP_MBAT 27
PR113
100K_4
+3VPCU
PJ1
PR111
*SHORT_PAD_4
PR2
100_4
PC2
47p/50V_6
ht
PC3
47p/50V_6
tp
TEMP_MBAT
PR1
100_4
PC23
PC24
*1u/16V_6 0.01u/50V_6
MBCLK
27
MBDATA
27
su
PHASE
23
ISL88731_PHASE
LGATE
20
ISL88731_LGATE
PU2
ISL88731C
5
4
PQ21
AON7410
PR5
0.01_0612
PL4
6.8uH_7X7X3
BAT-V
PR4
*4.7_6
19
CSOP
18 CSOP
CSON
17 CSON
PR8
10/F_4
PQ22
AON7410
CSOP_1
PC5
1000p/50V_6
PC80
2200p/50V_6
BAT-V
PC9
10u/25V_1206
PC11
10u/25V_1206
CSOP_1
PC12
0.1u/50V_6
ICOMP
NC
16
VBF
15
GND
29
BAT-V
B39 PR4 4.7ohm / PC5 1000pf phase into BOM list for EMI. 5/19
PR9
10/F_4
PR16
*SHORT0402
NC
VCOMP
PR44
2.21K/F_4
PC77
2200p/50V_6
3
2
1
VDDP
VCC
yc
PR43
22K/F_4
DCIN
:/
/m
88731ACSET
PC4
100p/50V_6
24
PGND
22
PR42
82.5K/F_4
PC1
0.1u/50V_6
2
1
UGATE
ISL88731_UGATE
PC26
0.01u/50V_6
ICMNT
GND
DCIN
NC
PR11
49.9/F_6
SCL
13
PC15
0.1u/50V_8
88731B_1
PC6
*10u/25V_1206
BAT-V
PR3
100_4
12
ACIN
14
27
SDA
PR25
2.7_6
25 88731B_2
PD4
*RB500V-40
3
2
1
9
10
ICM
MBCLK
27
PR23
100K_4
NC
MBDATA
BOOT
27
VDDSMB
om
p.
11
CSSN
NC
GND
GND
GND
GND
CSSP
PC17
0.1u/50V_6
PC7
10u/25V_1206
21
26
ISL88731_VDDP
+3VPCU
+3VPCU
EMI
PC10
1u/16V_6
/x
27 CSIN
1
33
32
31
30
28 CSIP
PR40
10/F_4
ISL88731 thermal pad

tie to Pin12
ICMNT
27
PC25
*0.01u/50V_6
PU1
*CM1293A-04SO
TEMP_MBAT
CH1
VN
CH2
CH4
VP
CH3
MBDATA
+3VPCU
MBCLK
PROJECT : ZQR
Size
Add ESD diode base on EC FAE suggestion

Date:
5
Document Number
Rev
1A
Charger(ISL88731A)
4
Sheet

1
28
of
35
MAIND
MAIND
SYS_SHDN#
6,32,34
SYS_SHDN#
4,34
Ven=7.23V
B11 Del JP10, connect to VIN. 5/17
27 SYS_HWPG
VIN
+3VPCU
VIN
VL
8223REF
+3VPCU

D
UGATE2
22
BOOT1
ENTRIP1
ENC
PR79
75K/F_4
PD6
CHN217
FB2
+15V_ALWP
PR77
*4.7_6
+3V_FB
PR82
6.81K/F_4
+
4
PC149
0.1u/50V_6
15
25
5
3
2
1
+3V_DL
PQ9
AON7702
PC65
*680p/50V_6
PC151
330u/6.3V_6X5.7
PR83
10K/F_4
PR81
75K/F_4
+5V_DL
OCP:6.2A
PR84
*SHORT_PAD_6
L(ripple current)
=(9-3.3)*3.3/(2.2u*0.5M*9)
~1.9A
Iocp=6.2-(1.9/2)=5.25A
Vth=5.25A*14mOhm=0.0735V
R(Ilim)=(73.5mV*10)/10uA
=73.5K
PR190
*SHORT_PAD_6
PC154
0.1u/50V_6
+3VPCU
PL14
2.2uH
tp
2
PD7
CHN217
ht
+15V
OUT2
PR89
+3V_DL
*SHORT_PAD_6
1
PC155
0.1u/50V_6
*0_6
:/
/m
PR90
L(ripple current)
=(9-5)*5/(2.2u*0.4M*9)
=2.525A
Iocp=6.6-(2.525/2)=5.34A
Vth=5.34A*14mOhm=0.07472mV
R(Ilim)=(74.72mV*10)/10uA
~74.723K
12
PC153
0.1u/50V_6
OCP:6.6A
+3V_LX
*Short_4
yc
Del net "+5VPCU_SRC". 5/17
PHASE2
11
PC69
0.1u/50V_6
PR87
1/F_6
PC71
0.1u/10V_4
PR103
100K/F_4
B12 Del JP11, connect to +3VPCU. 5/17
3
2
1
PR93
1
2
3
B24
PC64
*680p/50V_6
+3V_B
LGATE2
VOUT1
FB1
om
p.
/x
LGATE1
+3V_DH
BOOT2
su
19
10
GND
PHASE1
+5V_DL
PU4
RT8223M
GND
20
ENTRIP2
+5V_LX
UGATE1
8223_EN
PR80
10K/F_4
4.7u/6.3V_6
21
PC152
0.1u/50V_6
+3V_TON
+5V_DH
+5V_FB
1
2
3
PC150
330u/6.3V_6X5.7
REF
+3V_SKIP
24
PR76
*4.7_6
17
14
TONSEL
PR78
15.4K/F_4
+
VREG5
SKIPSEL
PGOOD
PC63
4.7u/25V_8
+3VPCU
3.3 Volt +/- 5%
TDC : 3.86A
PEAK : 5.15A
OCP : 6.2A
Width : 160mil
EN
+5V_B
PC62
2200p/50V_6
PQ7
AON7410
23
PQ8
AON7702
PR102
*0_4
*SHORT_PAD_4
13
PR88
1/F_6
PR105
*SHORT_PAD_4
PR91
+3V_PG
PC68
0.1u/50V_6
PR92
*0_4
SYS_SHDN#
PL13
2.2uH
VREG3
VIN
5
PQ6
AON7410
PC66
1u/6.3V_4
PR107
330K/F_4
16
PR86
*100K/F_4
PC72
PR85
*SHORT_PAD_4
8223_EN
PC70
0.1u/25V_4
+5VPCU
+5VPCU
5 Volt +/- 5%
TDC : 4.125A
PEAK : 5.5A
OCP : 6.6A
Width : 170mil
8223_VIN
PC61
2200p/50V_6
PC60
4.7u/25V_8
18
B13
Del JP12, connect to +5VPCU. 5/17
PC148
100u/25V_6X5.8
4.7u/6.3V_6
PR106
665K/F_4
PC67
PR100
10_8
VIN
VIN
PR109
22_8
PC74
0.1u/50V_6
+5VPCU
PR164
*1M_6
PR110
1M_6
PQ10
MDV1660
3
2
1
MAIND
PQ11
MDV1660
MAIND 4
PQ12
MDV1660
S5D
PQ20
AO3404
PQ36
DMN601K-7
+5V_S5
PQ37
DMN601K-7
PR167
1M_6
2
PQ39
DTC144EU
S5_ON
27,34
+3VPCU
+3VPCU
PR163
22_8
S5D
A
+5VPCU
3
2
1
PR162
22_8
VIN
PR168
1M_6
+15V
+5V_S5
3
2
1
+3V_S5
VIN
PQ38
DMN601K-7
PC75
*2.2n/50V_4
TDC : 2.25A
PEAK : 3A
Width : 100mil
+5V
TDC : 1.88A
PEAK : 2.5A
Width : 80mil
+3V
TDC : 2.74A
PEAK : 3.65A
Width : 110mil
3
+3V_S5
TDC : 0.16A
PEAK : 0.21A
Width : 10mil

PROJECT : ZQR
Size
Rev
1A
SYSTEM 5V/3V (RT8223M)

Date:
Document Number
Sheet

1
29
of
35
Close to the
CPU side.
36
+VCC_CORE
PROG2
PR21
80.6K/F_4
ht
95835_COMP
PR57
*10_4
95835_COMPG
6 VCCSENSE
PR29
*Short_4
6 VSSSENSE
PR37
*Short_4
PC98
330p/50V_4
VSS_SENSE_R
PR56
*10_4
B24 PR29, PR37 change from 0 to short pad. 5/18
PC123
4.7u/25V_8
PC40
2200p/50V_4
PC121
4.7u/25V_8
PC122
4.7u/25V_8
PC41
0.1u/50V_6
PR55
2.2_6
3
PC46
10u/6.3V_8
PC38
2200p/50V_4
1
2
3
yc
PC31
2200p/50V_4
PC29
4.7u/25V_8
PC28
4.7u/25V_8
+VCC_CORE
VSUM+
PR133
3.65K/F_6
ISEN_1
PR136
10K/F_4
VSUM-
PR28
1/F_4
PC48
0.1u/10V_4
PQ3
*AON6780
PR52
2.2_6
3
PQ27
AON6780
PC42
330u/2V_7343
VCORE Load Line :

1.9mV/A
ISEN_2
PR146
2.2/F_6
VIN
Place NTC close to the VCORE inductor of phase 1
UGATE_2
PR53
10K/F_4
PC113
0.22u/25V_6
VSUM-
VSUM+
PQ26
AON6414AL
PL9
0.36uH
PHASE_2
B55 PR139 changes from 1.33Kohm(CS21332FB11) to 1.58Kohm(CS21582FB00). 5/23
PQ29
AON6780
PQ4
*AON6780
LGATE_2
PC97
0.22u/10V_4
ISEN_1
PC91
ISEN_2
PC33
2200p/50V_4
BOOT_2
PR45
2.61K/F_4
PR156
10K_6_NTC
+VCC_GORE
TDC : 53A
PEAK : 53A
OCP : 60A
Width : 2120mil
B09 Del JP1, connect to Vin.

Del "+VIN_VCC_CORE" netname. 5/17
PC99PC103 change from 33nf(CH3334K1B00) to 0.1uf(CH4104K9B03). 5/23
1
2
3
1.58K/F_4
DCR=1.1mOhm
+
PC116
100u/25V_6X5.8
DCR=1.1mOhm
+VCC_CORE
0.22u/10V_4
ISUMP
ISUMN
PC114
100u/25V_6X5.8
PR32
*10K/F_4
Add 9 GND VIAs

for thermal pad
41
18
17
ISEN1
VR_PWM3
25
PC36
2200p/50V_4
4
LGATE_1
PC39
330u/2V_7343
VSUMVSUM+ PR129
3.65K/F_6
ISEN_3
PC101
330p/50V_4
Parallel
1
2
3
PC20
+5V_S5
VCC_SENSE_R
95835_VRON
11K/F_4
PC99
0.1u/25V_4
LGATE_2
PR51
2.2_6
3
PROG1
tp
PR38
3.83K/F_4
PHASE_2
27
10p/50V_4
PR126
2K/F_4
PR19
20K/F_4
28
PC93
PC96
PC89
560p/50V_4
PR119
887/F_4
PR139
PC86
1000p/50V_4
PR140
*100/F_4
PR127
267K/F_4
EP
B57
PC106
*330p/50V_4
ISEN2
FB
PR123
3.01K/F_4
Place NTC close to the

GFX_CORE Hot-Spot.
PWM3
COMP
ISEN3/FB2
12
VW
15
11
14
PC90
33p/50V_4
PR114
100K/F_4
LG2
UGATE_2
NTC
:/
/m
95835_FB
PR154
470K_4_NTC
PH2
29
PL8
0.36uH
PC104
4.7u/25V_8
NTCG
30
PQ28
AON6414AL
PHASE_1
B24
BOOT2
PR50
10K/F_4
PC35
2200p/50V_4
SCLK
BOOT_2
UGATE_1
PC109
4.7u/25V_8
SDA
13
95835_COMP
PR116
3.83K/F_4
PC84
680p/50V_4
LGATE_1
PC112
0.22u/25V_6
PR46
*Short_4
PR117
8.06K/F_4
PR39
27.4K/F_4
PHASE_1
24
ALERT#
RTN
PR157
470K_4_NTC
23
PC30
0.1u/50V_6
PH1
PC85
1000p/50V_4
10
Place NTC close to the

VCORE Hot-Spot.
UGATE_1
VIN
VR_HOT#
16
PR121
27.4K/F_4
22
PR144
2.2/F_6
1
2
3
UG1
UG2
BOOT_1
BOOT1
4,8 IMVP_PWRGD
35
21
1/F_4
PC32
0.1u/50V_6
6 VR_SVID_CLK
GFX_CORE Load Line :

-3.9mV/A for GT2
PC124
330u/2V_7343
+VCC_GFX
TDC : 24A
PEAK : 33A
OCP : 35.8A
Width : 1320mil

Del "+VIN_VCC_CORE" netname. 5/17
1
2
3
6 VR_SVID_DATA
LGATE_GT
0.1u/10V_4
8 GFX_PWRGD
PHASE_GT
11K/F_4
PR15
1.91K/F_4
*Short_4
PR12
10K/F_4
PR115
*100K/F_4
PR120
VRON
6 VR_SVID_ALERT#
+VCC_GFX
1.82K/F_4
PR31
1
2
3
PGOOD
LG1
PC83
43p/50V_4
DCR=1.1mOhm
BOOT_1
PU5
ISL95835HRTZ-T
8
4,27 H_PROCHOT#
32
31
ISNG
PGOODG
B01 remove PR22 from BOM for power up issue. 05/11
B24
37
LG_GT
UGATE_GT
+3V
38
40
39
PHASE_GT
VR_ON
BOOT_GT
33
PC103
.1u/25V_4
+3V_S5
PR34
1
2
3
2
7
VR_SVID_CLK
27
*0_4
VDDP
34
PR134
PR22
HG_GT
PC105
0.22u/10V_4
VR_SVID_DATA
95835_VRON
PC111
4.7u/6.3V_6
BOOT_GT
VDD
PR13
130/F_4
ISPG
1
2
3
26
PR14
54.9/F_4
PQ5
*AON6780
Close to VR
VIN
PQ32
AON6780
LGATE_GT
/x
19
ISUMPG
20
95835_VDD
RTNG
95835_VIN
PR155
10K_6_NTC
Place NTC close to the GFX_CORE inductor
ISUMNG
PC108
1u/6.3V_4
VWG
PR118
8.06K/F_4
FBG
95835_VWG
4
ISNG
0.1u/10V_4
1000p/50V_4
COMPG
+5V_S5
PR131
422/F_4
ISPG
su
PC87
PC27
0.22u/25V_6
+1.05V_VTT
PC88
330p/50V_4
95835_COMPG
PR48
2.2_6
PR47
10_6
PR124
475K/F_4
PL7
0.36uH
PR137
2.61K/F_4
om
p.
PC81
150p/50V_4
PC92
+5V_S5
PR135
VIN
PQ31
AON6414AL
PHASE_GT
1.1K/F_4
2.49K/F_4
PC100
0.22u/10V_4
PR130
PR33
39p/50V_4
PC21
*220p/50V_4
PC82
PR27
*100/F_4
PR20
*2.26K/F_4
330p/50V_4
PC14
*820p/50V_4
PR54
10K/F_4
PC43
0.1u/10V_4
B56 PR130 changes from 2.55Kohm(CS22552FB01) to

2.49Kohm(CS22492BB00). 5/23
Change "+VIN_VCC_CORE" net to Vin. 5/17
Check pull up resister to

1.05V for H_PROCHOT#
PC99PC103 change from 33nf(CH3334K1B00) to 0.1uf(CH4104K9B03). 5/23
B57
+VCC_GFX
B08
PC107
0.22u/25V_6
UGATE_GT
1
2
3
PC16
330p/50V_4
PR58
*10_4
B24 PR128,PR132 change from 0 to short pad. 5/18
VIN
BOOT_GT
VCC_AXG_SENSE_R
6 VCC_AXG_SENSE
PC47
10u/6.3V_8
*Short_4
VSS_AXG_SENSE_R
6 VSS_AXG_SENSE
PR128

Del "VCC_GT_VIN" netname. 5/17
PR138
2.2/F_6
*Short_4
PC44
10u/6.3V_8
PR132
PC19
1000p/50V_4
PR59
*10_4
Parallel
PC45
0.1u/10V_4
ISEN_2 PR125
10K/F_4
VSUM-
1/F_4
PR24
*10K/F_4
PR26
ISEN_1
PC102
1000p/50V_4
Close to the
CPU side.

PROJECT : ZQR
Size
Document Number
Rev
1A
+VCC_CORE & +VCC_GFX (ISL95835)

Date:
5
Sheet

1
30
of
35

VIN
+3V
PR181
360K/F_4
+5V_S5
PCH_TON
PR180
100K_4
PR170
10_6
PCH_VCC
PC140
2200p/50V_4
PR173
2_6
PC138
4.7u/25V_8
PC139
4.7u/25V_8
PCH_BST1
PCH_DL
10
PCH_CS
GND
4
1
2
3
12
CS
PR70
PR182
66.5K/F_4
*SHORT_PAD_4
PR179
*0_4
PCH_MODE
PR175
*0_4
:/
/m
6 VSSP_SENSE
PR69
*4.7_6
PC56
*680p/50V_6
PC134
560u/2.5V_6X5.7
PC130
0.1u/50V_6
Close to output cap
yc
PR174
PQ44
AOL1718
RDSon 4.3mOhm
*SHORT_PAD_4
6 VCCP_SENSE
PL12
1uH
/x
su
PHASE
PCH_LX
1
2
3
PCH_DH
3
2
PU8
RT8238A LGATE
PAD
PC142
*0.1u/10V_4
UGATE
+1.05V_VTT
B19 Del JP15, connect to +1.05V_VTT. 5/18
PQ42
AOL1448
om
p.
EN
13
PGOOD
FB
PCH_EN
MODE
PR176
*SHORT_PAD_4
27,32,34 MAINON
PC141
0.1u/25V_6
BOOST
11
TON
5
VCC
9
27,33 HWPG_VTT
PCH_BST
PC136
1u/6.3V_4
+1.05V_VTT
1.05Volt +/- 5%
TDC : 10.6A
PEAK : 14.1A
OCP : 17A
Width : 440mil
PR171
11K/F_4
PC137
*100p/50V_4
PCH_FB
PR177
*SHORT_PAD_4
ht
tp
+5V_S5
Ton=(8.8p*360K*1.05)/19-0.5=179.81ns
Lcurrent=(19-1.05)*179ns/1uH=3.228A
Iocp=17-3.228/2=15.386A
Vcs=15.386*4.3mohm=0.06616V
Rcs=0.06616/1u=66.16Kohm
PR172
10K/F_4
VOUT=(1+R1/R2)*0.5
A

PROJECT : ZQR
Size
Document Number
Rev
1A
+PCH&VTT (RT8238A)
Date:
5
Sheet
1
31
of
35
+0.75V_DDR_VTT
0.75 Volt +/- 5%
TDC : 0.75A
PEAK : 1A
Width : 40mil
PC144
10u/6.3V_8

PC143
0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
PR178
*Short_6
VIN
8207A_DH
PC146
10u/6.3V_8
8207A_LX
5
PC145
10u/6.3V_8
8207A_DL
PC55
4.7u/25V_8
B20
Del JP5, connect to +1.5VSUS, del "+1.5VSUS_SRC" Netname. 5/18
20
+1.5V_SUS
CS_GND
GND
CS
PU9
RT8207L
MODE
V5IN
17
16
PR71
5.76K/F_4
15
+5V_S5
NC
PR74
100K/F_4
HWPG_1.5V 27
*Short_6
PR73
*Short_6
S5_1.8V
PR186
*SHORT_PAD_4
SUSON
27
S3_1.8V
PR187
*SHORT_PAD_4
MAINON
27,31,34
PR188
*0_4
PC147
*33p/50V_6
PR184
10K/F_4
+5V_S5
PC54
*680p/50V_6
PC132
560u/2.5V
400KHZ ) close to pc2008
:/
/m
B27 PR73,PR75 change from 0 to short pad. 5/18
VIN (For RT8207A
yc
PR185
620K/F_4
PR75
PC58
1u/10V_4
+3V
+1.5V_SUS
1 Volt +/- 5%
TDC : 10A
PEAK : 13A
OCP : 15A
Width : 400mil
PQ41
AOL1718
om
p.
PR72
5.1/F_6
PC57
1u/10V_4
13
12
S5
S3
VDDQSET
PGOOD
11
FOR DDR III
COMP
10
V5FILT
VDDQSNS
+5V_S5
NC
PC59
0.033u/50V_6
VTTREF
+SMDDR_VREF
14
+1.5V_SUS
PR67
*4.7_6
1
2
3
B22 Change "+1.5VSUS_SRC" Netname to "+1.5V_SUS". 5/18

5
PL11
1uH
DRVL
LL
DRVH
VBST
VTTSNS
18
/x
PGND
PC135
2200p/50V_6
su
PQ43
AOL1448
+SMDDR_VREF
0.75 Volt +/- 5%
TDC : 0.38A
PEAK : 0.5A
Width : 20mil
VTTGND
VLDOIN
VTT
GND
1
2
3
19
22
21
23
25
24
Vout = (PR150/PR149) X 0.75 + 0.75
S5_1.8V
PR183
*0_4
+1.5V_SUS
MAIND
3
MAIND
6,29,34
AO1718 Rdson=3.8~4.3mOhm
L(ripple current)
=(19-1.5)*1.5/(1u*400k*19)
~3.454A
Vtrip= (15-3.454/2)*4.3mohm=0.05707V
RILIM=Vtrip/10u=5.707Kohm
S3_1.8V
ht
PR189
10K/F_4
tp
8207A_SET
PQ45
AO3404
+1.5V
+1.5V
1.5 Volt +/- 5%
TDC : 0.38A
PEAK : 0.5A
Width : 20mil
S3
S5
+1.5VSUS
REF
VTT
S0
ON
ON
ON
S3
ON
ON
OFF
S4/S5
OFF
OFF
OFF

PROJECT : ZQR
Size
Document Number
Rev
1A
DDR 1.5V(RT8207A)
5
3
Date:
Sheet
1
32
of
35
G1
VCCSA
0.9V
0.8V
0.725V
0.675V
G0
B17 Del JP2, connect to VIN, del "VSA_VIN" Netname. 5/18

+5V_S5
VCCSA_SEL
VCCSA
0.8V
0.9V
PR148
10_6
VIN
default 0.9V
+3V
VSA_VCC
PR143
*100K_4
PQ30
AON7410
PC115
1u/6.3V_4
VSA_DH
PC118
2200p/50V_6
PC119
4.7u/25V_8
VSA_EN
*SHORT_PAD_4
VSA_CS 11
CS
PHASE
VSA_LX
B18 Del JP4, connect to +VCCSA, del "VSA_SRC" Netname. 5/18

PL6
2.2uH_7X7X3
LGATE
GND
PR49
*4.7_6
VSA_DL
PC37
0.1u/50V_6
VCCSA_SEL
PR149
*Short_4
VSA_FB
6 VCCSA_SENSE
PC34
*680p/50V_6
PR147
100_4
tp
PR142
1K_4
ht
PR141
1K_4
PC120
560u/2.5V_6X5.7
yc
VCCSA_SEL0
:/
/m
3
2
1
PQ25
AON7702
+VCCSA
om
p.
PAD
FB
G1
12
*SHORT_PAD_4
TP50
PC117
0.1u/25V_6
VSA_BST1
13
10
G0
PR150
71.5K/F_4
PR151
*SHORT_PAD_4
PR153
PU6
RT8241DZ
PR152
3.3_6
PC110
*0.1u/10V_4
EN
27,31 HWPG_VTT
3
4
/x
PR145
UGATE
BOOST
PGOOD
su
27 HWPG_VCCSA
VCC
3
2
1
+VCCSA
TDC : 4.5A
PEAK : 6A
OCP : 7A
Width : 180mil
OCP=7A
Iripple=(19-0.9)*0.9/(2.2u*300K*19)
=1.299A
Rth=14mohm*8*(7-0.65)/10uA
=71.125K
Ipeak=8.299A

PROJECT : ZQR
Size
Document Number
Rev
1A
+VCCSA(RT8241A)
Date:
5
Sheet
1
33
of
35
PC131
0.1u/25V_6
PU3
VIN
VIN
PH
11
VIN
PH
12
15
EN
BOOT
13
VSNS
PW RGD
14
COMP
GND
GND
AGND
*SHORT_PAD_4
54418-1.8_VFB
PC53
1000p/50V_4
RT/CLK
SS
PR63
182K/F_4
PR64
B15 Del JP14, connect to +1.8V. 5/18

D
*Short_6
PC52
B27 0.1u/50V_6
R1
PR60
100K/F_4
PC127
0.1u/10V_4
HWPG_1.8V 27
PR65
100K/F_4
PC133
10u/6.3V_8
PC128
10u/6.3V_8
54418-1.8_VFB
+3V
PC51
0.01u/25V_4
R2
PC50
1200p/50V_4
PR62
78.7K/F_4
/x
PC49
*100p/50V_4
+1.8V
PL10
1uH_7X7X3
22
21
20
19
18
17
PR61
15K/F_4
+1.8V
1.8 Volt +/- 5%
TDC : 1.31A
PEAK : 1.75A
Width : 60mil
HPA00835RTER
PH 10
1
PR68
MAINON
1.76A
16
Change p/n
PC129
10u/6.3V_8
PAD
PAD
PAD
PAD
PAD
PAD
B16
Del JP6, connect to +3VPCU. 5/18
PR66
*100K/F_4
RT8223M input power change to +3V_S5
+3VPCU
V0=0.8*(R1+R2)/R2
om
p.
For EC control thermal protection (output 3.3V)
:/
/m
VL
SYS_SHDN#
Need fine tune

for thermal protect point
PR161
200K_6
2.469V
Note placement position

S5_ON
PR99
1M_4
MAIND
6,29,32
MAIND
PR101
*100K/F_6
PR108
1M_4
PQ13
DMN601K-7
PQ14
DMN601K-7
PQ16
DMN601K-7
PQ15
DMN601K-7
PQ17
*DMN601K-7
PQ18
DMN601K-7
PC73
*2.2n/50V_4
4,29
PQ33
DMN601K-7
PU7A
LM393
PC125
0.1u/50V_6
2
PQ34
DMN601K-7
PR160
200K/F_4
A
PR98
*22_8
ht
PC126
0.1u/50V_6
PR96
22_8
PR159
200K/F_4
PR158
1.54K/F_4
PR169
10K_6_NTC
tp
VL
PQ19
DTC144EU
27,31,32 MAINON
PR165
*SHORT0603
PQ35
DTC144EU
PR97
22_8
+15V
S5_ON
PR95
22_8
+1.8V
3
27,29
S5_ON 2
PR94
22_8
+1.5V
MAINON_ON_G
4,6 MAINON_ON_G
PR104
1M_4
+0.75V_DDR_VTT
+5V
PQ40
AO3409
+3V
yc
VIN
PR166
1M_6
Thermal protection
PU7B
LM393
PD5
SW1010CPT
VIN
su

PROJECT : ZQR
Size
Document Number
Date:
Rev
1A
Discharge/1.8V)
5
Sheet
34
1 7/7 modify
of
35
REV
Model
CHANGE LIST
2011/05/11
B01 remove PR22 from BOM for power up issue.

B02 L5,L8,L10 Change PN to CX8BA470003.
ZQR MB
2011/05/16
B03 Change net closed to Audio Codec PCBEEP netname to BEEP_2

2011/05/17
B
D
B04 Change L6,L7,L9 to 0, remove C76,C96,C121 for CRT Test.

B05 Add R409, remove U5, C142 for saving cost.
B06 Change Bottom side 0 to short pad for cost and SMT cycle time issue;
R284,R295,R296,R392,R395,R401,R402,R403,R404,R408.
B07 Remove R178 short pad, connect to +5V_S5.
B08 Change "+VIN_VCC_CORE" net to Vin.
B09 Del JP1,JP13, connect to Vin, del "+VIN_VCC_CORE" netname.
B10 Del JP3, connect to Vin. Del "VCC_GT_VIN" netname.
B11 Del JP9,JP10 connect to Vin.
B12 Del JP11, connect to +3VPCU.
B13 Del JP12, connect to +5VPCU.
B14 PQ23PQ24 change symbol from N-MOS to P-MOS
2011/05/18
/x
su
Del JP14, connect to +1.8V.

Del JP6, connect to +3VPCU.
Del JP2, connect to VIN, del "VSA_VIN" Netname.
Del JP4, connect to +VCCSA, del "VSA_SRC" Netname.
Del JP15, connect to +1.05V_VTT.
Del JP5, connect to +1.5VSUS, del "+1.5VSUS_SRC" Netname.
Del JP7,JP8 connect to VIN.
Change "+1.5VSUS_SRC" Netname to "+1.5V_SUS".
Mount C70, C71 for +Vcc_core overshoot issue.
PR29,PR30,PR35,PR37,PR41,PR46,PR93,PR120,PR128,PR132,PR149(0_4) change from 0ohm to short-pad.
PR178(0_6) change from 0ohm to short-pad.
R114,R197,R206(0_4) change from 0ohm to short-pad.
L11,PR64,PR73,PR75,R96,R97,R98,R99,R133,R168(0_6) change from 0ohm to short-pad.
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
2011/05/20
R392,R197
Del short
Del short
Del short
Del short
Del short
Del short
Del short
Del C442.
change from short pad to 0.

pad R114, connect to PCIE_CLKREQ_LAN#.
pad R206, connect to MIC1-VREFO-L.
pad R284, connect to ME_WR#.
pad R401, connect to PLTRST#.
pad R403, connect to HP_MUTE#.
pad R386, del netname ACZ_SDIN0_R, connect to ACZ_SDIN0.
pad R133,R168, connect to GND.
2011/05/23
ht
B55 PR139 changes from 1.33Kohm(CS21332FB11) to 1.58Kohm(CS21582FB00).

B56 PR130 changes from 2.55Kohm(CS22552FB01) to 2.49Kohm(CS22492BB00).
B57 PC99PC103 change from 33nf(CH3334K1B00) to 0.1uf(CH4104K9B03).
tp
B46
B47
B48
B49
B50
B51
B52
B53
B54
yc
:/
/m
Page 20 +1.5V_SUS mount C149,C182,C160,C175,C249,C250,C257,C445,C444 Cap for EMI

Page 20 +3V C347,C341,C55,C303,C449,C275,C453,C459 Change to 100PF for EMI.
Page 20 +5V C496,C437,C460,C232,C304,C454 change 100PF for EMI.
Page 20 +5V_S5 C489,C289 change 100PF for EMI.
Page 20 +VCC_CORE C47 change 100PF for EMI.
KB Cap CP1,CP2,CP3,CP4,CP5,CP6 change to 220 PF and phase into BOM list for EMI.
BOT layer +VCC_GFX add 100pf x 3 C499,C500,C501 for EMI.
BOT layer +1.8V Add 100pF X2 C502,C503 for EMI.
TOP layer +1.8V Add 100pF X2 C506,C507 for EMI.
TOP layer +1.5V Add 100pF X2 C504,C505 for EMI.
USB C.M Chock L12,L13,L14 Phase into BOM list, cancel 0 R166,R167,R174,R175,R201,R202 for EMI.
PR4 4.7ohm / PC5 1000pf phase into BOM list for EMI.
Change R386 from 22 to short pad.
Add a MOSFET Q26,R410,R412 to separate CODE SYNC and PCH Strap signal to avoid leakage issue.
Change R216,R221 from 56 to 47 for ACER SPEC.
Change 0 R5,R6,R210,R211,R225,R230 to short pad, remove CMC L1,L15,L20 for SMT.
Change CMC L12,L13,L14 PN from "DC09004A014" to "CX1HN900000".
Remove C315 for cost issue.
om
p.
2011/05/19
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
3C

Document Number
Date:
Rev
1A
Change list
Sheet
5
PROJECT MODEL :
DOC NO.
PROJECT : ZQR
Size
35
of
ZQR
PART NUMBER:
APPROVED BY:
DATE:
DRAWING BY:
REVISON:
2011/05/09
1A
35
4

.8041c Quanta ZQR Aspire-4349

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.8041c Quanta ZQR Aspire-4349

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5

3/5V SYS PWR

Dual SPI ROM

D/B USB*2 P23

DDR III - SODIMM 1

CPU CORE PWR

Dual Channel DDR III

DDR III - SODIMM 0

DDR SYSTEM MEMORY

SPI ROM Touch Pad

Quanta Computer Inc.

(D/A Type) P24

Monday, May 09, 2011

CHARGE PUMP POWER

CPU/SODIMM CORE POWER

SODIMM Termination POWER

Internal GPU POWER

MINI CARD/NEW CARD POWER

CPU VTT POWER

PCH CORE POWER

CPU CORE POWER

SWITCHABLE PWM IC POWER

GPU CORE POWER

GPU I/O POWER

VRAM CORE POWER

PCH/GPU/Peripheral component POWER

Thermal Follow Chart

Quanta Computer Inc.

Monday, May 09, 2011

PWR Status & GPU PWR CRL & THRM

Slave ADDRESS :A0H

Slave ADDRESS :A4H

Quanta Computer Inc.

Monday, May 09, 2011

Sandy Bridge Processor (DMI,PEG,FDI)

43_4 CPU_PLTRST#_R AR33

AK1 SM_RCOMP_0 R151

130/F_4 PM_DRAM_PW RGD_R

Quanta Computer Inc.

PEG_ICOMPO signals should

Sandy Bridge 1/4

PEG_ICOMPI and RCOMPO signals should

8,30 IMVP_PW RGD

eDP_COMPIO and ICOMPO signals should

DP & PEG Compensation

JTAG & BPM

PCI EXPRESS* - GRAPHICS

SNB_IVB# N.A at SNB EDS #27637 0.7v1

Sandy Bridge Processor (CLK,MISC,JTAG)

Monday, May 23, 2011

Sandy Bridge Processor (DDR3)

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

Quanta Computer Inc.

Sandy Bridge 2/4

Monday, May 23, 2011

Sandy Bridge Processor (POWER)CPU VTT

B23 Mount C70, C71 for +Vcc_core overshoot issue. 5/18

B45 Remove C315 for cost issue. 5/19

B54 Del C442. 5/20

CAD Note: +VDDR_REF_CPU should

Quanta Computer Inc.

Sandy Bridge 3/4