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EE
GEN FR
ALO
CAT28C65B
64K-Bit CMOS PARALLEL EEPROM
LE
A D F R E ETM
FEATURES
Fast read access times:
90/120/150ns
temperature ranges
Active: 25 mA max.
Standby: 100 A max.
1 to 32 bytes in 5ms
Page load timer
Toggle bit
DATA polling
BUSY
RDY/BUSY
5ms max
CMOS and TTL compatible I/O
DESCRIPTION
The CAT28C65B is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, a RDY/BUSY pin and Toggle status bits
signal the start and end of the self-timed write cycle.
BLOCK DIAGRAM
A5A12
ADDR. BUFFER
& LATCHES
ROW
DECODER
VCC
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
32 BYTE PAGE
REGISTER
I/O BUFFERS
TIMER
A0A4
8,192 x 8
EEPROM
ARRAY
DATA POLLING,
TOGGLE BIT &
RDY/BUSY LOGIC
ADDR. BUFFER
& LATCHES
I/O0I/O7
COLUMN
DECODER
RDY/BUSY
Doc. No.
No. 1009,
1009, Rev.
Rev. E
E
Doc.
CAT28C65B
PIN CONFIGURATION
DIP Package (P, L)
RDY/BUSY
A12
1
2
28
27
VCC
WE
A7
A6
3
4
26
25
NC
A8
A5
5
6
24
A9
A11
A4
A3
7
8
A2
A1
A0
9
10
I/O0
I/O1
11
12
I/O2
VSS
13
14
23
22
OE
21
20
A10
CE
19
18
I/O7
I/O6
17
I/O5
I/O4
I/O3
16
15
RDY/BUSY
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
A6
A5
A4
A3
VCC
WE
NC
4
5
6
7
8
9
10
25
24
23
22
21
20
19
A8
A9
A11
OE
11
12
13
14
18
17
A8
A9
A11
NC
OE
A10
CE
I/O7
OE
A11
A9
A8
NC
WE
VCC
RDY/BUSY
A12
A7
A6
A5
A4
A3
I/O6
PIN FUNCTIONS
Pin Name
Function
Pin Name
Function
A0A12
Address Inputs
WE
Write Enable
I/O0I/O7
Data Inputs/Outputs
VCC
5 V Supply
CE
Chip Enable
VSS
Ground
OE
Output Enable
NC
No Connect
RDY/BSY
Ready/Busy Status
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
A2
A1
A0
NC
I/O0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
TOP VIEW
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
28
27
26
A7
A12
RDY/BUSY
NC
VCC
WE
NC
1
2
3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
CAT28C65B
*COMMENT
Parameter
Min.
Max.
Units
Test Method
NEND(1)
Endurance
105
Cycles/Byte
TDR(1)
Data Retention
100
Years
VZAP(1)
ESD Susceptibility
2000
Volts
ILTH(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
MODE SELECTION
Mode
CE
WE
OE
Read
I/O
Power
DOUT
ACTIVE
DIN
ACTIVE
DIN
ACTIVE
High-Z
STANDBY
High-Z
ACTIVE
Units
Conditions
Input/Output Capacitance
10
pF
VI/O = 0V
CIN(1)
Input Capacitance
pF
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
CAT28C65B
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC
30
mA
CE = OE = VIL,
f = 1/tRC min, All I/Os Open
ICCC(1)
25
mA
CE = OE = VILC,
f = 1/tRC min, All I/Os Open
ISB
mA
ISBC(2)
100
CE = VIHC,
All I/Os Open
ILI
10
10
ILO
10
10
VIH(2)
VCC +0.3
VIL(1)
0.3
0.8
VOH
2.4
VOL
VWI
0.4
3.5
IOH = 400A
IOL = 2.1mA
Note:
(1) VILC = 0.3V to +0.3V.
(2) VIHC = VCC 0.3V to VCC +0.3V.
CAT28C65B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V 10%, unless otherwise specified.
Symbol
Parameter
28C65B-90
28C65B-12
28C65B-15
Min.
Min.
Min.
Max.
90
Max.
120
Max.
tRC
tCE
CE Access Time
90
120
150
ns
tAA
90
120
150
ns
tOE
OE Access Time
50
60
70
ns
tLZ(1)
ns
tOLZ(1)
ns
tHZ(1)(2)
50
50
50
ns
tOHZ(1)(2)
50
50
50
ns
tOH(1)
150
Units
ns
ns
2.0 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.8 V
0.45 V
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
CAT28C65B
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V 10%, unless otherwise specified.
Symbol
Parameter
28C65B-90
28C65B-12
28C65B-15
Min.
Min.
Min.
Max.
5
Max.
5
Max.
Units
ms
tWC
tAS
ns
tAH
100
100
100
ns
tCS
CE Setup Time
ns
tCH
CE Hold Time
ns
tCW(2)
CE Pulse Time
110
110
110
ns
tOES
OE Setup Time
ns
tOEH
OE Hold Time
ns
tWP(2)
OE Pulse Width
110
110
110
ns
tRB
tDS
60
60
60
ns
tDH
ns
tINIT(1)
10
10
10
ms
tBLC(1)(3)
.05
100
.05
100
.05
100
120
120
120
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
CAT28C65B
can be used to eliminate bus contention in a system
environment.
DEVICE OPERATION
Read
Byte Write
WE
tOHZ
HIGH-Z
DATA OUT
tHZ
tOH
tOLZ
DATA VALID
DATA VALID
tAA
WE Controlled]
Figure 4. Byte Write Cycle [WE
tWC
ADDRESS
tAS
tAH
tCH
tCS
CE
OE
tOES
tWP
tOEH
WE
tRB
RDY/BUSY
DATA OUT
DATA IN
tBLC
HIGH-Z
HIGH-Z
HIGH-Z
DATA VALID
tDS
tDH
CAT28C65B
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Page Write
The page write mode of the CAT28C65B (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single EEPROM write
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
tAH
tBLC
tCW
CE
tOEH
OE
tOES
tCS
tCH
WE
tRB
RDY/BUSY
HIGH-Z
HIGH-Z
HIGH-Z
DATA OUT
DATA IN
DATA VALID
tDS
tDH
CE
t BLC
t WP
WE
ADDRESS
t WC
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
CAT28C65B
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0I/O6
Figure 7. DATA Polling
ADDRESS
CE
WE
tOEH
tOES
tOE
OE
tWC
I/O7
DIN = X
DOUT = X
DOUT = X
CE
tOEH
tOES
tOE
OE
I/O6
(1)
(1)
tWC
CAT28C65B
HARDWARE DATA PROTECTION
WRITE DATA:
ADDRESS:
WRITE DATA:
ADDRESS:
AA
ADDRESS:
1555
WRITE DATA:
55
ADDRESS:
0AAA
WRITE DATA:
A0
1555
ADDRESS:
SOFTWARE DATA
(1)
PROTECTION ACTIVATED
WRITE DATA:
WRITE DATA:
XX
WRITE DATA:
TO ANY ADDRESS
ADDRESS:
WRITE DATA:
ADDRESS:
ADDRESS:
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC
Max., after SDP activation.
10
CAT28C65B
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
AA
1555
55
0AAA
tWC
A0
1555
BYTE OR
PAGE
CE
tWP
tBLC
WRITES
ENABLED
WE
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
tWC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Speed
90: 90ns
12: 120ns
15: 150ns
11
CAT28C65B
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C65B
Optional
Company
ID
Product
Number
-15
Temperature Range
Blank = Commercial (0C to +70C)
I = Industrial (-40C to +85C)
A = Automotive (-40 to +105C)*
Package
P: PDIP
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (Lead free, Halogen free)
Speed
90: 90ns
12: 120ns
15: 150ns
12
REVISION HISTORY
Date
Revision Comments
03/29/04
04/19/04
11/17/04
03/29/05
AE2
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Companys corporate office at 408.542.1000.
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
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Publication #:
Revison:
Issue date:
1009
E
03/29/05