Lecture17 2005 1 6

IP Core Design
Lecture 17
Introduction to AXI
Juinn-Dar Huang, Ph.D.
Assistant Professor
jdhuang@mail.nctu.edu.tw
November 2004
Outlines
Juinn-Dar Huang
Introduction to AXI
AXI overview
Signal definitions
Channel handshaking
Addressing options
Slave responses
Protocol Details
Transaction ordering
Data transfers
Clock and reset
copyright 2004
Background
Juinn-Dar Huang
AXI (Advanced eXtensible Interface) by ARM

Also known as AMBA 3.0
Debut in Embedded Professor Forum (EPF), 2003
Version 1.0 announced in March 2004
Introduction to AXI
copyright 2004
Objectives
Juinn-Dar Huang
Provide high bandwidth and low latency

Enable high frequency operations
Fit for devices with high initial latency
e.g., DRAM controllers
Introduction to AXI
Provide flexibility of interconnect architectures

Be (functionally) backward-compatible with
existing AHB and APB
not plug-n-play
bus bridges are required
copyright 2004
Key Features
Juinn-Dar Huang
Introduction to AXI
Separate address/control and data phases

Separate read and write channels to enable more
efficient DMA controllers
Burst-based transactions with only start address
issued
Unaligned data transfers using separate byte-lane
strobes
Multiple outstanding transactions
Out-of-order transaction completion
Latency-insensitive protocol by register slicing
copyright 2004
Channel Architecture
Write Address/Control
AWREADY
Juinn-Dar Huang
Read Address/Control
ARREADY
AXI
AXI
Write Data
Introduction to AXI
Master
copyright 2004
WREADY
Slave
Read Data
RREADY
Write Response
BREADY
5 unidirectional channels
5
Read Transaction (1/2)

ARREADY
Juinn-Dar Huang
AXI
AXI
Master
Slave
Read Data
Introduction to AXI
copyright 2004
RREADY
Master issues address and control

6
Read Transaction (2/2)

ARREADY
Juinn-Dar Huang
AXI
AXI
Master
Slave
Read Data
Introduction to AXI
copyright 2004
RREADY
Slave returns data and response

7
Write Transaction (1/3)

AWREADY
Juinn-Dar Huang
Write Data
AXI
AXI
WREADY
Master
Introduction to AXI
copyright 2004
Slave
Write Response
BREADY
Master issues address and control

8

AWREADY
Juinn-Dar Huang
Write Data
AXI
AXI
WREADY
Master
Introduction to AXI
copyright 2004
Slave
Write Response
BREADY
Master sends data

9

AWREADY
Juinn-Dar Huang
Write Data
AXI
AXI
WREADY
Master
Introduction to AXI
copyright 2004
Slave
Write Response
BREADY
Slave acknowledges
10
AMBA 2.0 AHB Burst
Juinn-Dar Huang
A31
Introduction to AXI
Address and Data are linked together (by HREADY signal)
copyright 2004
11
AXI Burst Start Address for a Burst
Juinn-Dar Huang
A31
Introduction to AXI
copyright 2004
Reduce the address channel utilization

Use Address/Control channel more efficiently
12
Outstanding Transactions
A31
Juinn-Dar Huang
Introduction to AXI
Decouple the fixed link between address and data

no HREADY-like signal to synchronize the pipeline
Enable parallel processing of transactions

Avoid a high-initial-latency slave blocking the
channel
copyright 2004
13
Out-of-Order Completion
A31
Juinn-Dar Huang
Introduction to AXI
Fast slaves may return data before slow slaves

Complex slaves may return data out of order
extremely helpful to DMAC and DRAMC
Effectively reduce the transaction latency
copyright 2004
14
Data Interleaving
A31
Juinn-Dar Huang
Introduction to AXI
Further boost the utilization of data bus

Data within a burst is always in order
each transaction has a unique ID
copyright 2004
15
Channel Handshaking
Two-way handshaking (VALID READY)
Juinn-Dar Huang
used in all 5 channels

source uses VALID to indicate when valid data is
available
destination uses READY to indicate the data is
accepted
Introduction to AXI
For read/write data channels

a LAST signal is used to indicate the last data transfer
is taking place
copyright 2004
16
Channel Properties
Address channels
Juinn-Dar Huang
variable-length burst, 1-16 data transfers per burst

a transfer can be of 1, 2, 4, , 64, 128 bytes
3 burst modes - fixed, incrementing, wrapping
Write data channel

each byte lane has its own strobe signal
Introduction to AXI
Byte Lane 4n+0

1
0
0
WSTRB[0]
Byte Lane 4n+1
WSTRB[1]
Byte Lane 4n+2
WSTRB[2]
Though bus width is 32-bit,

Only bytes on 4n+0 and 4n+3 lanes
are valid for writes in this transfer
Byte Lane 4n+3

1
WSTRB[3]
copyright 2004
17
Interconnect Matrix
Interconnection
Juinn-Dar Huang
shared bus architecture

multi-layer architecture
something in-between
Introduction to AXI
copyright 2004
Master-like port
Slave-like port
18
Read Burst Example
Juinn-Dar Huang
Introduction to AXI
19
copyright 2004
4-beat read burst
Overlapping Read Burst Example
Juinn-Dar Huang
Introduction to AXI
3-beat read burst + 2-beat read burst

Enable a slave to begin preparing data of the 2nd burst
before the completion of the 1st burst
copyright 2004
20
Write Burst Example
Juinn-Dar Huang
Introduction to AXI
21
copyright 2004
4-beat write burst
Transaction Ordering (1/2)

Out-of-order transaction completion is allowed
how? transaction ID is required
Juinn-Dar Huang
Transfers with the same transaction ID must be

completed in order
Applications
no way to distinguish the transfer order within a

transaction
Introduction to AXI
enable fast-responding slaves to complete in advance

of earlier transactions with slower slaves
complex slaves can return read data out-of-order
copyright 2004
e.g., DRAM controllers
22
Transaction Ordering (2/2)

If a master wishes to have OOO transactions
capability to supply different ID tags is required
Juinn-Dar Huang
If a master requires no OOO transactions

all transactions with the same ID tag
For multi-master systems

interconnect is responsible for appending a Master ID
Introduction to AXI
i.e., to ensure that ID tags from different masters are unique
Simple masters can issue all transactions with the

same ID tag
Simple slaves can respond transactions in order
regardless of the ID tag
copyright 2004
23
Signals of Write Address Channel

Signal
Source
Description
Juinn-Dar Huang
Introduction to AXI
AWID[3:0]
Write address ID.
AWADDR[31:0]
Write address. The 1st address in a write burst.
AWLEN[3:0]
Burst length. 1-16 transfers in a burst.
AWSIZE[2:0]
Burst size. 1, 2, 4, , 64, 128 bytes per transfer.
AWBURST[1:0]
Burst type. Fixed, incrementing, or wrapping.
AWVALID
Write address/control valid.
AWREADY
Write address/control accepted.
copyright 2004
24
Signals of Write Data Channel
Signal
Source
Description
Juinn-Dar Huang
Introduction to AXI
WID[3:0]
Write data ID. Must match AWID.
WDATA[31:0]
Write data. Can be 8, 16, , 512, 1024 bits wide.
WSTRB[3:0]
Write strobes. One strobe for each byte lane.
WLAST
Last write transfer in a burst.
WVALID
Write data valid.
WREADY
Write data accepted.
copyright 2004
25
Signals of Write Response Channel
Juinn-Dar Huang
Signal
Source
Description
Introduction to AXI
BID[3:0]
Write data ID. Must match AWID.
BRESP[1:0]
Write response.
BVALID
Write response valid.
BREADY
Write response accepted.
copyright 2004
26
Signals of Read Address Channel

Signal
Source
Description
Juinn-Dar Huang
Introduction to AXI
ARID[3:0]
Read address ID.
ARADDR[31:0]
Read address. The 1st address in a read burst.
ARLEN[3:0]
Burst length. 1-16 transfers in a burst.
ARSIZE[2:0]
Burst size. 1, 2, 4, , 64, 128 bytes per transfer.
ARBURST[1:0]
Burst type. Fixed, incrementing, or wrapping.
ARVALID
Read address/control valid.
ARREADY
Read address/control accepted.
copyright 2004
27
Signals of Read Data Channel
Signal
Source
Description
Juinn-Dar Huang
Introduction to AXI
RID[3:0]
Read data ID. Must match ARID.
RDATA[31:0]
Read data. Can be 8, 16, , 512, 1024 bits wide.
RRESP[1:0]
Read response.
RLAST
Last read transfer in a burst.
RVALID
Read data valid.
RREADY
Read data accepted.
copyright 2004
28
Handshaking Process
VALID READY two-way handshaking
Juinn-Dar Huang
sources generate VALID to indicate when the data is

valid
destinations generate READY to indicate when the data
is accepted
Introduction to AXI
No combination paths between masters and

slaves
all timing paths must be registered
Successful transfer must qualify both VALID and

READY
copyright 2004
29
Handshaking Timing Diagrams

1. VALID before READY
Juinn-Dar Huang
2. READY before VALID
Introduction to AXI
copyright 2004
3. VALID with READY
30
Fast Handshaking
Two-way handshaking typically needs 2 cycles
1st cycle for VALIID high, and 2nd cycle for READY
Juinn-Dar Huang
If a slave can always accept any valid address
Introduction to AXI
i.e., never require wait cycles

AWREADY/ARREADY can be always high for 1-cycle
handshaking
If a master can always accept any valid data

i.e., never require wait (busy) cycles
RREADY can be always high for 1-cycle handshaking
copyright 2004
31
Dependency in Read Transactions
Juinn-Dar Huang
A slave can wait for ARVALID before asserting ARREADY

A slave must wait for ARVALID & ARREADY before
asserting RVALID
A master can wait for RVALID before asserting RREADY
ARVALID
RVALID
Introduction to AXI
can wait
copyright 2004
must wait
ARREADY
RREADY
32
Dependency in Write Transactions
Juinn-Dar Huang
A slave can wait for AWVALID, WVALID, or both before

asserting AWREADY
A slave can wait for AWVALID, WVALID, or both before
asserting WREADY
A slave must wait for WVALID & WREADY before
asserting BVALID
A master can wait for BVALID before asserting BREADY
Introduction to AXI
can wait
AWVALID
copyright 2004
BVALID
WVALID
AWREADY
must wait
WREADY
BREADY
33
Burst in AXI
Juinn-Dar Huang
Masters provide the start address of a burst

Slaves are in charge to calculate the addresses of
subsequent transfers in a burst
Bursts can not cross 4KB boundary
Introduction to AXI
i.e., address is allocated to a slave in 4KB unit

simplify the decoder within an interconnect
simplify the address generator within a slave
copyright 2004
34
Burst Length
Juinn-Dar Huang
Introduction to AXI
No early burst termination

allowed
For a write transfer, write
strobes can be used to
disable writes on certain byte
lanes
In a read transfer, a master
can just discard the read data
copyright 2004
35
Burst Size
Juinn-Dar Huang
For incrementing and wrapping

bursts and transfer sizes are
smaller than the data bus width
transfers are on different byte lanes
for each beat
For fixed bursts

Introduction to AXI
address remains constant within a

burst
every transfer uses the same byte
lanes
The size of any transfer can not

exceed the data bus width
copyright 2004
36
Burst Type (1/2)
Juinn-Dar Huang
Introduction to AXI
37
copyright 2004
Burst Type (2/2)

Fixed burst
Juinn-Dar Huang
address remains constant within a burst

for FIFO-like devices
Incrementing burst
increment value depends on the transfer size
for typical sequential memory-like devices
Introduction to AXI
Wrapping burst
wrap boundary = transfer_size x number_transfer
two restrictions
the start address must be aligned to the transfer size
burst length must be 2, 4, 8, or 16 only
for cache line refill
copyright 2004
38
Advanced Controls
Cache support
Juinn-Dar Huang
ARCACHE[3:0], AWCACHE[3:0]
bufferable; cacheable; read allocate; write allocate
Access protection
ARPROT[2:0], AWPROT[2:0]
normal or privileged; secure or not; instruction or data
Introduction to AXI
Atomic operation
ARLOCK[1:0], AWLOCK[1:0]
normal, exclusive, or locked access
copyright 2004
39
Slave Responses (1/2)
Juinn-Dar Huang
Introduction to AXI
40
copyright 2004
Slave Responses (2/2)

Read response is returned along with read data
different responses for different transfers in a burst
Juinn-Dar Huang
Write response is returned via the dedicated Write

Response channel
just one response available for an entire burst
Introduction to AXI
No early burst termination allowed even if there

are transfer errors
Masters support multiple outstanding transactions
must be able to handle an erroneous earlier transaction
while later transactions are underway
copyright 2004
41
Response Type
OKAY
everything is fine
Juinn-Dar Huang
EXOKAY
SLVERR (slave error)
Introduction to AXI
FIFO/buffer overflow or underflow

unsupported transfer size
try to write a read-only region
try to access an address where no registers are there
access timeout
DECERR (decoder error)

no slave presented at that address
copyright 2004
42
Protocol Details
Transaction Ordering Rules
Juinn-Dar Huang
Introduction to AXI
Transactions from different masters have no ordering

restrictions
Transactions from the same master but with different IDs
have no ordering restrictions
Write transactions with the same AWID must complete in
order
Read transactions with the same ARID must complete in
order
a salve must complete transactions with the same ARID in order
an interconnect must ensure read transactions from different
slaves in order
copyright 2004
44
Read and Write Ordering
Juinn-Dar Huang
No ordering restrictions between read and

write transactions
If a given order is required
the master must ensure the earlier transaction is
complete before issuing the later transaction
Introduction to AXI
A read transaction is completed when the last

data/response transfer is received
A write transaction is completed when the write
response is received
sending out all write data is not an end
copyright 2004
45
ID Tag Width
Suggestions
Support transaction ID up to 4 bits for a master
Juinn-Dar Huang
16 outstanding transactions at most for a master
Support up to 16 master ports for an interconnect

Master ID up to 4 bits
Support 8-bit transaction ID for a slave

Introduction to AXI
copyright 2004
4-bit
8-bit
Master
Slave
Interconnect
4-bit
Master
46
Narrower Transfers
Juinn-Dar Huang
32-bit data bus

5-beat transfer
starting address is 4n+0
transfer size is 1-byte
Introduction to AXI
copyright 2004
64-bit data bus

3-beat transfer
starting address is 8n+4
transfer size is 4-byte
47
Unaligned Transfers (1/2)

WSTRB[3:0] = 4b1110
for the 1st transfer
Juinn-Dar Huang
WSTRB[3:0] = 4b1000
Introduction to AXI
Masters must ensure that

the low-order address must be consistent with byte lane strobes
Or, slaves can just ignore the low-order address and
refer byte lane strobes only
copyright 2004
48
Unaligned Transfers (2/2)

WSTRB[7:0] = 4h0F
Juinn-Dar Huang
Introduction to AXI
WSTRB[7:0] = 4h80
copyright 2004
49
System Clock
ACLK
Juinn-Dar Huang
all inputs are sampled on the rising edge of ACLK

all outputs changes just after the rising edge of ACLK
strictly synchronous design fashion
no combinational paths between master and slave I/Os
all timing paths must be registered
Introduction to AXI
copyright 2004
50
System Reset
ARESETn
Juinn-Dar Huang
active-low signal
can be asserted asynchronously
must be deasserted synchronously
During reset
Introduction to AXI
masters must drive ARVALID, AWVALID and WVALID

low
slaves must drive RVALID and BVALID low
copyright 2004
51

Lecture17 2005 1 6

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Lecture17 2005 1 6

Transféré par

Droits d'auteur :

Formats disponibles

IP Core Design

AXI (Advanced eXtensible Interface) by ARM

Provide high bandwidth and low latency

Provide flexibility of interconnect architectures

Separate address/control and data phases

Read Transaction (1/2)

Master issues address and control

Read Transaction (2/2)

Slave returns data and response

Write Transaction (1/3)

Master issues address and control

Write Transaction (2/3)

Master sends data

Write Transaction (3/3)

AMBA 2.0 AHB Burst

Address and Data are linked together (by HREADY signal)

AXI Burst Start Address for a Burst

Reduce the address channel utilization

Decouple the fixed link between address and data

Enable parallel processing of transactions

Fast slaves may return data before slow slaves

Effectively reduce the transaction latency

Further boost the utilization of data bus

used in all 5 channels

For read/write data channels

variable-length burst, 1-16 data transfers per burst

Write data channel

Byte Lane 4n+0

Though bus width is 32-bit,

Byte Lane 4n+3

shared bus architecture

Read Burst Example

4-beat read burst

Overlapping Read Burst Example

3-beat read burst + 2-beat read burst

Write Burst Example

4-beat write burst

Transaction Ordering (1/2)

Transfers with the same transaction ID must be

no way to distinguish the transfer order within a

enable fast-responding slaves to complete in advance

e.g., DRAM controllers

Transaction Ordering (2/2)

If a master requires no OOO transactions

For multi-master systems

i.e., to ensure that ID tags from different masters are unique

Simple masters can issue all transactions with the

Signals of Write Address Channel

Write address ID.

Write address. The 1st address in a write burst.

Burst length. 1-16 transfers in a burst.

Burst size. 1, 2, 4, , 64, 128 bytes per transfer.

Burst type. Fixed, incrementing, or wrapping.

Write address/control valid.

Write address/control accepted.

Signals of Write Data Channel

Write data ID. Must match AWID.

Write data. Can be 8, 16, , 512, 1024 bits wide.

Write strobes. One strobe for each byte lane.

Last write transfer in a burst.

Write data valid.

Write data accepted.

Signals of Write Response Channel