CURRICULUM VITAE

VIJAY KUMAR MAGRAIYA

Education
Indian Institute of Information Technology and Management, Gwalior (MP).
2-Year M.Tech (VLSI Design):2004-06.
Aggregate CGPA: 6.90/10
Madhav Inastitute of Technology &Science, Gwalior (MP).
Bachelor of Engineering (Electronics):1999-03.
Aggregate Percentage: 61.79%

Areas of Interest

Advanced Logic design

Analog Circuit Design
Verilog Programming
VHDL Programming

Working Experience
Presently working as Asst. Prof. & Coordinator M.Tech. in EC department at ShriRam
College of Engineering & Management, Banmore (From July 2010 to till date).
I have worked as Head & Lecturer in EC department at Nagaji Institute of Technology &
Management, Gwalior (From July 2009 to July 2010).
I have worked as lecturer in ECE department at Ambala College of Engg. & Applied
Research, Ambala Cantt. (From August 2007 to July 2009).
I have worked as lecturer in ECE department at HMRITM, Hamidpur, Delhi-36 (From
January 2007 to August 2007).
I have worked as lecturer in EC department at N.I.T.M., Gwalior (From August 2006 to
December2006).

VLSI Proficiency
Hardware Languages
CAD tools
Front-end tools
Backend tools

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VHDL, Verilog.

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C,C++
MS-office, Macromedia Flash5
Windows NT/9X,XP

Xilinx ISE 6.1i, ModelSim SE-EE 5.4a

Tanner L-Edit, PSpice, Mentor Graphics.

Software Proficiency
Languages
Packages
Operating Systems

Extracurricular Activities & Achievements

Got 2nd prize in 200 m run in Athletics Games at Shivpuri (distt. Level).

 Got many prizes in cultural programs at school level.

Qualified Gate-2004.

Projects & Dissertation

Radio Remote Control using DTMF (Dual Tone Multiple Frequency):[B.E. Project]
Radio remote control through FM transmission is an interesting proposition. The DTMF
remote control system has the following main feature: It allows remote control of up to 12 electrical/electronic appliances through a compact
radio remote. The control application may vary from simple ON/OFF operation to
complex operation.
It allows the user to perform the control function within the station (in a range of about
30 meters) without the use of any telephone line.
Low Power Design of Signed Pipelined Array Multiplier:[M.Tech. Thesis] To make the
multiplier run-time reconfigurable and improve its power awareness, a selective design
method to design pipelined signed array multiplier is proposed in the report. Along with the
2-D pipeline gating technique, the designed reconfigurable multipliers are able to process
operands in any length without sign extension. These designs also have very good power
awareness.
R8 Processor implementation using SystemC:[M.Tech. Summer Project]
Objective:
Understanding the Risc vs Cisc Architecture for processor design.
Achieve a real experience of processor design.
To learn about Hardware modeling language.
Designing load/store architecture of processor design.
Generate a platform to the research work on system on chip and network on chip
area.

Conferences & Workshops

Participated in National Conference on Modern Developments in Engineering & Sciences
organized by Ambala College of Engineering & Applied Research, Ambala from February
27th & 28th, 2009.
[1] Vijay Kumar Anand, N.B.Singh, Vijay Kumar Magraiya RTL Implmentation of 16 bit
fixed point data processorpublished in the proceedings of Nattional Conference, NCMDES
2009, vol 1, pp ECE-12 at ACE, Ambala
[2] Vijay Kumar Magraiya, Jai praksh Tamotiya, Vijay Kumar Anand, Parul Dogra Channel
identification using CSB estimation algorithm published in the proceedings of Nattional
Conference NCMDES 2009, vol 1, pp ECE-10 at ACE, Ambala.
Participated in National Workshop on Quality Assurance in Technical Education organized
by Madhav Institute of Technology & Science, Gwalior, February 6 th & 7th , 2010.
Participated in International Conference on VLSI, Communication and Networks (VCAN
2011) organized by Department of Electronics & Communication Engineering, Institute of
Engineering & Technology, M.I.A., Alwar-301030, December 24th & 25th, 2011.

[1] Bhanu Pandey, Jaydeep Singh Parmar, Dhiraj Shrivastava, Vijay Kumar Magraiya
Analysis & characterization of Strained Silicon p-MOS and n-MOS having Si 3N4 cap layer
published in the proceedings of International Conference on VCAN-2011, vol 1, pp VCAN11 at IET, Alwar

Personal Background
Fathers Name
Date of Birth
Permanent Address

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Contact no.
Email Id

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Date:
Place:

Shri K. L. Magraiya
8th September 1980
L.I.G. B 2/2, Tansen Nagar,
Gwalior, M.P. 474002
0751-2426443, +919691845789
vijay.magraiya@gmail.com.

Vijay Kumar Magraiya