Exercise of

FPGA-Based Digital System Design

Prof. C. Abbate - A.A. 2015/2016

The FSK Demodulator

Introduction.
In this exercise the FSK demodulator will be simulated and realized by using FPGA hardware.

Design of FSK Demodulator.

The schematic of the circuit is reported in the next picture:

The proposed receiver has the following pins:

clock:

clock of the system;

sclr:

synchronous clear. Is the reset of the system;

datain:

FSK input of the system;

out_FSK:

demodulated output data stream.

Before starting the design please, copy the folder of TX_FSK of last exercise in order to have a
backup.
Run QuartusII and open the last project TX_FSK.
In this project, please, Create a new Block Diagram / Schematics File called
RX_FSK and draw the circuit.
Note: For each component of the new schematic, please use an instance name that differ from
the name used in TX_FSK in order to avoid errors. For example you can use an instance
name starting from 200.
-

Please calculate the threshold value for the lpm_compare and the required bits.

Remove the schematic file of TX_FSK and set as Top Level Entity the realized
schematic.

Remove from the project also the Test beng file of TX_FSK.

Please compile the project by using the icon

See the compilation report.

Project Simulation.
In order to simulate the project a Verilog test beng file must be generated.
and select Verilog HDL File from

In order to create a Verilog please, push on

Design Files and push

OK

.
This will open an empty file in which to write the necessary Verilog instructions. An example of a
listing is shown in the figure. The full version can be downloaded from the web site. Define the
system clock by setting the clock frequency to 3.68MHz. Also in the list it has been defined the
periods related to the mark-signal ("1") and space ("0"), according to the Bell202 standards. The
auxiliary register "bit" is used in order to change the frequency of the input signal during the time
evolution defined with the "initial" block.
Set the simulation options trough the tools Assignments/Settings/EDA Tool
Settings/Simulation, and insert in Compile test bench the name of new generated test
beng.

Launch a new compilation. After Run the simulation by the command Tools/RunEDA
Simulation Tool/EDA RTL Simulation and see the results.
Please, analyze and comment the results. See also the counter evolution (conteggio) as analog
signal.

Experimental Verification of the Project.

Please create a TX_FSK block from the FSK transmitter, and a block from the RX_FSK and insert
it in a new schematic called MODEM_FSK as reported in the next picture.

Assign the FPGA pin as in the picture:

1) Pin 16= input sclr (pin connected to the switch 6);
2) Pin 15= input data (pin connected to the switch 5);
3) Pin 64= clock;
4) Pin 50= FSK input of the receiver (Pin 39 on the auxiliary PCB);
5) Pin 37= data output for FSK demodulator (Pin 37 of the connector).

Main connector of the auxiliary PCB

Moreover, some pins have been connected to some LEDs in order to have a debug.

Regarding the DAC converter, note that, in order to reduce the voltage value of analog voltage to 05V level for the input of the demodulator, the most significant bit (Pin54 on the auxiliary board) has
been set to zero. Alternatively you can use a resistive divider on the input of the receiver.
Also remember to put to zero the CS and CE signals for a correct operation of the DAC converter.
1) Please, check the correct operation of the FSK transmitter, using the oscilloscope probe on
the BNC output of the DAC. Measure the corresponding amplitude.
2) Make a BNC cable that connects the DAC output to the input of the demodulator (Pin 39 on
the auxiliary PCB).
3) Send through the switch 5, the bit "1" or a "0" and check that the demodulator return the
same bits.