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A Quasi-Switched-Capacitor Resonant Converter

Article in IEEE Transactions on Power Electronics January 2015
DOI: 10.1109/TPEL.2015.2490554

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2490554, IEEE Transactions on Power Electronics

A Quasi-Switched-Capacitor Resonant
Converter
Xuan Zhang, Student Member, IEEE, Chengcheng Yao, Student Member,
and Jin Wang, Member, IEEE
The Ohio State University, Columbus, Ohio, U.S.A

Abstract A Quasi-Switched-Capacitor (QSC) resonant converter is proposed for isolated

dc/dc conversion in off-line power supply application. Similar to the 2 resonant converter, the
proposed converter is operated most efficiently at fixed switching frequency and duty ratio, and it
features trapezoidal voltage waveforms on all switches. Full soft switching combining ZCS, ZVS
on and off is achieved within a wide load range, and therefore the switching loss is minimized. In
addition, compared to half/full-bridge converters (e.g. the LLC resonant converter and the dualactive-bridge converter), the proposed converter reduces the voltage stress on primary-side
switches to 2/3 of the input voltage, and thus enables more choices of low-voltage devices, which
are more efficient because of better figure of merit. Furthermore, the proposed converter reduces
the transformer turns ratio by 2/3, and thus enables less number of turns of the winding, lower
winding loss and lower transformer leakage inductance, making it suitable for high-frequency
operation. A 90-W, 88-V/19-V, 700-kHz prototype is built with 100-V eGaN FETs. The
transformer design and PCB layout are presented to minimize the transformer leakage inductance
and stray inductance. The prototype achieved a power density of 172 W/inch3, and a flat efficiency
curve with a peak value of 96 %.
Index Terms dc/dc converter, off-line power supply, Quasi-Switched-Capacitor circuit,
reduced switch voltage stress, reduced transformer turns ratio, ZVS on and off.
Contact Author Information:
Xuan Zhang
The Ohio State University
Department of Electrical and Computer Engineering
Phone: 614-795-5300
Email: zhang.1973@osu.edu
1

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I.

INTRODUCTION

Consumer electronics (CE) such as laptops, smart-phones, and smart-pads are indispensable
information-technology tools in todays world. CE products require an external off-line ac/dc
power adapter to power up the device or charge its internal battery with a universal line input. The
outlook for the external ac-dc power supply market is expected to remain strong over the next
several years increasing from $10.7 billion in 2014 to $14.9 billion in 2019, a compounded annual
growth rate (CAGR) of 6.9% [1]. In this market, there exists ever-increasing demands for high
power-density and highly energy efficient power supplies. Currently, available commercial
products are based on the Silicon (Si) devices. For example, the state-of-art, Si-based,
commercially available 90-W ac/dc power adapter product from AcBel is in the size of 5.27 inch3,
and the measured peak efficiency is 92 %. However, the growing consensus in the power
electronics community is that Si devices cannot meet the needs of the future of power electronics
[2-6]. This is driven by market demands for further improvements in efficiency, reduction of
physical sizes, and an increase in maximum operating temperatures. The Wide Bandgap (WBG)
power devices, such as the Gallium Nitride (GaN) devices, are posed to satisfy these emerging
market needs. The 3X wider bandgap of the GaN devices enable them to operate under greater
voltage stress per channel length, at higher temperatures, while switching at faster speeds and
causing lower power loss. All of these attributes indicate that by using GaN devices, smaller and
more efficient ac/dc power adapters can be realized. For example, FINsix has announced a stateof-art, GaN-based, pre-order available 65-W ac/dc power adapter Dart, measuring 2.5 inch3 and
weighing 60 gram, which is 60~75% smaller than its conventional counterparts [1, 7, 8].
To maximize the benefits of GaN devices, low-voltage rating of the devices is preferred. This
is because low-voltage rated devices are more efficient, as they have better figure of merits which
2

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is the product of the on-resistance and the total gate charge [9, 10]. Currently, most power adapter
products are based on traditional circuit topologies, including: 1) single-stage Flyback PFC circuit
[11-13], 2) two-stage topology composed of a Boost-PFC circuit and a Half-bridge LLC resonant
converter [14-17], and 3) topologies based on 2 resonant converter [18-21]. All these topologies
impose high voltage stress (dc-link voltage) on switches, and thus require high-voltage (e.g. 600V) rated devices, which is neither energy efficient nor power-density optimized. For the two-stage
topology, Buck-PFC circuit can be applied to lower the dc-link voltage to 80~90 Vdc, so as to
reduce the voltage stress on switches in the downstream dc/dc stage [22, 23]. It is demoed that a
Buck-PFC based 90-W ac/dc power adapter achieved the size of 5.93 inch3 and the efficiency of
92.5 % [22].
For the downstream isolated dc/dc stage, to enable the use of low-voltage GaN devices, a
Quasi-Switched-Capacitor (QSC) dc/ac circuit is proposed in [24]. Comparing to half/full-bridge
circuits, it reduces the voltage stress on switches by 1/3, and reduces the transformer turns ratio by
2/3. Based on it, a QSC PWM converter is derived in [26]. However, even though with ZVS on,
the turn-on loss of the converter could be minimized, the turn-off loss still limits the capability of
the converter to operate at higher switching frequency.
In this paper, a QSC resonant converter is proposed to address the aforesaid challenges [25-27].
It serves as an isolated dc/dc converter, downstream to a Buck-PFC circuit, in off-line power
adaptor application. The converter is based on the QSC dc/ac circuit that provides reduced voltage
stress on the switches and transformer. It also features full soft switching combining both ZCS and
ZVS within a wide load range, and it is operated most efficiently at fixed switching frequency and
duty ratio. A 90-W, 88-V/19-V, 700-kHz prototype is built with 100-V eGaN FETs. The
transformer and PCB layout are designed to minimize the leakage inductance and loop stray
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inductance. The circuit design and control method yield high power density as well as high
efficiency across a wide load range.
This paper is divided into five sections. Section II presents the descriptions and operation
principles of the QSC resonant converter. Section III presents the prototype design, including the
transformer design and PCB layout. Section IV presents the simulation results and experimental
results. Section V concludes the paper.

II.

CIRCUIT DESCRIPTIONS AND OPERATION PRINCIPLES

A. Circuit Descriptions and Operation Principles

The proposed QSC resonant converter is shown in Fig. 1. The operation waveforms are shown
in Fig. 2. As shown in the operation waveforms, the converter has the following features:
1) Similar to the 2 resonant converter, the voltage waveforms of all switches in the QSC
resonant converter are trapezoidal, featuring ZVS on and off [28]. However, as the 2
resonant converter imposes the voltage stress on switch 2X higher than the input voltage,
the QSC resonant converter reduces the voltage stress on HV-side switches to 2/3 input
voltage, and thus enables more choices of low-voltage GaN devices.
2) Compared to half/full-bridge converters (e.g. the LLC resonant converter and the dualactive-bridge converter), the transformer turns ratio of the QSC resonant converter is
reduced by 2/3, which enables less number of turns of the winding, lower winding loss and
lower transformer leakage inductance.

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3) As discussed in details in the following content, by utilizing two types of circuit resonance,
the converter achieves full soft switching combining both ZCS and ZVS within a wide load
range, and therefore significantly reduces the switching loss.

Coss1

Coss1

C
3

Coss2

Lm

S2

C4

S2

Vin

Lo
+

C
2

S1

S4

N:1:1

a Ls

Co

R Vout

S3
n

Coss1

Coss2

Fig. 1. Equivalent circuit of the QSC resonant converter. C2, C3 and C4 are the switched capacitors; Ls and Lm are the
transformer leakage inductance and magnetizing inductance; and Lo and Co compose the output filter. To analyze all
switching transients within a switching cycle, the output capacitance of all the switches (Coss1 and Coss2) must be taken
into consideration.
Tsw/2
Ton_sw
S1&S3

Tsw/2
Ton_sw

ON

ON
Tdb_min

S2&S4

Tdb_min
ON
Vin/3

t
t

Van

-Vin/3

ILm

Idc_Lm
t

ILs

Idc_Ls

2Vin/3
VDS(S1)
0

VDS(S2)
0 t0

t
2Vin/3
t1

t2 t3 t4

t5

t6 t7 t8

Fig. 2. Operation waveforms of the QSC resonant converter. Two types of resonance are utilized in operation, which
exists in the active switching modes and dead-time modes respectively. As results, ZCS on and near ZCS off are
achieved during the active switching modes, while ZVS on and off are achieved during the dead-time modes.

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In steady state, the converter has 8 switching modes within a switching cycle (Tsw), as shown in
Fig. 3 (a)-(h). In the figures, the red loops signify the current paths of which the resonance is
determined by Ls; the blue loops signify the current paths of which the resonance is dominated by
Lm.
Coss1

Coss1

S2

Coss2

C4

S1

IR

S2

Lm

C
2

Vin

S3

S2

Coss2

Coss1

C3

Lm

(a)

Vin

C
3

Lm

S2

Coss2

Coss1

C4

S2

S1

IR

C3

C2

Lm

Vin
S3

S2

Coss2

Coss1

n
Coss1

Coss1

Coss1

Coss2

C4

S1

IR

C3

Lm

Coss1

Coss1

Coss1

Coss2

C3

Lm

S2

C4

S2

S1

IR
Vin

(g)

S4

Ls
C3

C2

S3

S2

Coss2

Coss1

Lm

Coss2

C4

IR

S3
n

n
Coss1

IR

S2

C
2

Coss2

(f)

Coss1

S4

Ls

Vin

S1

Coss1

Coss2

(e)

C4

n
Coss1

Coss2

S3

S2

S3

S2

S2

C
2

Vin

Lm

S4

Ls

S3

Coss1

Vin

+
C3

IR

Coss2

S4

Ls

S2

C
2

(d)

Coss1

S1

C4

Coss2

(c)

S4

Ls

C
2

IR

Coss2

(b)

S2

S1

Coss1

S4

Ls

Coss1

Coss1

C4

Coss2

S3

n
Coss1

S4

Ls

Vin

C3

C
2

Coss1
a

S2

S1

Coss1

S4

Ls

(h)

Coss2

Fig. 3. The switching-mode diagrams of the continous operation in a switching cycle, including: (a) Mode 1: current
path between t0 - t1, (b) Mode 2: current path between t1 - t2, (c) Mode 3: current path between t2 - t3, (d) Mode 4:
current path between t3 - t4, (e) Mode 5: current path between t4 - t5, (f) Mode 6: current path between t5 - t6, (g) Mode
7: current path between t6 t7, (h) Mode 8: current path between t7 t8 (one switching cycle completes).

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There are two types of resonance identified in operation. The first type causes resonant switching
currents. It results in ZCS on and near ZCS off, and therefore significantly reduces the switching
losses. Such resonance exists between the C2, C3, C4, and Ls, and it happens in the active switching
modes, including the Mode 1, 2, 5, and 6. The equivalent resonance path for Mode 1 and 2 are
shown in Fig. 4 (a), and the equivalent resonance path for Mode 5 and 6 are shown in Fig. 4 (b).

N2
sC 4

sL S
N2
sC 4

VS2
s

VS1
s

RS

1
2sC 2

sL S

RS

2
sC 2

(b)

(a)

Fig. 4. The equivalent resonant paths after Laplace transformation to denote the first type of resonance happening
during the active switching modes, including (a) Mode 1 and 2, and (b) Mode 5 and 6. Such resonance causes resonant
swithcing currents and thus results in ZCS on and near ZCS off for all the switches.

The second type of resonance exists between the Coss1, Coss2, and Lm. It happens in the dead-time
switching modes, including the Mode 3 and 7. The equivalent resonance path is shown in Fig. 5.
This type of resonance transfers the energy stored in the output capacitance of one switch to its
complementary switch, recycling that energy which otherwise would be lost in the ZCS operation.
This resonance leads to ZVS on and off of the switches, which furthermore improves the efficiency.
It also helps slow down the dv/dt of the switches, eliminate the voltage overshoot, and reduce the
EMI noises.

Lm

3COSS1

2COSS2
N2

Fig. 5. The equivalent resonant path after Laplace transformation to denote the second type of resonance during the
dead-time switching modes, including Mode 3 and 7. Such resonnace recycles the energy in switch output capacitance
which otherwise would be lost in the ZCS operation, and thus results in ZVS on and off for all the switches.

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The converter is operated most efficiently when both aforesaid types of resonance are
implemented. This requires the right timing of switching, which leads us to derive the optimal duty
ratio and switching frequency.

B. Optimal Duty Ratio and Switching Frequency

To find the optimal duty ratio and switching frequency, the optimal duration of the active
switching modes and the dead-time switching modes must be derived respectively, and the
derivation is presented as follows. As shown in Fig. 4, in the equivalent resonant paths for the active
switching modes, Lm is ignored since it is much larger than Ls. Despite the initial voltages on C2
and C4, the current ILs equals to 0 at both t0 and t4, so a lumped voltage source represents all the
initials conditions for each case. In Mode 5 and 6 where S2 is turned on, the sum of the voltage drop
across the Ls (VLs) and the loop parasitic resistance Rs (VRs) is
V Ls ( s ) + V Rs ( s ) = V S 2

sL s C 2 C 4 + R s C 2 C 4
s L s C 2 C 4 + sR s C 2 C 4 + C 2 + 0.5C 4
2

(1)

The loop current resonates to 0 when the derivative of VLs(t)+VRs(t) reaches 0, so the
VLs(t)+VRs(t) is derived with Inverse Laplace Transformation based on (1) as

at
cos bt +
V Ls (t ) + V Rs (t ) = L1 {V Ls ( s ) + V Rs ( s )} = V S 2 e

a at

e sin bt ,
b

a = Rs 2 Ls
.
b 2 = (C 2 + 0.5C 4 ) Ls C 2 C 4 Rs 2 4 Ls 2

where

According to (2), the derivative of the VLs(t)+VRs(t) is derived as

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(2)

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d [V Ls (t ) + V Rs (t )]
a2
= V S 2 b +

dt
b

at
e sin bt .

(3)

By equating (3) with 0, the optimal duration of the active modes (Ton_sw) is derived as
Ton _ sw =

2
.
b

(4)

The minimum deadtime (Tdb_min) is required to complete Mode 3 and Mode 7. To simplify the
analysis, the current of Lm is assumed to have a triangular waveform, and the dc-offset current is
ignored since it is very small compared to the ripple current. Then, the following equations are
derived

I L _ pk

Ton _ sw + Tdb _ min

V
= in
3L m
2

, Tdb _ min =

2Vin C oss1 +

4Vout C oss 2
N

I L _ pk

(5)

Based on (5), the Tdb_min can be derived as

Tdb _ min

2V C

12VinCoss1 + out oss 2 Lm

2
N
+ Ton _ sw Ton _ sw .

=
Vin
4
2

(6)

Based on (4) and (6), the optimal duty ratio (Dsw) and optimal switching frequency (fsw) can be
derived as
Dsw =

Ton _ sw
2(Ton _ sw + Tdb _ min )

, f sw =

1
.
2(Ton _ sw + Tdb _ min )

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(7)

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III.

PROTOTYPE DESIGN

To verify the circuit analysis, a 90-W, 88-V/19-V QSC resonant converter prototype is built,
using 100-V EPC eGaN FETs (EPC2016) for all switches. High switching frequency is preferred
to shrink the passive components and increase power density, so high resonant frequency of the
circuit is required. To ensure underdamped switching currents in the ZCS operation during the
active switching modes, in practical design, it requires: 1) low transformer leakage inductance,
and 2) minimized stray inductance in power-loop layout.
A. Planar Transformer Design
In order to reduce the transformer leakage inductance, a center-tapped planar transformer with
an interleaving winding structure is designed, as shown in Fig. 6 (b). Aiming initially at a switching
frequency at 1 MHz, the Ferrite material 3F45 from Ferroxcube is chosen for the magnetic core.
Based on the material permeability and voltage stress on winding, the transformer turns ratio is
designed as N=3:2:2. As discussed in [29], the leakage inductance can be estimated as:
Lleak = 0

l w h1 + h2

+ h ,
4
bw 2

(8)

where lw is the length of each turn, bw is the width of each turn, h1 and h2 are the lay-thickness
of the primary and the secondary respectively, and h is the height of insulator layer.
As (8) implies, in order to reduce the transformer leakage inductance, the winding traces are
preferred to be designed with shorter length, larger width, and smaller thickness per turn.
Meanwhile, the insulation layer is preferred to have smaller thickness. As shown in Fig. 6 (a), an
ideal model without termination is analyzed first in ANSYS Maxwell 3D.The simulation results
are: Lm=19 H, Ls=12 nH.
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Ipri
Isec1

pri/2

(reserved for Isec2)

Isec1
Ipri/2

(reserved for Isec2)

Ipri

(a)

(b)

Fig. 6. (a) ANSYS Maxwell 3D simulation model of the ideal planar transformer without termination and (b) the
interleaving winding structure.

Then, a detailed transformer model with vias connecting different layers, as shown in Fig. 7 (a),
is built in ANSYS Q3D Extractor for termination inductance analysis. Two parts of stray
inductance contribute to the total resonance inductance, including the stray inductance of the vias
connecting different layers of the winding, and the resulted extra winding strip between the vias.
These inductance are estimated respectively. The stray inductance of the extra winding strip can
be estimated by the following equation [30]
Lstrip = 0.0002 L[ln

2L
W +H
+ 0.2235
+ 0.5] H
W +H
L

(9)

, where L is the length of the strip, W is the width of the strip, and H is the thickness of the strip.
For example, the estimated stray inductance of the strip highlighted in purple in Fig. 7 (a) is 6.3
nH.
In addition, to reduce the stray inductance caused by the vias connecting different layers of the
transformer windings, an interleaving structure of the vias is applied, as shown in Fig. 7 (b). For
each transformer winding, at places where different layers of the winding connect, interleaving
rows of vias carrying opposite currents are placed with enough clearance distance for breakdown
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prevention. The paralleled vias in a row provide reduced resistance and reduced conduction loss.
The interleaved rows of vias allow for reduced eddy and proximity effects, reducing the ac
conduction losses. The stray inductance of the interleaving vias can be estimated by the following
equation [31]
Lvia =

0 3 s 1
h[ ln + ln 2] H
2 2 r 2

(10)

where s is the distance between 2 adjacent rows of vias, r is the via-hole radius, and h is the via
length. For example, the estimated stray inductance of the vias shown in Fig. 7 (b) is 0.6 nH.

stray inductance of
this strip: 6.3 nH

(a)

(b)

Fig. 7. (a) Detailed simulation model of the planar transformer built in ANSYS Q3D Extractor for termination
inductance analysis, (b) Interleaving vias of the palanr transformer.

B. PCB Layout
An 8-layer PCB is designed, where the power-loop traces and the planar transformer windings
are integrated. The spacing between the PCB layers need to be large enough to meet the isolation
requirement in the industrial safety standards. However, smaller spacing is preferred in order to
reduce both the transformer leakage inductance and the stray inductance in layout. To meet the
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safety standards such as IEC60950, the spacing is required to be at least 400 m. However,
according to the standard IPC2221, the electric strength of the FR4 material is 39.4 kV/mm, so a
4-mil spacing is selected in this preliminary design, which is enough to withstand 4-kV isolation.
The stray inductance in the power loop is also part of the resonance inductance. It slows down
the dV/dt of the switches, causing more switching loss [32, 33], and thus needs to be minimized.
In the PCB layout, the idea of the optimal layout for reduced stray inductance and resistance, as
proposed in [33], is followed. Take the layout of S2, C2 and C3 for example (shown in Fig. 8): 1)
S2, C2 and C3 are all placed on the top layer, with minimal spacing in between; 2) the transformer
primary-side winding starts from the top layer and ends on the 2nd layer; 3) the switch currents
flow to the transformer on the top layer, and returns on the 2nd layer. The current return path is
located directly underneath the top layers power loop, allowing for the smallest physical loop size
combined with field self-cancellation.

Transformer
C2
S2

Gate
Driver

S2
C3

On the top layer

On the 2nd layer

Fig. 8. Optimal PCB layout of the switched capacitors and switches for reduced high frequency parasitic inductance
and resistance in the power loop of the converter.

C. Output Rectifiers
The switches S3 and S4 operate as synchronous rectifiers (SR) to reduce the conduction loss.
However, due to the high source-drain forward voltage of eGaN FETs, the propagation delay before
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turning on the device would lead to high conduction loss, which can be minimized by Schottky
diodes in parallel [34]. In the design, S3 and S4 are paralleled with Si Schottky Diode PDS760,
which are selected for its low forward voltage.
The prototype of the QSC resonant converter is shown in Fig. 9. The circuit parameters are
listed in Table I. It includes the main circuit and gate-drive circuits, but doesnt include the
controller, the isolated power supplies for the gate-drive circuits, and the output filter. The power

47

mm

24

mm

density of this preliminary prototype has reached 172 W/inch3.

Height:
7.6 mm

Fig. 9. The 90-W, 88-V/19-V, 700-kHz QSC resonant converter prototype.

TABLE I.
Item
Vin/Vout
fsw
Dsw
C2, C3, C4
Ls, Lm

SPECIFICATIONS OF THE SIMULATION MODEL AND EXPERIMENTAL PROTOTYPE

Descriptions
Input voltage/Output voltage
Optimal switching frequency
Optimal duty ratio
Switched capacitors
Planar transformer (integrated
in the PCB)

S1~S4

Switches

Rs

Power-loop PCB series stray

resistance

Specifications
88 V/19 V
700 kHz
0.32
2.2 F, ceramic 100 V
Ferrite material 3F45 from Ferroxcube,
Lm=16 H, Ls=25 nH , N=3:2:2,
eGaN FETs EPC2016 (100 V, 11 A), S3 and S4
are paralleled with a schottky diode PDS760
0.1 @ 1 MHz

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IV.

SIMULATIONAL AND EXPERIMENTAL VERIFIVATIONS

Two experiments are conducted to compare the operations with and without optimized duty
ratio and switching frequency. The first experiment is conducted under the conditions: Vin=88 V,
Po=90 W, Dsw=0.47, and fsw=900 kHz. Both the simulation and experimental waveforms are shown
in Fig. 10. Since the switch currents and transformer current couldnt be monitored in the
prototype, only the voltage waveforms are recorded.

200 ns/div
Vds_S2
(25V/div)

Vds_S1
(25V/div)

Van
(25V/div)
Vds_S3
(25V/div)

(a)
(b)
Fig. 10. (a) The simulation waveforms and (b) the experimental waveforms of the voltage across the switches (Vds_S1,
Vds_S2, Vds_S3), the transformer primary-side winding voltage (Van), the transformer primary-side winding current (I_Ls),
and transformer primary-side-referred magnetizing inductor current (I_Lm). All waveforms are recorded in the
operation condition: Vin=88 V, Po=90 W, Dsw=0.47, and fsw=900 kHz. Based on the analysis, in this case the Dsw and
fsw are not optimized, so ZVS on and off are not achieved.

Following that, the second experiment is conducted, under the test conditions: Vin=88 V, Po=90
W, Dsw=0.32, and fsw=700 kHz. Both the simulation and experimental waveforms are shown in Fig.
11.

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Vds_S2
(25V/div)

Van
(25V/div)

200 ns/div
Vds_S1
(25V/div)

Vds_S3
(25V/div)

(a)
(b)
Fig. 11. (a) The simulation waveforms and (b) the experimental waveforms of the voltage across the switches (Vds_S1,
Vds_S2, Vds_S3), the transformer primary-side winding voltage (Van), the transformer primary-side winding current (I_Ls),
and transformer primary-side-referred magnetizing inductor current (I_Lm). All waveforms are recorded in the
operation condition: Vin=88 V, Po=90 W, Dsw=0.32, and fsw=700 kHz. Based on the analysis, in this case the Dsw and
fsw are optimized, so ZVS on and off are achieved.

As shown in the Fig. 10 and Fig. 11: 1) the voltage stress on S1 and S2 are reduced to 2Vin/3, and
the voltage stress on the transformer is reduced to Vin/3 on the primary side; 2) ZVS on and off are
not achieved in Fig. 10, but achieved in Fig 11. With optimized Dsw and fsw applied, the switching
loss is minimized; 3) In Fig. 10, the voltage overshoot and ringing on the switches at turning off are
significant, which increases the risk of breakdown failure and the EMI noise. However, such ringing
and overshoots are eliminated when optimized Dsw and fsw are applied, as shown in Fig 11, which
indicates more reliable operation and reduced EMI noise.
The converter power loss and efficiency curves are shown in Fig. 12. It is shown that the power
loss and efficiency are significantly improved with optimized Dsw and fsw applied, as results a flat
efficiency curve with a peak value at 96 % is achieved.

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100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66

10

20

30

40 50 60 70
Output Power (W)

80

90

100 110

12
11
10
9
8
7
6
5
4
3
2
1
0

Power Loss (W)

Efficiency (%)

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Efficiency with optimized duty ratio and switching frequency

Efficiency with non-optimized duty ratio and switching frequency
Power loss with optimized duty ratio and switching frequency
Power loss with non-optimized duty ratio and switching frequency
Fig. 12. Power loss and efficiency reuslts of the prototype, in comparison between the operations with and witout
optimized Dsw and fsw.

V.

CONCLUSIONS

The QSC resonant converter proposed here offers high power density and high efficiency for
isolated dc/dc conversion in off-line power adaptor application. Similar to the 2 resonant
converter, the converter is operated most efficiently at fixed switching frequency and duty ratio
applied, and it features trapezoidal voltage waveforms on all switches. Full soft switching is
achieved combining ZCS on, near ZCS off, ZVS on, and ZVS off within a wide load range, so the
switching loss is minimized. In addition, compared to half/full-bridge converters (e.g. the LLC
converter and dual-active-bridge converter), the proposed converter reduces the voltage stress on
primary-side switches to 2/3 of the input voltage, and thus enables more choices of low-voltage
GaN devices, which are more efficient because of their better figure of merit. Furthermore, the
converter reduce transformer turns ratio by 2/3, and thus enables less number of turns of the
winding, lower winding loss and lower transformer leakage inductance, making it suitable for
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high-frequency operation. A 90-W, 88-V/19-V, 700-kHz prototype is built with 100-V eGaN
FETs. The transformer design and PCB layout are presented to minimize the transformer leakage
inductance and stray inductance. The prototype achieved a power density of 172 W/inch3, and a
flat efficiency curve with a peak value of 96 %.
The proposed QSC resonant converter is not limited only to low-power applications, but also
has the scalability to be applied in high-voltage, high-power applications. The reduced voltage
stress on switches and transformer are of particular interest for high voltage converters such as the
solid-state transformers, where challenges exist in the development and application of high-voltage
(>10 kV) SiC power devices and also the insulation design of the high-voltage transformer. Efforts
should be made thus in such directions to explore and expand the applications of the proposed
converter.
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0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2015.2490554, IEEE Transactions on Power Electronics

[31] H. W. Johnson and M. Graham, High Speed Signal Propagation: Advanced Black Magic, 1st Edition, Prentice
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Xuan Zhang (S11) received his B.S. and M.S. degrees in Electrical
Engineering from Huazhong University of Science and Technology, Wuhan,
China, in 2008 and 2011. He is currently working towards his Ph.D. degree in
Electrical Engineering at The Ohio State University in Columbus, Ohio. He
was an intern at the GE Global Research, Shanghai, China, from February to
June 2011, and an intern at the ABB Corporate Research Center, USA, from
June to August 2014. His current research interests include topology and control of PWM and
resonant dc/dc converters, evaluation and application of wide-bandgap (WBG) power devices,
WBG gate drive design, and transformer-less galvanic isolation.

Chengcheng Yao (S11) received his B.S. degree in Automation from

Changsha University of Science and Technology, Changsha, China, in 2011.
He is currently working towards his Ph.D. degree in Electrical Engineering at
The Ohio State University in Columbus, Ohio. From February to July 2011,
he was an intern at the R&D Center of SANY Corporation, Changsha,
China. From May to August 2013, he worked as an intern at the Research and
Innovation Center of Ford Motor Company, Dearborn, Michigan. His current research interests
include electrometric interference, power module packaging and application of wide bandgap
power devices.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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Jin Wang (S02M05) received a B.S. degree from Xian Jiaotong

University, in 1998, an M.S. degree from Wuhan University, in 2001, and a
Ph.D. from Michigan State University, East Lansing, in 2005, all in electrical
engineering.
From Sept., 2005 to Aug. 2007, he worked at the Ford Motor Company
as a Core Power Electronics Engineer and contributed to the traction drive
design of the Ford Fusion Hybrid. He joined the Department of Electrical
and Computer Engineering at The Ohio State University as an assistant professor in September
2007 and was promoted to associate professor in September 2013. His research interests include
wide bandgap power devices and their applications, high-voltage and high-power
converter/inverters, integration of renewable energy sources, and electrification of transportation.
Dr. Wang received multiple teaching and research awards including the IEEE Power
Electronics Society Richard M. Bass Young Engineer Award and the National Science
Foundations CAREER Award, both in 2011; Ralph L. Boyer Award for Excellence in
Undergraduate Teaching Innovation from the College of Engineering at The Ohio State University
in 2012, and the Lumley Research Award of the College of Engineering at The Ohio State
University in 2013. Dr. Wang has over 100 peer-reviewed journal and conference publications
and three patents. Dr. Wang had been an Associate Editor for IEEE Transactions on Industry
Applications from 2008 to 2014. He initiated and served as the General Chair for the 1st IEEE
Workshop on Wide Bandgap Power Devices and Applications in 2013. Currently, Dr. Wang
serves as an Associate Editor for IEEE Transactions on Power Electronics and IEEE Journal of
Emerging and Selected Topics in Power Electronics (J-ESTPE).

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