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bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
3 Description
PACKAGE
bq77904
TSSOP (20)
bq77905
6.50 4.40 mm
Simplified Schematic
2 Applications
PACK+
VDD
VTB
VC5
TS
bq77094/5
LD
Vss
SRP
SRN
DSG
CHGU
CTRD
CTRC
VDD
VTB
VC5
TS
bq77094/5
LD
Vss
SRP
SRN
DSG
CHG
PACK-
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
1
1
1
2
3
4
5
38
38
38
38
38
38
4 Revision History
Changes from Original (June 2016) to Revision A
Page
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5 Device Comparison
DEVICE
NUMBER OF
CELLS
bq77904
3, 4
bq77905
3, 4, 5
PROTECTIONS
TYPICAL NORMAL
MODE CURRENT (A)
PACKAGE
20-TSSOP
Unless specified, the devices in Table 1 and Table 2 are default with state comparator enabled with 2 mV
threshold. Filtered fault detection is used by default. Contact Texas Instruments for new configuration option or
device in preview.
Table 1. bq77904 Device Configuration
(1)
(2)
0
(disable)
Delay (s)
200
Threshold (mV)
Delay (ms)
2800
Current Fault
Recovery
SCD
Threshold (mV)
Hyst(mV)
100
OCD2
Delay (ms)
Delay(s)
OCD1
Threshold (mV)
Thresh (mV)
4225
Current(nA)
Hyst(mV)
OW
Delay(s)
Part Number
bq7790400 (2)
UV
Threshold(mV)
OV
Method
40
1420
80
700
160
Load Removal
OTD
OTC
UTD
OTC
70
50
-20
-5
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10k resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
Product Preview
Current(nA)
Threshold (mV)
Delay (ms)
Threshold (mV)
Delay (ms)
Threshold (mV)
Delay (s)
Hyst(mV)
SCD
Delay(s)
OCD2
Thresh (mV)
OCD1
Hyst(mV)
OW
Delay(s)
UV
Threshold(mV)
OV
Method
OTD
OTC
UTD
OTC
bq7790500
4200
0.5
100
2600
400
100
30
1420
50
700
120
Load Removal
+ Delay
70
50
-20
bq7790501 (2)
4200
0.5
100
2600
400
100
30
1420
50
700
120
Load Removal
+ Delay
70
50
-20
(2)
4250
200
2700
200
100
85
700
120
350
240
Load Removal
70
50
-20
-5
bq7790503 (2)
4200
100
2700
400
100
80
1420
160
350
320
Load Removal
+ Delay
70
50
-10
-5
bq7790504 (2)
4250
0.5
200
2700
200
100
80
350
160
200
Load Removal
+ Delay
70
50
-10
-5
Part Number
bq7790502
(1)
(2)
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10k resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
Product Preview
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
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VDD
20
DVSS
AVDD
19
CTRD
VC5
18
CTRC
VC4
17
CCFG
VC3
16
VTB
VC2
15
TS
VC1
14
LD
AVSS
13
CHG
SRP
12
CHGU
SRN
10
11
DSG
Not to scale
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AVDD
AVSS
Analog ground
CCFG
17
CHG
13
CHG FET driver, use on a single device or on the bottom device of a stack
configuration
CHGU
12
CHG FET signal, use for upper device of a stack configuration to feed the CHG signal
to the CTRC pin of the lower device
CTRC
18
CTRD
19
DSG
11
DVSS
20
Digital ground
LD
14
SRN
10
SRP
TS
15
Thermistor measurement input. Connect a 10k resistor to AVSS pin if the function is
not used
VC1
VC2
VC3
VC4
VC5
VDD
Supply voltage
VTB
16
(1)
bq77904, bq77905
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). All values are referenced to VSS unless otherwise noted.
(1)
Input voltage
MAX
UNIT
36
LD
30
20
0.3
3.6
DSG, CHGU
0.3
20
CHG
30
20
VTB
0.3
VO
II
Input current
LD, CHG
II
Input current
IO
IO
3.6
500
CHGU, DSG
mA
Output current
CHG
mA
Output current
CHGU, DSG
mA
150
MIN
0.3
65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
V(ESD)
(1)
(2)
Electrostatic discharge
1000
250
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VI
TSTG
MAX
25
CTRD, CTRC
(VDD + 5)
AVDD
0.2
0.8
CCFG
SRN, SRP
VO
NOM
VDD
LD
16
TS
VTB
16
VTB, AVDD
40
85
UNIT
V
V
C
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
bq77904
bq77905
(1)
UNITS
PW (TSSOP)
16 PINS
JA
TBD
JCtop
TBD
JB
TBD
JT
TBD
JB
TBD
JCbot
TBD
(1)
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(POR)
POR threshold
VDD rising, 0 to 6 V
V(SHUT)
Shutdown threshold
VDD falling, 6 to 0 V
V(AVDD)
AVDD voltage
C(VDD) = 1 F
2
2.1
3.25
2.5
3.25
I(CFAULT)
State comparator on
IOFF
ILKG(OW_DIS)
ILKG(100nA)
ILKG(200nA)
ILKG(400nA)
12
0.5
100
100
nA
30
110
175
nA
95
210
315
nA
220
425
640
nA
PROTECTION ACCURACIES
VOV
Overvoltage programmable
threshold range
3000
4575
mV
VUV
Undervoltage programmable
threshold range
1200
3000
mV
10
10
mV
18
18
mV
TA = 0 to 60C
28
26
mV
TA = 40 to 85C
40
40
mV
V(VA)
VHYS(OV)
OV hysteresis programmable
threshold range
400
mV
VHYS(UV)
UV hysteresis programmable
threshold range
200
800
mV
VOTD
Overtemperature in discharge
programmable threshold
(1)
6
(1)
17.48
20.56
23.64
%VTB
15.49
18.22
20.95
%VTB
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VOTD(REC)
VOTC
VOTC(REC)
Overtemperature in charge
programmable threshold
Undertemperature in discharge
programmable threshold
VUTD(REC)
Undertemperature in discharge
recovery
VUTC(REC)
TYP
MAX
UNIT
22.20
26.12
30.04
%VTB
19.72
23.2
26.68
%VTB
28.00
32.94
37.88
%VTB
(1)
Overtemperature in charge
recovery
VUTD
VUTC
TEST CONDITIONS
Overtemperature in discharge
recovery
MIN
24.97
29.38
33.79
%VTB
34.82
40.97
47.12
%VTB
31.30
36.82
42.34
%VTB
(1)
74.07
87.14
100.21
%VTB
68.80
80.94
93.08
%VTB
68.80
80.94
93.08
%VTB
62.20
73.18
84.16
%VTB
65.64
77.22
88.80
%VTB
62.20
73.18
84.16
%VTB
58.48
68.80
79.12
%VTB
54.59
64.23
73.86
%VTB
Undertemperature in charge
programmable threshold
Undertemperature in Charge
Recovery
VOCD1
85
10
mV
VOCD2
20
170
mV
VSCD
40
340
mV
VCCAL
30%
30%
VCCAH
20%
20%
VOW
450
VOW(HYS)
500
550
100
mV
mV
11
VDD < 12 V, CL = 10 nF
VDD - 1
12
14
VDD
0.5
V(FETON)
CHG/CHGU/DSG on
V(FETOFF)
CHG/CHGU/DSG off
R(CHGOFF)
0.5
R(DSGOFF)
10
16
ICHG(CLAMP)
450
VCHG(CLAMP)
ICHG(CLAMP) = 300 A
18
20.5
tCHGON
50
150
tDSGON
75
tCHGOFF
15
30
tDSGOFF
15
16
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCTR2
VCTR(DIS)
VCTR(MAXV)
ICTR = 600nA
0.6
VDD + 2.2
2.04
VDD + 2.8
VDD + 4
VDD + 0.7
VDD + 5
tCTRDEG_ON)
(2)
ms
tCTRDEG_OFF
(2)
ms
Measured at SRP-SRN
-3
-1
mV
V(STATE_C1)
Measured at SRP-SRN
mV
1.2
ms
tSTATE
(2)
LD clamp voltage
I(LDCLAMP) = 300 A
ILD(CLAMP)
LD clamp current
V(LDCLAMP) = 18 V
16
VLDT
LD threshold
1.25
RLD(INT)
Measured to VSS
tLD_DEG
LD detection de-glitch
18
20.5
450
1.3
1.35
160
250
375
1.5
2.3
ms
10
%AVDD
100
%AVDD
45
%AVDD
CCFG PIN
V(CCFGL)
3 cell configuration
V(CCFGH)
4 cell configuration
65
V(CCFGHZ)
25
tCCFG_DEG
(2)
CCFG de-glitch
33
6
ms
8.5
50
10
tCTM_ENTRY
(3)
tCTM_DELAY
(3)
TA = 25C
200
ms
100
ms
tCTM_OC_REC
(2)
(3)
(3)
ms
bq77904, bq77905
www.ti.com
TYP
MAX
0.4
0.5
0.8
1 s Delay Option
0.8
1.4
2 s Delay Option
1.8
2.7
UNIT
tOVn_DELAY
tUVn_DELAY
4.5
5.2
1 s Delay Option
0.8
1.5
2 s Delay Option
1.8
2.7
4.5
5.5
9 s Delay Option
10.2
tOWn_DELAY
3.6
4.5
5.3
tOTC_DELAY
3.6
4.5
5.3
tUTC_DELAY
3.6
4.5
5.3
tOTD_DELAY
Overtemperature discharge
detection delay time
3.6
4.5
5.3
tUTD_DELAY
Undertemperature discharge
detection delay time
3.6
4.5
5.3
10 ms delay option
10
15
20 ms delay option
17
20
26
45 ms delay option
36
45
52
90 ms delay option
78
90
105
155
180
205
320
350
405
640
700
825
1290
1420
1620
10 ms delay option
10
15
20 ms delay option
17
20
26
45 ms delay option
36
45
52
90 ms delay option
78
90
105
155
180
205
320
350
405
tOCD1_DELAY
5 ms delay option
tOCD2_DELAY
tSCD_RELAY
tCD_REC
(1)
640
700
825
220
400
610
1 s option
0.8
1.4
9 s option
10.2
ms
ms
s
s
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
0.25
0.2
7
6.5
6
5.5
5
0.15
0.1
0.05
4.5
4
-40
-15
10
35
Temperature (qC)
60
0
-40
85
-15
60
85
D002
15
10
10
UV Error (mV)
5
0
-5
-10
0
-5
-10
-15
-15
-20
-40
-15
10
35
Temperature (qC)
60
-20
-40
85
-15
10
35
Temperature (qC)
D003
85
D004
0.1
60
4.0
2.5
0.05
3.5
0.0
0.2
-0.1
0.4
-0.15
-0.2
0.6
-0.25
Error (in mV)
Error (in %)
-0.3
-0.35
40
20
20
40
60
2.5
1.5
2.0
1
1.5
1.0
Error (in mV)
Error (in %)
1.0
40
20
20
40
60
0.5
0.0
80
Temperature (C)
C001
10
3.0
0.5
0.8
80
Temperature (C)
-0.05
OV Error (mV)
10
35
Temperature (qC)
D001
C002
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2.5
1.4
1.2
1.0
1.5
0.8
1
0.6
SCD Error(%)
0.4
0.5
Error (in mV)
Error (in %)
0
40
20
20
40
60
0.2
0.0
80
Temperature (C)
C003
11
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
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8 Detailed Description
8.1 Overview
The bq77904 and bq77905 families are full-feature stackable primary protectors for Li-ion/Li-polymer batteries.
The devices implement a suite of protections including:
Cell voltage: overvoltage, undervoltage
Current: Overcurrent discharge 1 and 2, short circuit discharge
Temperature: overtemperature and undertemperature in charge and discharge
PCB: cell open wire connection
FET body diode protection
Protection thresholds and delays are factory-programmed and available in a variety of configurations.
The bq77904 supports 3S-to-4S cell configuration and bq77905 supports 3S-to-5S cell configuration. Up to 4
devices can be stacked to support 6S cell configuration, providing protections up to 20S cell configuration.
The device has built-in CHG and DSG drivers for low-side N-channel FET protection, which automatically opens
up the CHG and/or DSG FETs after protection delay time when a fault is detected. A set of CHG/DSG override is
provided to allow disabling of CHG and/or DSG driver externally. Although host system can use this function to
disable the FETs control, the main usage of these pins is to channel down the FET control signal from the upper
device to the lower device in a cascading configuration in 6S battery pack.
8.1.1 Device Functionality Summary
For brevity, in this and subsequent sections, a number of abbreviations will be used to identify specific fault
conditions. The fault descriptor abbreviations and their meanings are defined in Table 3.
Table 3. Device Functionality Summary
FAULT DESCRIPTOR
OV
Overvoltage
0.5, 1, 2, 4.5 s
Hysteresis
UV
Undervoltage
1.2 V to 3 V
(100 mV step for < 2.5 V,
50 mV step for 2.5 V)
1, 2, 4.5, 9 s
Hysteresis, OR
Hysteresis + Load Removal
200, 400 mV
OW
4.5 s
OTD (1)
Overtemperature during
Discharge
65C or 70C
4.5 s
Hysteresis
10C
OTC (1)
Overtemperature during
Charge
45C or 50C
4.5 s
Hysteresis
10C
UTD (1)
Undertemperature during
Discharge
-20C or -10C
4.5 s
Hysteresis
10C
Undertemperature during
Charge
-5C or 0C
4.5s
Hysteresis
10C
Delay, OR
Delay + Load Removal , OR
Load Removal
1 s or 9 s
UTC
(1)
OCD1
Overcurrent1 during
Discharge
10 mV to 85 mV (5 mV step)
OCD2
Overcurrent1 during
Discharge
SCD
360 s
tCTRDEG_ON
tCTRDEG_OFF
tCTRDEG_ON
tCTRDEG_OFF
CTRC
CTRD
(1)
12
These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10-k resistor connected to VTB and TS. Actual
thresholds must be determined in mV. Refers to the over- and under-temperature mV threshold in the Electrical Characteristics table.
bq77904, bq77905
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VDD
CCFG
BG
REFERENCE
BIAS
CONFIG
LOGIC
AVDD
VDIG
REGULATOR
AND
SHUTDOWN
VTB
POR
TS
VC5
VC4
EEPROM
COMPARE
1
MUX
VC3
CTRC
VC2
STACK
INTERFACE
CTRD
VC1
EQUINOX
CONTROL
LOGIC (ECL)
OPEN
WIRE
CHG
CHG
DRIVER
CHGU
MUX
COMPARE
2
DSG
DRIVER
DSG
LOAD
DETECTION
LD
SRP
STATE
COMPARE
SRN
CLOCK
and
WDT
AVSS
DVSS
Copyright 2016, Texas Instruments Incorporated
13
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
Check OV VCELL1
Check OV VCELL2
Check OV VCELLn
Time to check
UV?
NO
Time to check
OT?
YES
Check UV VCELL1
NO
YES
Time to check
UT?
NO
YES
Check OT
Time to check
OW?
NO
YES
Check OW VCELLx,
x = x +1
Check UT
Check UV VCELL2
x starts
from 1
at POR
Reset x = 1, if x >
the highest cell
configured via
CCFG pin
Check UV VCELLn
Check SCD
Time to check
OCD1?
YES
Check
OCD1
NO
Time to check
OCD2?
NO
YES
Check
OCD2
14
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15
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SLUSCM3A JUNE 2016 REVISED JUNE 2016
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PACK+
bq77094/5
Load Detect
block
VLDT
LD
pin
RLD_INT
RLD
LOAD
16
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LOAD STATE
VLDT
Load present
Load removed
17
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SLUSCM3A JUNE 2016 REVISED JUNE 2016
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FAULT TRIGGER
CONDITION
CHG
DSG
RECOVERY METHOD
RECOVERY
DELAY
TRIGGER DELAY
CTRC disabled
OFF
tCTRDLY
CTRD disabled
OFF
tCTRDLY
OV
OFF
tOVn_DELAY
UV
OFF
tUVn_DELAY
OW
OFF
OFF
tOWn_DELAY
OCD1, OCD2,
SCD
OFF
OFF
OTC (1)
OFF
tOTC_DELAY
OTD (1)
OFF
OFF
tOTD_DELAY
UTC (1)
OFF
tUTC_DELAY
UTD (1)
OFF
OFF
tUTD_DELAY
(1)
tOCD1_DELAY,
tOCD2_DELAY,
tSCD_DELAY,
tCD_REC
TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected
thermistor resistance.
For bq77904 and bq77905 devices to prevent CHG FET damage, there are times when the CHG FET may be
enabled even though an OV, UTC, OTC or CTRC low event has occurred. See the State Comparator section for
details.
8.3.4 Configuration CRC Check And Comparator Built-In-Self-Test
To improve reliability, the device has built in CRC check for all the factory-programmable configuration, such as
the thresholds and delay time setting. When the device is set up in the factory, a corresponding CRC value is
also programmed to the memory. During normal operation, the device compares the configuration setting against
the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the CRC fault
counter. The digital reset forces the device to reload the configuration as an attempt to correct the configurations.
A correct CRC check reduces the CRC fault counter. Three CRC faults counts will turn off both the CHG and
DSG drivers. If FETs are opened due to CRC error, only a POR can recover the FET state and reset the CRC
fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, each comparator is checked for a period of time. If a fault is detected for the entire check period, the
particular comparator is considered at fault, and both the CHG and DSG FETs is turned off. The BIST continuous
to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver resumes
normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not specific
indication when a CRC or BIST error is detected besides turning off both CHG and DSG drivers. If there is no
voltage, current or temperature fault condition present, but CHG and DSG drivers remain off, it is possible either
CRC or BIST error is detected. User can POR the device to reset the device.
18
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Fault Threshold
Recovery Threshold
FAULT
FAULT
Sample
0 1 2 3 4 3 2 1 2 3 4 5 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 2 3 4 5 0 0 0
CHG
DSG
OFF
ON
ON
Normal
MODE
VSTATE_C Detection
ON
OFF
UV, CTRD
VSTATE_D Detection
OFF
ON
OFF
OFF
OFF
19
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SLUSCM3A JUNE 2016 REVISED JUNE 2016
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PACK IS CHARGING
PACK IS DISCHARGING
SRP - SRN
VSTATE_D
0V
VSTATE_C
DSGFET_OFF_SCD
DSGFET_OFF
DSGFET_OFF_UTD
DSGFET_OFF_OTD
OWn
CTRD
20
bq77904, bq77905
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Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG pin is designed to
switch on quickly and the target on resistance is about 2 k. When the pin is turned off, the CHG driver pin is
actively driven low and will together with PACK- voltage below ground.
The CHG FET may be turned on to protect the FET's body diode if the pack is discharging, even if a charging
inhibit fault condition is present. This is done via the state comparator. The State comparator (with VSTATE_D
threshold) remains on for the entire duration of a DSG fault with no CHG fault event.
If (SRP - SRN) > VSTATE_D, no discharge event is detected, the CHG FET output will remain OFF due to
the present of a CHG fault
If (SRP - SRN) VSTATE_D, a charge event is detected, the CHG FET output will turn ON for body diode
protection
The CHGFET_OFF signal is a result of the presence of any related faults as shown in Figure 15.
CHGFET_OFF_OVn
CHGFET_OFF_UTC
CHGFET_OFF_OTC
CHGFET_OFF_OCD1
CHGFET_OFF_OCD2
CHGFET_OFF
CHGFET_OFF_SCD
CHGFET_OFF_UTD
CHGFET_OFF_OTD
OWn
CTRC
21
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
ENABLED
VCTR2
VCTRDIS (max)
VDD
DISABLED
(FET OFF)
VCTRDIS (min)
VCTR1
ENABLED
VSS
CHG driver set by CTRC
DSG driver set by CTRD
CONFIGURATION
CONNECT TO
3 cells
AVSS
4 cells
AVDD
5 cells
Floating
The CCFG pin should be tied to the recommended net from Table 7. The device compares the CCFG input
voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is
for 5S, leave the CCFG pin floating. The internal pin bias is approximately 30% of the AVDD voltage for 5S
configuration. Note that the bq77904 should be configured in 5S mode as this results in a permanent UV fault.
8.3.11 Stacking Implementations
Higher than 5S cell packs may be supported by daisy-chaining multiple devices. Each device will ensure OV, UV,
OTC OTD, UTC, and UTD protections, of its directly monitored cells, while any fault conditions automatically
disable the global CHG and/or DSG FET driver. Note that upper devices do not provide OCD1, OCD2, or SCD
protections, as these are based on pack current. For bq77904 and bq77905 used on the upper stack, the SRP
and SRN pins should be shorted to prevent false detection.
Table 8. Stacking Implementation Configurations
CONFIGURATION
CHG PIN
CHGU PIN
Leave unconnected
Upper stack
Leave unconnected
bq77904, bq77905
www.ti.com
For the bottom device, the CHG pin should be used to drive the CHG FET and leave the CHGU pin
unconnected. For the upper device, the CHGU pin should be used to connect to lower devices CTRC pin
with a RCTRx and leave the CHG pin unconnected.
Connect the upper DSG pins with a RCTRx to the immediate lower device CTRD pin
All upper devices should have the SRP and SRN to its AVSS pin.
If load removal is not used for UV recovery, connect the upper device LD pin to its AVSS pin shown in
Figure 17 and Figure 18. Otherwise, refer to Figure 25 for proper LD connection.
PACK+
RVDD
CVDD
CVDD
RIN
CIN
RIN
DVSS
CTRD
VC5
CTRC
VC4
CCFG
VC3
CIN
RIN
VDD
AVDD
bq77905
VC2
RIN
CIN
RIN
RTS
TS
VC1
CIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
CIN
RVDD
CVDD
CVDD
RIN
CIN
RIN
RIN
RIN
RIN
VC3
CIN
VC2
VC1
CIN
CIN
bq77905
RCTRD
RCTRC
RTS_PU
VTB
RTS
TS
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS_DSG
RGS_CHG
RSNS
PACK-
23
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
PACK+
RVDD
CVDD
RIN
CVDD
CIN
RIN
CIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
RIN
CIN
bq77905
VC2
CIN
RIN
CIN
RTS
TS
VC1
RIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RVDD
CVDD
CVDD
RIN
CIN
RIN
DVSS
CTRD
VC5
CTRC
VC4
CCFG
VTB
VC3
CIN
RIN
VDD
AVDD
bq77905
VC2
CIN
RIN
RTS_PU
RTS
LD
AVSS
RIN
RCTRC
TS
VC1
CIN
RCTRD
CHG
SRP
CHGU
SRN
DSG
CIN
RVDD
CVDD
CVDD
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VTB
VC3
VC2
RIN
RIN
RIN
VC1
CIN
CIN
bq77905
RCTRD
RCTRC
RTS_PU
RTS
TS
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS
RGS
RSNS
PACK-
bq77904, bq77905
www.ti.com
25
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
CHG
RCHG
RDSG
RGS_DSG
RGS_CHG
Q2 Q1
RSNS
PACK-
Figure 19. Select Proper Gate Resistor For FET Rise And Fall Time
The CHG FET fall time is generally slower because it is connected to the PACK- terminal. The CHG driver will
pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or
Vgsth, the PACK- will start to fall below ground, the CHG signal will follow suit in order to turn off the CHG FET.
This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel, and
the value of gate-source resistor (RGS_CHG).
26
bq77904, bq77905
www.ti.com
Once the CFET gate voltage reach PACK-, PACKvoltage starts to fall below ground. The gate
voltage is then relying on RGS_CHG to fall with
PACK- to keep the CHG FET off.
CHG
LD
Q3
RDSG
RCHG
RLD
RGS_DSG
RGS_CHG
Q2
Q1
RSNS
PACK-
27
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
CHG
RDSG
RGS_CHG
(>=1M)
RGS_DSG
Q2
Q1
16V
RSNS
PACK-
LD
CHG
Q3
RCHG
(1M )
RDSG
RGS_DSG
Q2
Q1
RLD
RGS_CHG
(>=1M)
16V
RSNS
PACK-
28
bq77904, bq77905
www.ti.com
bq77094/5
Load Detect
block
VLDT
LD
pin
RLD_INT
FET driver
block
VFETON
LOAD
CHG
pin
RCHG
RLD
16V
CFET
RGS_CHG
29
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
Upper
device
Vss
pin
bq77094/5
LD
pin
Bottom
device
Vss
pin
RLD
PACKFigure 25. Simplified Circuit: LD Connection On Upper Device When Using For UV Fault Recovery
9.1.1.5 Temperature Protection
The device detects temperature by checking the voltage divided by RTS_PU and RTS, with the assumption of using
10 K RTS_PU and 103AT NTC for RTS. System designer should always check the thermistor resistance
characteristic and refer to the temperature protection threshold specification in the Electrical Characteristic table
to determine if a different pull up resistor should be used. If a different temperature trip pint is required, it is
possible to scale the threshold using this equation: Temperature Protection Threshold = RTS/(RTS + RTS_PU).
Example: Scale OTC trip points from 50C to 55C
The OTC protection can be set to 45C or 50C. When the device's OTC threshold is set to 50C, it is referred to
configure the VOTC parameter to 29.38% of VTB (typical), with the assumption of RTS_PU = 10K and RTS =
103AT or similar NTC (which the NTC resistance at 50C = 4.16K). The VOTC specification is simply the resistor
divider ratio of RTS_PU and RTS.
The VOTC, VOTD, VUTC and VUTD configuration options are fixed in the device. Hence, the actual temperature trip
point can only adjust by using a different B-value NTC and/or using a different RTS_PU.
In this example, the 103AT NTC resistance at 55C is 3.536 K. By changing the RTS_PU from 10 K to 8.5 K,
we can scale the actual OTC temperature trip point from 50C to 55C. Because the RTS_PU value is smaller, this
change affects all the other temperature trip points and scales OTD, UTC and UTD to ~5C higher as well.
9.1.1.6 Adding Filter To Sense Resistor
Current fault is sense through voltage across sense resistor. Optional RC filters can be added to the sense
resistor to improve stability.
30
bq77904, bq77905
www.ti.com
0.1 F
SRN
0.1 F
100
0.1 F
100
R SNS
PACK-
For example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor is
mostly 3 m or less.
The typical current to turn on the FET body diode protection is 667 mA using this example. Since there is no
built-in hysteresis, noise can reset the state comparator counter and toggle off the FET body diode protection
and vice versa. Hence, it is normal to observe the device toggles the FET body diode protection on or off within 1
mV to 3 mV range. With a 3mohm sense resistor, it is about 330 mA to 1 A. As this behavior is due to noise from
the system, the FET toggling behavior is usually occurs right at the typical 2mV state comparator threshold, as
current increases or decreases from the typical value, the detection is more solid and has less frequent FET
toggling. Using this example, either charge or discharge should provide a solid FET body diode protection
detection.
Look at the device behavior during an OV event (and no other fault is detected). In an OV event, CHG FET is off
and DSG FET is on. If a discharge of >1 A occurs, the device would turn on the CHG FET immediate to allow the
full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery level, the OV
fault is recovered and CHG driver turns on (or remains on in this scenario) and the state comparator is turned off.
If the discharge current is < 1 A when the device is still in OV fault, the CHG FET may toggle on and off until the
overcharged cell voltage is reduced down to the OV recovery level. When OV fault recovered, the CHG FET will
be solidly turned on and the state comparator is off.
Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can
only pass through the CHG FET body diode until the OV fault is recovered. This increase the risk of damaging
the CHG FET if the MOSFET is not rate to sustain such current through its body diode. It also increases the FET
temperature as current is now carry through the body diode.
31
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
CVDD
RIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
CIN
VC2
RIN
RIN
RIN
bq77905
bq77904
CIN
RTS
TS
VC1
CIN
RTS_PU
VTB
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RCHG
RDSG
RLD
CIN
RGS
RGS
RSNS
DESCRIPTION
VALUES
RIN
1 k 5%
CIN
RVDD
1 k 5%
CVDD
1 F 20%
RTS
NTC thermistor
RTS_PU
Thermistor pullup resistor to VTB pin, assuming using 103AT NTC or NTC with similar
resistance-temperature characteristic
RGS_CHG
RGS_DSG
RCHG
0.1 F 10%
103AT, 10 k 3%
10 k 1%
3.3 M 5%
1 M 5%
1 M 5%
1 k 5%
1 M 5%
RDSG
DSG gate resistor, system designer should adjust this parameter to meet the
desirable FET rise/fall time
10 M 5%
RLD
450 K 5%
RSNS
Current sense resistor for current protection , system designer should change this
parameter according to the application current protection requirement
32
4.5 k 5%
1 m 1%
bq77904, bq77905
www.ti.com
33
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
Threshold
Hystersis
Delay
Recovery Method
OV
4.3 V
200 mV
1 s (default setting)
Hysteresis
UV
2.6 V
400 mV
1 s (default setting)
OW
100 nA
(default setting)
OCD1
40 mV
350 ms
OCD2
80 mV
5 ms
SCD
100 mV
Fixed at 360us
OTC
50C
10C
4.5 s
Hysteresis
OTD
70C
10C
4.5 s
Hysteresis
UTC
-5C
10C
4.5 s
Hysteresis
UTD
-10C
10C
4.5 s
Hysteresis
34
bq77904, bq77905
www.ti.com
DSG remains on
DSG remains on
1st OV Fault
OV fault
35
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
RVDD
CVDD
RIN
RIN
RIN
RIN
RIN
CVDD
CIN
CIN
CIN
CIN
VDD
DVSS
AVDD
CTRD
VC5
CTRC
VC4
CCFG
VC3
VTB
bq77905
VC2
TS
VC1
LD
AVSS
CHG
SRP
CHGU
SRN
DSG
RTS_PU
RTS
RCHG
RDSG
RLD
CIN
RGS
RSNS
RGS
36
bq77904, bq77905
www.ti.com
11 Layout
11.1 Layout Guidelines
1. Match SRN and SRP trace.
2. RIN filters, VDD, AVDD filters and CVDD capacitor should be placed close to the device pins.
3. Separating device ground plane (low current ground) from the high current path. Filter capacitors should
reference to the low current ground path or device Vss.
4. In a stack configuration, the RCTRD and RCTRC should be placed closer to the lower device CTRD and CTRC
pins.
5. RGS should be placed near the FETs
DVSS
AVDD
RC
Filters
PACK+
VC5
:
:
VC1
AVSS
AVSS
CHGU
DSG
RC
Filters
VC5
:
:
DVSS
DVSS
CTRD
Please CTRs
resistors close to
the lower device
CTRC
VC1
AVSS
AVSS
PACK-
37
bq77904, bq77905
SLUSCM3A JUNE 2016 REVISED JUNE 2016
www.ti.com
PRODUCT FOLDER
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq77904
Click here
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bq77905
Click here
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12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
www.ti.com
17-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
BQ7790400PW
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
BQ7790400PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
BQ7790500PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790500
BQ7790500PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790500
BQ7790501PW
PREVIEW
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790501
BQ7790501PWR
PREVIEW
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B7790501
BQ7790502PW
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
BQ7790502PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
BQ7790503PW
PREVIEW
TSSOP
PW
20
1050
TBD
Call TI
Call TI
-40 to 85
BQ7790503PWR
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
www.ti.com
17-Jul-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
30-Jun-2016
Device
BQ7790500PWR
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
30-Jun-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ7790500PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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