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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
- 50
RDS(on) ()
VGS = - 10 V
0.28
Qg (Max.) (nC)
14
Qgs (nC)
6.5
Qgd (nC)
6.5
Configuration
Single
S
Available
RoHS*
COMPLIANT
DESCRIPTION
DPAK
(TO-252)
IPAK
(TO-251)
D
P-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
DPAK (TO-252)
IRFR9020PbF
SiHFR9020-E3
IRFR9020
SiHFR9020
DPAK (TO-252)
IRFR9020TRPbFa
SiHFR9020T-E3a
IRFR9020TRa
SiHFR9020Ta
DPAK (TO-252)
IRFR9020TRLPbFa
SiHFR9020TL-E3a
IRFR9020TRLa
SiHFR9020TLa
IPAK (TO-251)
IRFU9020PbF
SiHFU9020-E3
IRFU9020
SiHFU9020
Note
a. See device orientation.
SYMBOL
VDS
VGS
VGS at - 10 V
TC = 25 C
TC = 100 C
ID
IDM
EAS
IAR
EAR
LIMIT
- 50
20
- 9.9
- 6.3
- 40
0.33
440
- 9.9
4.2
UNIT
V
A
W/C
mJ
A
mJ
WORK-IN-PROGRESS
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LIMIT
42
5.8
- 55 to + 150
300d
UNIT
W
V/ns
C
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
Case-to-Sink
RthCS
110
1.7
RthJC
3.0
UNIT
C/W
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = - 250 A
- 50
Static
Drain-Source Breakdown Voltage
VGS(th)
- 2.0
- 4.0
Gate-Source Leakage
IGSS
VGS = 20 V
500
nA
IDSS
250
1000
0.20
0.28
2.3
3.5
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 9
490
320
RDS(on)
gfs
VGS = - 10 V
ID = 5.7 Ab
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Crss
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = - 10 V
VDD = - 25 V, ID = - 9.7 A,
RG = 18 , RD = 2.4 , see fig. 15
(Independent operating temperature)
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center of
die contact.
70
9.4
14
4.3
6.5
4.3
6.5
8.2
12
57
66
12
18
25
38
4.5
7.5
pF
nC
ns
nH
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SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
- 9.9
- 40
TJ = 25 C, IS = - 9.9 A, VGS = 0 Vb
- 6.3
UNIT
IS
ISM
VSD
trr
Qrr
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
56
110
280
ns
0.17
0.34
0.85
nC
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 14).
b. Pulse width 300 s; duty cycle 2 %.
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IAS
VDS
IL
VDD
tp
VDS
Fig. 14 - Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse Duration
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td(on)
tr
td(off) tf
VGS
10 %
90 %
VDS
QG
- 10 V
QGS
QGD
VG
Charge
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+
Circuit layout considerations
Low stray inductance
Ground plane
Low leakage inductance
current transformer
RG
dV/dt controlled by RG
ISD controlled by duty factor "D"
D.U.T. - device under test
+
- VDD
Period
D=
P.W.
Period
VGS = - 10 V*
Re-applied
voltage
VDD
ISD
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?90350.
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, Vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishays terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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