Pulse & Digital Circuits Lab Manual 3

MADANAPALLE INSTITUTE OF TECHNOLOGY &
SCIENCE
MADANAPALLI
ANGALLU, MADANAPALLE 517 325
PULSE AND DIGITAL CIRCUITS

LABORATORY MASTER MANUAL
DEPARTMENT
OF
ELECTRONICS & COMMUNICATION ENGINEERING
JULY- 2013
Faculty in Charge:
HOD, ECE:
MADANAPALLE INSTITUTE OF
TECHNOLOGY &SCIENCE,
Department of ECE
PULSE AND DIGITAL CIRCUITS

STUDENT LAB MANUAL
Prepared By
Mr. P.R.RATNA RAJU.K, M.Tech,

Asst. Professor,
Department of ECE,
MITS.
P.R.Ratna Raju .K, Department of ECE, MITS
Page 1
JAWAHARLAL NEHRU
TECHNOLOGICAL UNIVERSITY ANANTAPUR
Electronics and Communication Engineering
(9A04506) PULSE & DIGITAL CIRCUITS LAB
(Common to ECE, E Con E, EIE)
B.Tech III-I Sem. (E.C.E.)
Minimum Twelve experiments to be conducted:
1. Linear wave shaping.
2. Non Linear wave shaping Clippers.
3. Non Linear wave shaping Clampers.
4. Transistor as a switch.
5. Study of Logic Gates & Some applications.
6. Study of Flip-Flops & some applications.
7. Sampling Gates.
8. Astable Multivibrator.
9. Monostable Multivibrator.
10. Bistable Multivibrator.
11. Schmitt Trigger.
12. UJT Relaxation Oscillator.
13. Bootstrap sweep circuit.
14. Constant Current Sweep Generator using BJT.
Equipment required for Laboratories:
1. RPS - 0 30 V
2. CRO - 0 20 M Hz.
3. Function Generators - 0 1 M Hz
4. Components
5. Multi Meters
Page 2
PULSE AND DIGITAL CIRCUITS LAB

LIST OF EXPERIMENTS
1. Linear wave shaping.
2. Non Linear wave shaping Clippers.
3. Non Linear wave shaping Clampers.
4. Transistor as a switch.
5. Study of Logic Gates & Some applications.
6. Study of Flip-Flops & some applications
7. Sampling Gates.
8. Astable Multivibrator.
9. Monostable Multivibrator.
10. Bistable Multivibrator.
11. Schmitt Trigger.
12. UJT Relaxation Oscillator.
Additional Experiments:
13. TTL NAND GATE

14. ECL NOR GATE
Advanced Experiments:
15. CMOS NAND GATE,

16.CMOS TRANSMISSION GATE
Page 3
EXP.NO
1
DATE
Experiment Name
Linear wave shaping.
Non Linear wave shaping Clippers.
Non Linear wave shaping Clampers.
Transistor as a switch.
Study of Logic Gates & Some

applications.
Study of Flip-Flops & some

applications
UJT Relaxation Oscillator.
Astable Multivibrator.
Monostable Multivibrator.
10
Bistable Multivibrator.
11
Schmitt Trigger.
12
Sampling Gates.
Page No
Remarks
13
TTL NAND GATE
ECL NOR GATE
14
15
CMOS NAND GATE
16
CMOS TRANSMISSION GATE
Page 4
1. LINEAR WAVESHAPING
A.INTEGRATOR
AIM: To Design RC integrator circuit, calculate rise times theoretically, observe the
response of RC integrator circuit for a square wave input for different time constants
i) RC>>T ii) RC = T
iii) RC<<T and to determine rise time for RC<<T
APPARATUS:
S.No
1.
Name of the
component/Equipments
Resistors
2.
3.
4.
5.
6.
Capacitors
Bread board
Connecting wires
Function generator
CRO
Specification
Quantity
100
1k
10K
0.1uf
1
1
1
1
1
1 Bunch
1
1
CIRCUIT DIAGRAM:
Figure 1: RC Integrator circuit
Page 5
MODEL WAVE FORMS:
OBSERVATIONS:
Vi(volts)
R(K)
C( F)
RC(m sec)
T(m sec)
Vo(volts)
DESIGN:
1. Choose T = 1msec.
2. Select C = 0.1F.
3. For RC = T; select R.
4. For RC >> T; select R.
5. For RC << T; select R.
Page 6
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the figure1.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a square wave signal of frequency 1 KHz at the input. (T = 1 msec.)
4. Observe the output waveform of the circuit for different time constants.
5. Calculate the rise time for low pass filter and compare with the theoretical
values.
6. For low pass filter select rise time (tr) = 2.2 RC (theoretical). The rise time is
defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its
final value.
PRECAUTIONS:
1. Connections should be tight.
2. Take care when biasing the supply.
RESULT:
VIVA QUESTIONS:
1. What is high pass circuit under what condition it acts as a differentiator?
2. What is low pass circuit under what condition it acts as a integrator?
3. Show theoretically how you get a triangular wave when a square wave is
given to an integrator?
4. What happens when a sine wave is applied to a differentiator or integrator
circuit?
5. What are different applications of a differentiator?
6. What are different applications of a integrator?
7. What is the ideal value of phase shift offered by an RC circuit?
Page 7
Integrator output with RC 1msec
Page 8
1 (B) .DIFFERENTIATOR
AIM: Design RC differentiator circuit, calculate percentage of tilt,
observe the
response of the circuit for a square input with different time constants
i) RC>>T ii) RC = T iii) RC<<T and to determine percentage tilt for RC = T
APPARATUS:
S.No
1.
Name of the
Resistors
2.
3.
4.
5.
6.
Capacitors
Bread board
Connecting wires
Function generator
CRO
Specification
Quantity
100 K
1k
10K
0.1uf
1
1
1
1
1
1 Bunch
1
1
CIRCUIT DIAGRAM:
Figure 2: RC Differentiator circuit
Page 9
MODEL WAVE FORMS:
OBSERVATIONS:
Vi(volts)
R(K)
C( F)
RC(m sec)
T(m sec)
Vo(volts)
DESIGN:
1. Choose T = 1msec.
2. Select C = 0.1F.
3. For RC = T; select R.
4. For RC >> T; select R.
5. For RC << T; select R.
Page 10
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the figure2.
3. Apply a square wave signal of frequency 1 KHz at the input. (T = 1 msec.)
4. Observe the output waveform of the circuit for different time constants.
5. Calculate the %tilt for high pass filter and compare with the theoretical values.
6.
%Tilt
V V '
T
*100 % %Tilt 1 1 *100 (theoretical)
2 RC
(V / 2)
V V '
%Tilt 1 1 *100 % (practical)
(V / 2)
PRECAUTIONS:
2. Take care when biasing the supply.
RESULT:
Differentiator output at RC=1m sec.
Page 11
2 . NON-LINEAR WAVE SHAPING - CLIPPERS

AIM: Design, obtain voltage transfer characteristics, plot input and output
waveforms for different clipping circuits with different reference voltages and to
verify the responses of
(I) Shunt diode positive voltage clipper to clip at 1.6V.
(II) Shunt diode negative voltage clipper to clip at -0.4V.
(III) series diode positive voltage clipper to clip at 1V.
(IV) series diode negative voltage clipper to clip at 1V
(V) A two level voltage clipper to clip at +3.6V and -3.6 V
APPARATUS:
S.No
1.
2.
3.
4.
5.
6.
7.
Name of the
Resistors
Diodes
Bread board
Connecting wires
Function generator
CRO
Regulated Power Supply
Specification
Quantity
1k
1N4007
1
2
1
1 Bunch
1
1
1
Page 12
CIRCUIT DIAGRAMS:
1. Shunt diode positive clipper
Figure :1
DC Transfer characteristics:
Input& output waveforms:
Page 13
2. Shunt diode negative clipper
Figure : 2
Page 14
3. Series diode positive clipper
Figure :3
Page 15
4. Series diode negative clipper
Figure :4
Page 16
5. Two level clipper
Figure:5
Page 17
THEORY:
PROCEDURE:
1. Connect the circuit as shown in the figure 1.
3. Apply a sine wave signal of frequency 1 KHz, Amplitude greater than the
reference voltage at the Input and observe the output waveforms of the circuits.
4. Repeat the procedure for remaining circuits.
PRECAUTIONS:
2. Take care when applying proper supply.
RESULT:
IVA QUESTIONS:
1.
2.
3.
4.
5.
Define clipping?
What are the applications of clippers?
Define peak inverse voltage of diode?
What are the other names for the clippers?
Explain the clipping process?
Page 18
3. NON-LINEAR WAVESHAPING - CLAMPERS

AIM: Design following clamper circuits, verify output waveforms and plot them.
(I) Positive clamper (II) Negative clamper. (III) Positive clamper with a +2V,
(IV) Negative clamper with a -2V.
APPARATUS:
1.
2.
3.
4.
5.
6.
Diode 1N4001 1 No
Capacitor 0.1 F
Resistor - 1K
Function Generator
RPS
CRO
CIRCUIT DIAGRAMS:
1. POSITIVE CLAMPER
Page 19
2. NEGATIVE CLAMPER
3 POSITIVE CLAMPER with 2V
Page 20
4.NEGATIVE CLAMPER WITH -2V
Page 21
THEORY:
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. I/P signal is applied to the circuit with the amplitude of 4v p-p and 1 KHz
frequency.
3. The AC / DC push button switch of CRO is to be kept in DC mode.
4. Note down the o/p amplitude for each and every circuit.
5. The O/P waveforms are to be drawn on the graph sheet.
RESULT:
VIVA QUESTIONS:
1. Define clipping?
2. Define clamping?
3. Define peak inverse voltage of diode?
4. Draw the o/p wave forms for
1. +ve clamper
2. ve clamper
5. What are the other names for the clamper?
6. What are the applications of clampers?
7. Explain the clipping process?
Page 22
4.TRANSISTOR AS A SWITCH
AIM: Design a switch using BJT to switch LED, and observe the waveform, note
down Vce, Vbe ON & Voff values.
APPARATUS:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
Name of the component

Resistors
Transistor
Bread board
Connecting wires
Function generator
CRO
Dual Regulated Power supply
LED
Specification
2.4k
BC 107
(0-30) V DC
Quantity
1
1
1
1
1 Bunch
1
1
1
1
CIRCUIT DIAGRAMS:
Figure:1
Page 23
MODEL WAVE FORMS:
OBSERVATIONS:
VBE (Volts)
VCE (Volts)
VCB (Volts)
1.When Transistor is ON
2. When Transistor is OFF
DESIGN :Ic max = , VBE =
, VCE (sat) = , Vcc =
Rc min= VCC / Ic max=

ICS = (VCC VCE (sat)) / Rc =
IB = ICS/ hfe=(Vi-VBE)/RB=
(hfe =
RB = ( Vi VBE ) / IB=
THEORY:
Page 24
PROCEDURE :
1. Connect the circuit as shown in the figure 1.
2. Connect 5V power supply to VCC and 0V to the input terminals.
3. Measure the voltage (a) across collector to emitter terminals, (b) across
collector to base terminals and (c) Base to emitter terminals.
4. Connect 5V to the input terminals.
5. Measure the voltage (a) across collector to emitter terminals, (b) across
collector to base terminals and (c) Base to emitter terminals.
6. Observe that the LED glows when the input terminals are supplied with 0 volts.
The LED will NOT glow when the input voltage is 5V.
7. Remove the load (1kand LED) and DC power supply (connected between
RB and Gnd.). Now connect a function generator to the input terminals.
8. Apply Square wave of 1 KHz, V (p-p) is 5V
9. Observe the waveforms at the input terminals and across collector and ground.
10. Plot the waveform on a graph sheet. Note the inversion of the signal from input to
output.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
What are the different switching times of a transistor?

Define ON time of a transistor?
Define OFF time of a transistor?
Explain how transistor acts as a switch?
Define delay time (td), raise time (tr), saturation time (ts) and fall time (tf) of a
transistor?
Page 25
5. STUDY OF LOGIC GATES & SOME APPLICATIONS

STUDY OF LOGIC GATES
AIM: To verify the truth tables of AND, OR, NOT, NAND, NOR, and EX-OR
gates.
APPARATUS:
1.
2.
3.
4.
5.
6.
7.
8.
Bread board IC trainer

IC74LS08 (AND)
IC74LS32 (OR)
IC 74LS04 (NOT)
IC74LS00 (NAND)
IC74LS02 (NOR)
IC74LS86 (EX-OR)
Patch cards
CIRCUIT DIAGRAM
AND GATE IC
NOT GATE IC
OR GATE IC
NAND GATE IC
Page 26
NOR GATE IC
EX-OR GATE IC
OBSERVATIONS:
AND GATE
OR GATE
A
0
0
1
1
B
0
1
0
1
NAND GATE
A
0
0
1
1
B
0
1
0
1
B
0
1
0
1
B
0
1
0
1
NOR GATE
Y
EX-OR GATE
A
0
0
1
1
A
0
0
1
1
A
0
0
1
1
B
0
1
0
1
EX-NOR GATE
Y
A
0
0
1
1
B
0
1
0
1
THEORY:
Page 27
PROCEDURE:
1. +5V DC is applied at VCC (pin no:14) of each IC w.r.t. ground(pin no:7).
2. I/ps are applied (at pin nos 1 &2) and o/p is taken from (pin no:3).
3. I/ps are applied from toggle switches and o/p is observed at o/p indicators.
PRECAUTIONS:
1. Avoid loose connections on Breadboard.
2. Take care while making connections with NOT and NOR gates.
RESULT:
Page 28
5(b) APPLICATIONS
HALF ADDER, FULL ADDER AND HALF SUBTRACTOR
AIM: Design Half Adder, Full Adder and Half subtractor and verify truth table
practically.
APPRATUS:
i.
ii.
iii.
iv.
v.
vi.
IC 7432-- OR gate
IC 7408--AND gate
IC 7404NOT gate
IC 7486EX-OR gate
Bread board IC trainer
Patch cards
CIRCUIT DIAGRAMS:
Half adder:
Full adder:
Page 29
Half Subtractor:
THEORY:
PROCEDURE:
Half adder:
1. All the connections are made as per the circuit diagram.
2. Inputs are applied from logic inputs and outputs are observed at the output
indicators.
3. The truth table of half adder is verified.
Half Subtractor:
indicator.
3. The truth table of half sub tractor is verified.
Full Adder:
1. All the connections are made as per the circuit diagram
indicator
3. The truth table of full adder is verified.
Page 30
TRUTH TABLES:
Half Adder:
INPUTS
A
0
0
1
1
B
0
1
0
1
SUM
OUTPUTS
CARRY
Half Subtractor:
INPUTS
A
0
0
1
1
B
0
1
0
1
OUTPUTS
DIFFERENCE
BORROW
Full Adder:
A
0
0
0
0
1
1
1
1
INPUTS
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
OUTPUTS
SUM
CARRY
PRECAUTIONS:
1. Connections should be correct.
2. Pin numbers should be identified properly.
RESULT:
Page 31
VIVA QUESTIONS:
1. What is meant by half adder?
2. What is meant by full adder?
3. What is meant by half subtractor?
4. What is meant by 1s complement?
5. What is meant by 2s complement?
6. Why do you prefer 2s complement in computers?
7. What is Boolean expression for full adder sum and carry?
8. What is the advantage of look ahead carry adder?
9. Design full adder by using half adders?
10. What is the disadvantage of look ahead carry adder?
Page 32
6. STUDY OF FLIP FLOPS & SOME APPLICATIONS

STUDY OF FLIP FLOPS USING ICS
AIM: To construct and verify the truth tables of SR flip flop, JK flip flop, D and T
flip - flop.
APPRATUS:
i.
ii.
iii.
iv.
v.
vi.
IC 7473 JK flip flop

IC 7400NAND gate
IC 7404 NOT gate
Patch cards
Connecting wires
IC bread board trainer
CIRCUIT DIAGRAMS:
i)
S-R FLIP-FLOP using NAND gate
ii)
S-R FLIP-FLOP using NOR gate
Page 33
iii)
J-K FLIP- FLOP
iv)
D FLIP- FLOP
v)
T FLIP- FLOP
Page 34
TRUTH TABLES:
S-R FLIP-FLOP:
Q(t)
0
0
0
0
1
1
1
1
Inputs
S
0
0
1
1
0
0
1
1
Outputs
Q(t+1)
Outputs
Q(t+1)
0
1
0
1
0
1
0
1
J-K FLIP-FLOP:
Q(t)
Inputs
J
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D- FLIP-FLOP:
Q(t)
0
0
1
1
D
0
1
0
1
Q(t+1)
Page 35
T- FLIP-FLOP:
Q(t)
0
0
1
1
T
0
1
0
1
Q(t+1)
PIN DIAGRAM:
THEORY:
PROCEDURE:
1. The input S, R is given to NAND gates and clock pulse is applied between
the other two terminals and NAND gates.
2. The input of the one NAND gate is connected to the other gate and vice
versa to form SR latch.
3. The output of the NAND gate whose input is S, is connected to the input
of the other NAND gate.
4. The output of the NAND gate whose input is R, is connected to the input
of the other NAND gate whose output is Q1.
Page 36
J K flip-flop:
1.
2.
3.
4.
5.
Connections are made as per the circuit diagram.

The inputs J1 and K1 are given to the pin numbers 14 and 3 of IC 7473.
Clock pulse CP1 is applied at the pin 1.
Vcc and ground connections are given to the pin 4 and 11.
The outputs Q1 and Q1 bar are connected to pin 12 and 13.
D flip-flop
1. Connections are made per the circuit diagram.
2. A NOT gate is connected between the inputs J and K.
3. From JK flip flop we can obtain the D flip flop.
T flip-flop
2. From J K flip flop, we can obtain the T flip-flop by shorting the two inputs
J and K.
RESULT:
Page 37
6 (b) APPLICATIONS OF FLIP- FLOPS

AIM:
Design a synchronous counter using JK FF to count up to 6, and verify its truth
table..
APPARATUS:
1.
2.
3.
4.
5.
J-K flip-flop(IC 7473)

AND gate(IC 7408)
Patch cards
Bread board trainer
Connecting wires
LOGIC DIAGRAM:
PRESENT STATE
QA
QB
QC
JA=
KA=
TRUTH TABLE
NEXT STATE
QA
QB
QC
JA
KA
JB=
KB=
OUT PUT
JB
KB
JC=
JC
KC
KC=
Page 38
THEORY:
PROCEDURE:
1. Connect the circuit as per logic diagram shown.
2. Switch ON the Kit and note down the output.
3. Verify output sequence with truth table.
PRECAUTIONS:
1. Connections should be made carefully.
2. ICs and flip-flops should be handled carefully.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
What does meant by memory?

Define sequential circuits?
Define combinational circuits?
What is the difference between RS and JK flip flops
Page 39
7. UJT RELAXATION OSCILLATOR

AIM:
Design UJT relaxation oscillator at 200Hz, verify response and plot waveforms.
APPARATUS:
1.
2.
3.
4.
5.
6.
7.
8.
Bread board trainer

UJT 2N 2646
Resistors-(4.7k ,47,330)
DRB
Capacitors-(0.1f)
CRO
Regulated power supply(0-30V)
Connecting wires
CIRCUIT DIAGRAM:
Page 40
MODEL WAVE FORMS:
THEORY:
THEORITICAL CALCULATIONS:
T = RTCT ln(1/(1-n) )
n = (VP - VD)/VBB
Let =0.56 ,RT=24.7Kohm ,CT=0.1microfarad Then T=
Page 41
PROCEDURE:
1.
2.
3.
4.
5.
6.
Connections are made as per the circuit diagram.

The Output Vo is noted, time period is also noted.
The theoretical time period should be calculated.
T=RTCT ln(1/1-n)
The Output at base 1 and base 2 should note.
Graph should be plotted and waveforms are drawn for V0, VB1,VB2.
PRECAUTIONS:
2. UJT terminals are identified properly.
3. Readings can not be exceeding the limits.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
Draw the circuit symbol of double sided diode?

Define intrinsic-standoff ratio?
Define peak voltage?
Define valley voltage?
Mention the names for negative resistances devices?
Page 42
8. ASTABLE MULTIVIBRATOR
AIM: Design astable multivibrator to run at 1K Hz frequency and to observe the
response at base and collector points of the transistors and plot them.
APPARATUS:
1.
Function generator.
2.
Resistors (2.2 k, 15 k) (2 nos.)
3.
Capacitors (0.047 F) (2nos.)
4.
CRO
5.
RPS (0-30 V)
6.
Bread board
7.
Connecting wires
CIRCUIT DIAGRAM:
Page 43
MODEL WAVEFORMS:
THEORY:
PROCEDURE:
2. Different voltages are measured at base and collector points of two transistors
w.r.t ground as VC1, VC2, VB1 and VB2.
3. All the waveforms are plotted on the graph sheet, the amplitudes and time
periods are noted down.
4. Theoretical values of amplitudes and time periods are compared with practical
values.
Page 44
PRECAUTIONS:
2. Should take care when applying proper supply.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
Define stable state of a transistor?

Define semi-stable state of transistor?
What are the other names of Astable Multivibrator?
Explain the operation of a Astable Multivibrator?
How many stable states and semi-stable states present in the Astable
Multivibrator?
6. Draw the waveforms of VC1 and VC2 of a Astable Multivibrator?
7. What is the formula for the theoretical value of T in Astable Multivibrator?
Page 45
9. MONOSTABLE MULTIVIBRATOR
AIM: Design a monostable multivibrator using transistors to generate a pulse with
500 sec and to observe the response at base and collector points of the transistors and
plot them.
APPARATUS:
1.
2.
3.
4.
5.
6.
7.
Transistors BC107 (2 nos)

Breadboard trainers
Resistors 1k , 10k , 100k
Capacitors 0.047F (2 nos)
CRO
Connecting wires
R.P.S
CIRCUIT DIAGRAM:
Page 46
MODEL WAVEFORMS:
THEORY:
PROCEDURE:
2. The voltages are measured at collector and base terminals w.r.t ground by
giving the VBB of 1.5v through the 100k resistor and the wave forms are
drawn as VC1, VC2, VB1, VB2.
3. The amplitudes and time periods of all the waveforms are noted down.
Page 47
RESULT:
VIVA QUESTIONS:
1. What are the other names of Monostable Multivibrator?
2. How many stable and semi stable states present in the Monostable
Multivibrator?
3. Explain the operation of Monostable Multivibrator?
4. What is the theoretical value of T ?
5. What is the name of base capacitor and what is the purpose of base capacitor?
Page 48
10. BISTABLE MULTIVIBRATOR

AIM: To understand the working of Bistable Multivibrator using transistors.
APPARATUS:
1.
2.
3.
4.
5.
6.
7.
Transistors - BC107 (2 nos)

Breadboard trainer
Resistors (2.2 k ,15 k ,100 k)
CRO
Capacitors - 0.047F (2 nos)
Connecting wires
R.P.S
CIRCUIT DIAGRAM:
Page 49
MODEL WAVEFORMS:
Page 50
THEORY:
PROCEDURE:
2. Without keeping the base resistances and with base resistances measure the
voltages at base and collector points of the two transistors T1 and T2 as VC1,
VB1 and VC2, VB2 respectively.
3. By applying the triggering voltage of 1.5V at the base terminals measure the
time period and amplitude of the waveform.
4. All the graphs are drawn on the graph sheet.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
What are the other names of Bistable Multivibrator?

How many stable and semi stable states present in the Bistable Multivibrator?
Explain the operation of Bistable Multivibrator?
What is the theoretical value of T?
What is the name of base capacitor and what is the purpose of base capacitor?
Page 51
11. SCHMITT TRIGGER

AIM: Design a Schmitt trigger circuit using transistors with UTP = 5.2V, and LTP
=3.8V. Vcc= 12V, Rc2= 1K, Rc1= 4K Rs= 1K Vbeon= 0.6V, Vbe sat= 0.8,
Re= 3K, and observe the waveforms, plot it.
APPARATUS:
1. Breadboard trainer
2. Function generator
3. Transistors BC107 - (2 nos)
4. Resistors (820, 1.2k , 1k (2nos), 10k, 150 )
5. Capacitors (0.047 F)
6. Function generator
7. CRO
8. R.P.S
CIRCUIT DIAGRAM:
Page 52
MODEL WAVE FORMS:
THEORY:
PROCEDURE:
2. Fixed the i/p voltage 10v p-p at 1 KHz frequency.
3. The o/p voltage was taken at the collector point of transistor T2. w.r.t the
ground applying the bias voltage 12V.
4. The magnitudes of UTP and LTP are noted. By observing waveform on CRO.
PRECAUTIONS:
2. Should take care when biasing proper supply.
RESULT:
Page 53
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
Define upper trigger potential?

Define lower trigger potential?
Define hysterisis?
What are the other names of Schmitt trigger?
For any type of i/p what is the o/p of a Schmitt trigger?
Explain the operation of a Schmitt trigger?
What is the theoretical value of UTP?
What is the theoretical value of LTP?
Page 54
12. SAMPLING GATES

AIM: To construct and verify the response of sampling gate by using diode.
APPARATUS:
1.
2.
3.
4.
5.
6.
Function generator
CRO
Connecting wires
Resistors(1 K, 10 K)
Capacitor (0.047F)
Diode 1N4007
CIRCUIT DIAGRAM:
MODEL WAVEFORMS:
Page 55
THEORY:
PROCEDURE:
1. Connect the circuit as per circuit diagram
2. Applying both inputs (signal input and control input) simultaneously to the
circuit.
3. Repeat the second step by varying input signal and putting the control signal
fixed.
4. Note down the output waveforms for various range of input signals
PRECAUTIONS:
2. Take care when applying the control signal.
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
What is sampling gate?

Define control signal?
What is the other name for the control signal?
What is the difference between logic gates and sampling gates?
What is the necessity of the sampling gate?
Page 56
13. TTL NAND GATE

AIM: Simulate standard TTL NAND GATE in Multisim and find out transfer
characteristics. Estimate Noise margins, propagation delay, fan out and fan in.
APPARATUS:
Multisim
CIRCUIT DIAGRAM:
Standard TTL circuit Diagram.
Theory:
Procedure:
1. Connect the circuit as shown in circuit diagram.
2. Apply V1 & V2 individually and note down output voltage.
3. Tie V1 and V2 together, perform DC analysis and obtain DC transfer
characteristics.
4. Findout Noise margin from DC transfer characteristics.
5. Apply a clock signal at input and obtain transient response.
6. From the transient response calculate propagation delay.
Page 57
DC TRASFER CHARACTERISTICS:
Transient response:
Result:
Page 58
14. ECL NOR GATE
AIM: Simulate standard ECL NOR GATE in Multisim and find out transfer
characteristics. Estimate Noise margins, propagation delay, fan out and fan in.
APPARATUS:
Multisim
CIRCUIT DIAGRAM:
Fig: ECL NOR GATE
Theory:
Page 59
Procedure:
1. Connect the circuit as shown in circuit diagram.
2. Apply V1 & V2 individually and note down output voltage.
3. Tie V1 and V2 together, perform DC analysis and obtain DC transfer
characteristics.
4. Find out Noise margin from DC transfer characteristics.
5. Apply a clock signal at input and obtain transient response.
6. From the transient response calculate propagation delay.
Result:
Page 60

Pulse &amp; Digital Circuits Lab Manual 3

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MADANAPALLE INSTITUTE OF TECHNOLOGY &

PULSE AND DIGITAL CIRCUITS

PULSE AND DIGITAL CIRCUITS

Mr. P.R.RATNA RAJU.K, M.Tech,

P.R.Ratna Raju .K, Department of ECE, MITS

P.R.Ratna Raju .K, Department of ECE, MITS

PULSE AND DIGITAL CIRCUITS LAB

13. TTL NAND GATE

15. CMOS NAND GATE,

P.R.Ratna Raju .K, Department of ECE, MITS

Non Linear wave shaping Clippers.

Non Linear wave shaping Clampers.

Study of Logic Gates & Some

Study of Flip-Flops & some

UJT Relaxation Oscillator.

CMOS NAND GATE

CMOS TRANSMISSION GATE

P.R.Ratna Raju .K, Department of ECE, MITS

iii) RC<<T and to determine rise time for RC<<T

Figure 1: RC Integrator circuit

P.R.Ratna Raju .K, Department of ECE, MITS

MODEL WAVE FORMS:

P.R.Ratna Raju .K, Department of ECE, MITS

P.R.Ratna Raju .K, Department of ECE, MITS

Integrator output with RC 1msec

P.R.Ratna Raju .K, Department of ECE, MITS

Figure 2: RC Differentiator circuit

P.R.Ratna Raju .K, Department of ECE, MITS

MODEL WAVE FORMS:

P.R.Ratna Raju .K, Department of ECE, MITS

Differentiator output at RC=1m sec.

P.R.Ratna Raju .K, Department of ECE, MITS

2 . NON-LINEAR WAVE SHAPING - CLIPPERS

P.R.Ratna Raju .K, Department of ECE, MITS

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

2. Shunt diode negative clipper

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

3. Series diode positive clipper

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

4. Series diode negative clipper

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

5. Two level clipper

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

P.R.Ratna Raju .K, Department of ECE, MITS

3. NON-LINEAR WAVESHAPING - CLAMPERS

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

Input& output waveforms:

3 POSITIVE CLAMPER with 2V

P.R.Ratna Raju .K, Department of ECE, MITS

Input& output waveforms:

4.NEGATIVE CLAMPER WITH -2V

Input& output waveforms:

P.R.Ratna Raju .K, Department of ECE, MITS

P.R.Ratna Raju .K, Department of ECE, MITS

Name of the component

P.R.Ratna Raju .K, Department of ECE, MITS

MODEL WAVE FORMS:

Pulse & Digital Circuits Lab Manual 3

Pulse & Digital Circuits Lab Manual 3