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CHAPTER 2
CHAPTER 3
CMOS Processing
82
Bipolar Processing
95
CMOS Layout and Design Rules
Analog Layout Considerations
Latch-Up
118
References
121
Problems
121
96
105
125
Chapter 1
Since the diode area is 100 x lo-'' m2, the total zero-bias depletion capacitance is
As expected, we see a decrease in junction capacitance as the width of the depletion region is increased.
Graded Junctions
All of the above equations assumed an abrupt junction where the doping concentration changes quickly from p to n over a small distance. Although this is a good
approximation for many integrated circuits, it is not always true. For example, the
collector-to-base junction of a bipolar transistor is most commonly realized as a
graded junction. In the case of graded junctions, the exponent 112 in Eq. (1.15) is
inaccurate, and a better value to use is an exponent closer to unity, perhaps 0.6 to 0.7.
Thus, for graded junctions, (1.15) is typically written as
where
From (1.27), we see that a graded junction results in a depletion capacitance that
is less dependent on V, than the equivalent capacitance in an abrupt junction. In other
words, since rn is less than 0.5, the depletion capacitance for a graded junction is