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Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
CMOS summary
Logic consumes no static power in CMOS
design style.
Vdd
Vi
Vo
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Vdd
Out
in
Gnd
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Static Characteristics
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Low input
Vdd
Out
in
Gnd
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
V1 V2 V1 + (Vi VTn )2 = 0
2
2
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
1 2
V1 V2 V1 + (Vi VTn )2 = 0
2
2
The solutions are:
q
V1 = V2 V22 (Vi VTn )2
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Noise Margins
We find points on the transfer curve where the slope is -1.
When the input is low and output high, we should use
q
Vo = VTp + (Vdd VTp )2 (Vi VTn )2
and
Vdd VTp
ViL = VTn + p
( + 1)
VoH = VTp +
Dinesh Sharma
(V VTp )
+ 1 dd
Logic Design Styles
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
(Vdd VTp )
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Ratioed Logic
To make the output low value lower than VTn , we get the
condition
1 Vdd VTp 2
>
3
VTn
This places a requirement on the ratios of widths of n and
p channel transistors. The logic gates work properly only
when this equation is satisfied.
Therefore this kind of logic is also called ratioed logic.
In contrast, CMOS logic is called ratioless logic because it
does not place any restriction on the ratios of widths of n
and p channel transistors for static operation.
The noise margin for pseudo nMOS can be determined
easily from the expressions for ViL , VoL , ViH , VoH .
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Rise Time
Vdd
ViL
Vo
This gives
rise
2VTp
Vdd + VoH 2VTp
C
+ ln
=
Kp (Vdd VTp ) Vdd VTp
Vdd VoH
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Fall Time
Vdd
Out
in
Gnd
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Fall Time
If we assume that the pMOS current remains constant at its
saturation value,
Kp
Ip =
(Vdd VTp )2
2
. We can write the KCL equation at the output node as:
In Ip + C
dVo
=0
dt
which gives
fall
=
C
VoL
Vdd
dVo
In Ip
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Fall Time
Vdd
Out
in
Gnd
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Fall Time
fall
=
C
V1
Vdd
dVo
1
2
2 Kn V1 Ip
VoL
V1
dVo
Kn (V1 Vo 21 Vo2 ) Ip
so,
fall
V V1
= 1 dd 2
+
C
2 Kn V1 Ip
Dinesh Sharma
V1
VoL
dVo
Kn (V1 Vo 21 Vo2 ) Ip
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Dinesh Sharma
Static Characteristics
Noise margins
Dynamic characteristics
Pseudo nMOS design Flow
Vdd
Out
Dinesh Sharma