GATE 2016 Exam - EC

30 January 2016 - 9:00 am to 12:00 noon (Morning)

Subject

No. of
Questions

Topics asked in Paper

Level of
Toughness

Total
Marks

Networks

1M:3
2M:3

Network Solution ;Transient Analysis to DC

input;Two port Network;
Network Topology

MODERATE

Control System

1M:4
2M:4

State Variable Analysis;RLT;

Stability & R-H Criterion;Time domain
Analysis; Basics

TOUGH

12

Signals &
Systems

1M:2
2M:2

(LTI)System; FourierAnalysis;Z-Transform;
Frequency Response of LTI System

EASY

Digital &P

1M:2
2M:4

Boolean Algebra &K-Map

Logic Gates; Combinational& Sequential
Circuit ,Counter; Microprocessor

EASY

10

Analog Circuits

1M:2
2M:3

Op-Amp; Elber-Moll Model; Current Mirror;

MODERATE

Com. Systems

1M:2

Random Process; Digital communications

EASY

2M:2
EDC

1M:3
2M:5

FET(TEFT,MOSFET,)&
CMOS;Semiconductor theory

TOUGH

13

EMT

1M:4
2M:4

Optical Fibers*; Electrostatics; Lorentz Force

Uniform Plane Waves; Transmission Lines

TOUGH

12

Engineering
Mathematics

1M:3
2M:3

Linear Algebra ;Probability and Distribution

;Numerical Method; Complex Variable

MODERATE

GA

1M:5
2M:5

Verbal Ability; Time and Work; Directions;

Venn Diagrams; Mensuration and Area; Clock MODERATE

Total

65

MODERATE

15
100

GATE 2016 Exam - EC

31 January 2016 - 9:00 am to 12:00 noon

Subject
Networks

No. of
Questions

Topics asked in Paper

1 M: 4
2 M: 3

Star-Delta; Basic Networks; Dependent

Source;

Level of
Toughness

Total
Marks

EASY

10

Control System

1 M: 2
2 M: 3

Maximum Power Transfer

Bode Plot; Time Response; Nyquist Plot;
Initial Value (L.T)

Signals &
Systems

1 M: 1
2 M: 2

Digital filters; Energy and Power; DFT

EASY

Digital & uP

1 M: 2
2 M: 3

DAC; Flip-flop; Finite State Machines*,

Memory Interface

MODERATE

Analog Circuits

1 M: 3
2 M: 4

Op-Amp; Elber-Moll Model; Current Mirror;

TOUGH

11

Com. Systems

1 M: 4
2 M: 3

Random Process

TOUGH

10

EDC

1 M: 1
2 M: 4

P-n Junction; NMOS

MODERATE

EMT

1 M: 4
2 M: 4

Optical Fibers*; Electrostatics; Lorentz

Force Uniform Plane Waves; Transmission
Lines

MODERATE

12

Engineering
Mathematics

1 M: 4
2 M: 4

Joint Distribution*; Analytic Function;

Greens Theorem; Eulers Method; Eigen
Values;

MODERATE

12

GA

1 M: 5
2 M: 5

Verbal Ability; Time and Work; Directions;

Venn Diagrams; Mensuration and Area;
Clock

EASY

15

Total

65

Moderate

100

EASY

GATE 2016 Exam - EC

31 January 2016 - 2:00 pm to 5:00 pm (Afternoon)

Subject

No. of
Questions

Topics asked in Paper

Level of
Toughness

Total
Marks

Networks

1 M: 1
2 M: 3

Network Solution and methodology ;Transient

Analysis to DC input;
Two port Network;
Network Topology

MODERATE

1 M: 2
Control System
2 M: 3

State Variable Analysis;

Root Locus Technique;
Stability & R-H Criterion ;Time domain
Analysis; Basics

EASY

Signals &
Systems

1 M: 3
2 M: 4

Linear Time invariant (LTI)System;

FourierAnalysis ;Z-Transform; Frequency
Response of LTI System

TOUGH

11

Digital &P

1 M: 3
2 M: 3

Boolean Algebra &K-Map

Logic Gates; Combinational& Sequential
Circuit ,Counter; Microprocessor

TOUGH

Analog Circuits

1 M: 3
2 M: 4

Op-Amp; Elber-Moll Model; Current Mirror;

MODERATE

11

Com. Systems

1 M: 3
2 M: 4

Random Process

TOUGH

11

EDC

1 M: 3
2 M: 3

FET(TEFT,MOSFET,)& CMOS;Semiconductor
TOUGH
theory

EMT

1 M: 2
2 M: 2

Optical Fibers*; Electrostatics; Lorentz Force

Uniform Plane Waves; Transmission Lines

MODERATE

Engineering
Mathematics

1 M: 5
2 M: 4

Linear Algebra ;Probability and Distribution

;Numerical Method; Complex Variable

MODERATE

13

GA

1 M: 5
2 M: 5

Total

65

Verbal Ability; Time and Work; Directions; Venn

MODERATE
Diagrams; Mensuration and Area; Clock
MODERATE

15
100

* Indicates Questions from New Syllabus

Faculty Feedback: Few questions came from New Syllabus; General Ability was pretty easy; Not
many calculations except from Electronic Devices; question required logic for solving , qualifying is
easy but scoring is tough , Time Management very critical. practice previous question papers will be
beneficial.