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FEATURES
20
19
18
17
16
15
14
13
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
VCC
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
RGY PACKAGE
(TOP VIEW)
20
3
4
19 OE
18 B1
17 B2
5
6
16 B3
15 B4
7
8
14 B5
13 B6
12 B7
10
11
B8
DIR
GND
DESCRIPTION/ORDERING INFORMATION
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated.
ORDERING INFORMATION
PACKAGE (1)
TA
QFN RGY
(1)
TOP-SIDE MARKING
SN74LV245ATRGYR
Tube
SN74LV245ATDW
SN74LV245ATDWR
SOP NS
SN74LV245ATNSR
74LV245A
SSOP DB
SN74LV245ATDBR
LV245A
TSSOP PW
SN74LV245ATPWR
LV245AT
TVSOP DGV
SN74LV245ATGVR
LV245A
SOIC DW
40C to 85C
VV245
LV245A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
OPERATION
OE
DIR
B data to A bus
A data to B bus
Isolation
1
19
A1
18
OE
B1
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
(1)
MAX
VCC
0.5
VI
0.5
0.5
0.5
VCC + 0.5
state (2)
UNIT
VO
VO
Output voltage range applied in the high or low state (2) (3)
IIK
VI < 0
20
mA
IOK
50
mA
IO
VO = 0 to VCC
35
mA
70
mA
JA
package (4)
70
92
DW package (4)
58
NS package (4)
60
PW package (4)
83
C/W
37
65
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
Supply voltage
VIH
VIL
VI
Input voltage
MIN
MAX
4.5
5.5
UNIT
V
V
0.8
5.5
VCC
3-state
5.5
VO
Output voltage
IOH
16
IOL
16
mA
t/v
20
ns/V
TA
85
(1)
40
V
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
TA = 40C
to 85C
TA = 25C
MIN
TYP
4.5
IOH = 50 A
4.5 V
4.4
IOH = 16 mA
4.5 V
3.8
IOL = 50 A
4.5 V
IOL = 16 mA
4.5 V
MAX
UNIT
MIN MAX
4.4
3.8
0
0.1
0.1
0.55
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
0.1
IOZ
VO = VCC or GND
5.5 V
0.25
2.5
ICC
VI = VCC or GND, IO = 0
5.5 V
20
5.5 V
1.35
1.5
mA
0.5
ICC
(1)
Ioff
VI or VO = 0 to 5.5 V
Ci
Control inputs
VI = VCC or GND
5V
pF
Cio
A or B port
VO = VCC or GND
5V
pF
(1)
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHz
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
CL = 50 pF
TA = 25C
MIN
MAX
MIN
TYP
MAX
3.1
4.9
7.7
8.5
2.3
4.9
7.7
8.5
3.5
9.4
13.8
15
3.7
9.4
13.8
15
3.5
3.9
7.5
2.6
3.9
7.5
4.6
5.4
8.7
9.5
4.7
5.4
8.7
9.5
4.9
9.9
14.8
16
5.3
9.9
14.8
16
4.5
10.1
15.4
16.5
4.1
10.1
15.4
16.5
UNIT
ns
ns
ns
ns
ns
ns
ns
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
Noise Characteristics
(1)
VCC = 5 V, CL = 50 pF
TA = 25C
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
1.1
1.5
VOL(V)
1.1
1.5
VOH(V)
VIH(D)
VIL(D)
(1)
V
0.8
Operating Characteristics
VCC = 5 V, TA = 25C
PARAMETER
Cpd
Outputs enabled
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
TYP
19
UNIT
pF
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
Test
Point
RL = 1 k
From Output
Under Test
CL
(see Note A)
S1
Open
TEST
GND
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
VCC
50% VCC
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH 0.3 V
VOH
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
SN74LV245AT
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
MECHANICAL DATA
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74LV245ATDBR
ACTIVE
SSOP
DB
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDBRE4
ACTIVE
SSOP
DB
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDBRG4
ACTIVE
SSOP
DB
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDGVR
ACTIVE
TVSOP
DGV
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDGVRE4
ACTIVE
TVSOP
DGV
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDGVRG4
ACTIVE
TVSOP
DGV
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDW
ACTIVE
SOIC
DW
20
25
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDWE4
ACTIVE
SOIC
DW
20
25
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDWG4
ACTIVE
SOIC
DW
20
25
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDWR
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDWRE4
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATDWRG4
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATNSR
ACTIVE
SO
NS
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATNSRE4
ACTIVE
SO
NS
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATNSRG4
ACTIVE
SO
NS
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPW
ACTIVE
TSSOP
PW
20
70
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWE4
ACTIVE
TSSOP
PW
20
70
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWG4
ACTIVE
TSSOP
PW
20
70
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWR
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWRE4
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWRG4
ACTIVE
TSSOP
PW
20
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWT
ACTIVE
TSSOP
PW
20
250
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWTE4
ACTIVE
TSSOP
PW
20
250
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATPWTG4
ACTIVE
TSSOP
PW
20
250
CU NIPDAU
Level-1-260C-UNLIM
SN74LV245ATRGYR
ACTIVE
QFN
RGY
20
CU NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
Lead/Ball Finish
4-Jun-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74LV245ATRGYRG4
ACTIVE
QFN
RGY
Lead/Ball Finish
CU NIPDAU
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
19-May-2007
Pack Materials-Page 1
Device
19-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV245ATDBR
DB
20
MLA
330
16
8.2
7.5
2.5
12
16
Q1
SN74LV245ATDGVR
DGV
20
MLA
330
12
7.0
5.6
1.6
12
Q1
SN74LV245ATDWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74LV245ATNSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
SN74LV245ATPWR
PW
20
MLA
330
16
6.95
7.1
1.6
16
Q1
SN74LV245ATRGYR
RGY
20
MLA
180
12
3.8
4.8
1.6
12
Q1
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74LV245ATDBR
DB
20
MLA
342.9
336.6
28.58
SN74LV245ATDGVR
DGV
20
MLA
338.1
340.5
20.64
SN74LV245ATDWR
DW
20
MLA
333.2
333.2
31.75
SN74LV245ATNSR
NS
20
MLA
333.2
333.2
31.75
SN74LV245ATPWR
PW
20
MLA
342.9
336.6
28.58
SN74LV245ATRGYR
RGY
20
MLA
190.0
212.7
31.75
Pack Materials-Page 2
19-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
08
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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