Co-requisite:

Prerequisite:
Data Book /
Codes/Standards
Course Category
Course designed by
Approval
Sessio
n
1.

NIL
P
PROFESSIONAL CORE
Department of Information Technology
-- Academic Council Meeting -- , 2016
Contac
t hours

Description of Topic (Theory)

UNIT I: DIGITAL DATA REPRESENTATION

Introduction to Number Systems, Number Base Conversions

Signed number representation, fixed

representations, character representation

3.

Logical operations using gates, logic expression minimization

and

floating

point

UNIT II: ARITHMETIC OPERATIONS AND LOGIC

CIRCUITS

Multiplication-shift-and-add, Booth multiplier, carry save

multiplier

Cycle Test-I

Division-non-restoring and restoring techniques, floating point

arithmetic

Combinational circuits and flip-flops

UNIT III: FUNCTIONAL BLOCKS OF A COMPUTER

CPU, Memory, Input-Output subsystems, Control unit

11.

12.

Referenc
e

1,3

1,3

C,I

1,3

1,5

1,5

1,5

1,5

C,I

5.

10. . Instruction set architecture

of a CPU-registers, Instruction execution cycle, RTL interpretation of
instructions

IO
s

10
2

9.

C,I

Computer arithmetic-integer addition and subtraction, ripple carry

adder, carry look-ahead adder

8.

C-DI-O

C,I

4.

7.

P
2

NIL
NIL

2.

6.

L T
3 0

COMPUTER ORGANIZATION AND ARCHITECTURE

SYLLABUS

15IT212J

C,I

C,I
C,D,
I
C
C
2
C

Addressing modes, Instruction set

Cycle Test-II

13. Hardwired and micro-programmed design approaches. Case study

Design of a simple hypothetical CPU2. Instruction sets of some
common CPUs
UNIT IV: PERIPHERAL DEVICES AND THEIR
CHARACTERISTICS

C,D
3

C
4

14. Input-output Subsystems, I/O Transfers-program controlled, interrupt

driven and DMA, Privileged and Non-privileged instructions,
Software Interrupts and Exceptions

15. Programs and Processes-Role of interrupts in process state

Transitions

16. Concept of hierarchical memory organization and description of

various memories (Limited Scope).

UNIT V: OPTIMIZATION OF PROCESSOR PERFORMANCE

17. Basic concepts of pipelining, throughput and speedup, Pipeline
hazards
18.
Understanding modern processors
19.

Reducing loop overhead

20. Fundamentals of parallel computer architecture (Limited Scope)Enhancing parallelism

21.
Cycle Test-III

C
C

1,4

9
2
2
2
3

C
C
C
C

Total contact hours

Sl.
No.
1.

45

LEARNING RESOURCES
M.Morris Mano ,Computer System Architecture,Pearson Education,3 rd Edition 2007

2.

R.E.Bryant, D.R.OHallaron, Computer Systems- A Programmers Perspective, 2 ND Edition, 2010

3.

William Stallings,Computer Organization and Architecture: Designing for Performance,Prentice Hall of

India, 9th Edition, 2012.

4.

John.P.Hayes, Computer Architecture and Organization, McGraw Hill, Third Edition,2012

5.

Carl Hamachar,Zvoncovranesic and Safwatzaky,Computer Organization,McGraw Hill, 5 th Edition, 2002.

Course nature
Theory + Practical
Assessment Method Theory Component (Weightage 50%)
Assessment tool Cycle test I Cycle test II Cycle Test III Surprise Test
Quiz
In-semester
Weightage
10%
15%
15%
5%
5%
End semester examination Weightage :
Assessment Method Practical Component (Weightage 50%)
Assessment
Model
Experiments
Record
MCQ/Quiz/Viva Voce
In-semester
tool
examination
Weightage
40%
5%
5%
10%
End semester examination Weightage :

Total
50%
50%

Total
60%
40%