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Horia Cucu Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology
Horia Cucu Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology
Horia Cucu Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology
Horia Cucu Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology
Horia Cucu Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology

Horia Cucu

Speech & Dialogue Research Laboratory Faculty of Electronics, Telecommunications and Information Technology

University POLITEHNICA of Bucharest

1.1 Example #1
1.1 Example #1
1.1 Example #1
1.1 Example #1
1.1 Example #1

1.1 Example #1

Overview of a CISC, General Purpose Microprocessor Core  General Purpose Registers (GPRs)  Memory

Overview of a CISC, General Purpose

Microprocessor Core

Overview of a CISC, General Purpose Microprocessor Core  General Purpose Registers (GPRs)  Memory Data
Overview of a CISC, General Purpose Microprocessor Core  General Purpose Registers (GPRs)  Memory Data

General Purpose Registers (GPRs)

Memory Data Register (DR)

Memory Address Registers (AR)

Arithmetic and Logic Unit (ALU)

Memory Addressing Control Unit

Timing and Control Unit (TCU)

Instruction Execution Timing Premises  Busses  8-bit internal and external data bus  16-bit

Instruction Execution Timing

Premises

Instruction Execution Timing Premises  Busses  8-bit internal and external data bus  16-bit external

Busses

8-bit internal and external data bus

16-bit external address bus

Memory

Linear memory organization

16-bit physical addresses

8-bit memory locations

Registers

addresses  8-bit memory locations  Registers  8- bit, general purpose registers: R1, …, R6;

8-bit, general purpose registers: R1, …, R6; can be concatenated

8-bit special function registers: A (accumulator), F (flags), DR

(data reg), IR (instruction reg), ATEMP, TEMP, AUX1, AUX2

16-bit special function registers: PC, SP, IX, RA

Instruction Execution Timing Example  Instruction example: (2000h) <- (2000h) + 50h  Instruction format:

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (2000h) <- (2000h) + 50h  Instruction format: 

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand 1

M5. Read operand 2 and Execute

M6. Write result

Machine Cycle 1: Fetch  Instruction example: (2000h) <- (2000h) + 50h  Instruction format:

Machine Cycle 1: Fetch

Machine Cycle 1: Fetch  Instruction example: (2000h) <- (2000h) + 50h  Instruction format: 

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand 1

M5. Read operand 2 and Execute

M6. Write result

Machine Cycle 1: Fetch  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 8

Machine Cycle 1: Fetch

Machine Cycle 1: Fetch  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 8
Machine Cycle 1: Fetch  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 8

T1. (AR) <- (PC), MEM-READ

Machine Cycle 1: Fetch  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016

Machine Cycle 1: Fetch

Machine Cycle 1: Fetch  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016 Microprocessors
Machine Cycle 1: Fetch  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016 Microprocessors

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 1: Fetch  T3. (IR) <- (DR) 27.05.2016 Microprocessors Architecture 10

Machine Cycle 1: Fetch

Machine Cycle 1: Fetch  T3. (IR) <- (DR) 27.05.2016 Microprocessors Architecture 10
Machine Cycle 1: Fetch  T3. (IR) <- (DR) 27.05.2016 Microprocessors Architecture 10

T3. (IR) <- (DR)

Machine Cycle 1: Fetch  T4. decode instruction code 27.05.2016 Microprocessors Architecture 11

Machine Cycle 1: Fetch

Machine Cycle 1: Fetch  T4. decode instruction code 27.05.2016 Microprocessors Architecture 11
Machine Cycle 1: Fetch  T4. decode instruction code 27.05.2016 Microprocessors Architecture 11

T4. decode instruction code

Machine Cycle 2: Read Address  Instruction example: (2000h) <- (2000h) + 50h  Instruction

Machine Cycle 2: Read Address

Machine Cycle 2: Read Address  Instruction example: (2000h) <- (2000h) + 50h  Instruction format:

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX2) <- (DR)

M3. Read address (most significant byte)

M4. Read operand 1

M5. Read operand 2 and Execute

M6. Write result

Machine Cycle 2: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 13

Machine Cycle 2: Read Address

Machine Cycle 2: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 13
Machine Cycle 2: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 13

T1. (AR) <- (PC), MEM-READ

Machine Cycle 2: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 2: Read Address

Machine Cycle 2: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016
Machine Cycle 2: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 2: Read Address  T3. (AUX2) <- (DR) 27.05.2016 Microprocessors Architecture 15

Machine Cycle 2: Read Address

Machine Cycle 2: Read Address  T3. (AUX2) <- (DR) 27.05.2016 Microprocessors Architecture 15
Machine Cycle 2: Read Address  T3. (AUX2) <- (DR) 27.05.2016 Microprocessors Architecture 15

T3. (AUX2) <- (DR)

Machine Cycle 3: Read Address  Instruction example: (2000h) <- (2000h) + 50h  Instruction

Machine Cycle 3: Read Address

Machine Cycle 3: Read Address  Instruction example: (2000h) <- (2000h) + 50h  Instruction format:

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX1) <- (DR)

M4. Read operand 1

M5. Read operand 2 and Execute

M6. Write result

Machine Cycle 3: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 17

Machine Cycle 3: Read Address

Machine Cycle 3: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 17
Machine Cycle 3: Read Address  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 17

T1. (AR) <- (PC), MEM-READ

Machine Cycle 3: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 3: Read Address

Machine Cycle 3: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016
Machine Cycle 3: Read Address  T2. (PC) <- (PC) + 1, (DR) <- ((AR)) 27.05.2016

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 3: Read Address  T3. (AUX1) <- (DR) 27.05.2016 Microprocessors Architecture 19

Machine Cycle 3: Read Address

Machine Cycle 3: Read Address  T3. (AUX1) <- (DR) 27.05.2016 Microprocessors Architecture 19
Machine Cycle 3: Read Address  T3. (AUX1) <- (DR) 27.05.2016 Microprocessors Architecture 19

T3. (AUX1) <- (DR)

Machine Cycle 4: Read Operand 1  Instruction example: (2000h) <- (2000h) + 50h 

Machine Cycle 4: Read Operand 1

Machine Cycle 4: Read Operand 1  Instruction example: (2000h) <- (2000h) + 50h  Instruction

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand 1

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (A) <- (DR)

M5. Read operand 2 and Execute

M6. Write result

Machine Cycle 4: Read Operand 1  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture

Machine Cycle 4: Read Operand 1

Machine Cycle 4: Read Operand 1  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 21
Machine Cycle 4: Read Operand 1  T1. (AR) <- (PC), MEM-READ 27.05.2016 Microprocessors Architecture 21

T1. (AR) <- (PC), MEM-READ

Machine Cycle 4: Read Operand 1  T2. (PC) <- (PC) + 1, (DR) <-

Machine Cycle 4: Read Operand 1

Machine Cycle 4: Read Operand 1  T2. (PC) <- (PC) + 1, (DR) <- ((AR))
Machine Cycle 4: Read Operand 1  T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

Machine Cycle 4: Read Operand 1  T3. (A) <- (DR) 27.05.2016 Microprocessors Architecture 23

Machine Cycle 4: Read Operand 1

Machine Cycle 4: Read Operand 1  T3. (A) <- (DR) 27.05.2016 Microprocessors Architecture 23
Machine Cycle 4: Read Operand 1  T3. (A) <- (DR) 27.05.2016 Microprocessors Architecture 23

T3. (A) <- (DR)

Machine cycle 5: Read operand 2 and Execute  Instruction example: (2000h) <- (2000h) +

Machine cycle 5: Read operand 2 and Execute

Machine cycle 5: Read operand 2 and Execute  Instruction example: (2000h) <- (2000h) + 50h

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand 1

M5. Read operand 2 and Execute

T1. (AR) <- (AUX1, AUX2), MEM-READ

T2. (DR) <- ((AR))

T3. (A) <- (A) + (DR)

M6. Write result

Machine cycle 5: Read operand 2 and Execute  T1. (AR) <- (AUX1, AUX2), MEM-READ

Machine cycle 5: Read operand 2 and Execute

Machine cycle 5: Read operand 2 and Execute  T1. (AR) <- (AUX1, AUX2), MEM-READ 27.05.2016
Machine cycle 5: Read operand 2 and Execute  T1. (AR) <- (AUX1, AUX2), MEM-READ 27.05.2016

T1. (AR) <- (AUX1, AUX2), MEM-READ

Machine cycle 5: Read operand 2 and Execute  T2. (DR) <- ((AR)) 27.05.2016 Microprocessors

Machine cycle 5: Read operand 2 and Execute

Machine cycle 5: Read operand 2 and Execute  T2. (DR) <- ((AR)) 27.05.2016 Microprocessors Architecture
Machine cycle 5: Read operand 2 and Execute  T2. (DR) <- ((AR)) 27.05.2016 Microprocessors Architecture

T2. (DR) <- ((AR))

Machine cycle 5: Read operand 2 and Execute  T3. (A) <- (A) + (DR)

Machine cycle 5: Read operand 2 and Execute

Machine cycle 5: Read operand 2 and Execute  T3. (A) <- (A) + (DR) 27.05.2016
Machine cycle 5: Read operand 2 and Execute  T3. (A) <- (A) + (DR) 27.05.2016

T3. (A) <- (A) + (DR)

Machine Cycle 6: Write Result  Instruction example: (2000h) <- (2000h) + 50h  Instruction

Machine Cycle 6: Write Result

Machine Cycle 6: Write Result  Instruction example: (2000h) <- (2000h) + 50h  Instruction format:

Instruction example: (2000h) <- (2000h) + 50h

Instruction format:

6 machine cycles:

 

code

addr low

addr high

data

 

(00h)

(20h)

(50h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand 1

M5. Read operand 2 and Execute

M6. Write result

T1. (DR) <- (A)

T2. (AR) <- (AUX1, AUX2), MEM-WRITE

Machine Cycle 6: Write Result  T1. (DR) <- (A) 27.05.2016 Microprocessors Architecture 29

Machine Cycle 6: Write Result

Machine Cycle 6: Write Result  T1. (DR) <- (A) 27.05.2016 Microprocessors Architecture 29
Machine Cycle 6: Write Result  T1. (DR) <- (A) 27.05.2016 Microprocessors Architecture 29

T1. (DR) <- (A)

Machine Cycle 6: Write Result  T2. (AR) <- (AUX1, AUX2), MEM-WRITE 27.05.2016 Microprocessors Architecture

Machine Cycle 6: Write Result

Machine Cycle 6: Write Result  T2. (AR) <- (AUX1, AUX2), MEM-WRITE 27.05.2016 Microprocessors Architecture 30
Machine Cycle 6: Write Result  T2. (AR) <- (AUX1, AUX2), MEM-WRITE 27.05.2016 Microprocessors Architecture 30

T2. (AR) <- (AUX1, AUX2), MEM-WRITE

1.2 Example #2
1.2 Example #2
1.2 Example #2
1.2 Example #2
1.2 Example #2

1.2 Example #2

Instruction Execution Timing Example  Instruction example: (R1) <- (R3)  Instruction format:  1

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (R1) <- (R3)  Instruction format:  1 machine

Instruction example: (R1) <- (R3)

Instruction format:

1 machine cycle:

code

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

Execute

T1. (TEMP) <- (R3)

T2. (R1) <- (TEMP)

1.3 Example #3
1.3 Example #3
1.3 Example #3
1.3 Example #3
1.3 Example #3

1.3 Example #3

Instruction Execution Timing Example  Instruction example: (A) <- (A) + (R1)  Instruction format:

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (A) + (R1)  Instruction format: 

Instruction example: (A) <- (A) + (R1)

Instruction format:

1 machine cycle:

code

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

Execute

T1. (TEMP) <- (R1), (ATEMP) <- (A)

T2. (A) <- (ATEMP) + (TEMP)

1.4 Example #4
1.4 Example #4
1.4 Example #4
1.4 Example #4
1.4 Example #4

1.4 Example #4

Instruction Execution Timing Example  Instruction example: (A) <- (A) + ((R5, R6))  Instruction

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (A) + ((R5, R6))  Instruction format:

Instruction example: (A) <- (A) + ((R5, R6))

Instruction format:

3 machine cycles:

code

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

M2. Read operand

T1. (AR) <- (R5, R6), MEM-READ

T2. (DR) <- ((AR))

T3. (TEMP) <- (RD), (ATEMP) <- (A)

M3. Execute

(A) <- (ATEMP) + (TEMP)

1.5 Example #5
1.5 Example #5
1.5 Example #5
1.5 Example #5
1.5 Example #5

1.5 Example #5

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4 machine

Instruction example: (A) <- (2000h)

Instruction format:

4 machine cycles:

 

code

addr low

addr high

   

(00h)

(20h)

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4 machine

Instruction example: (A) <- (2000h)

Instruction format:

4 machine cycles:

 

code

addr low

addr high

   

(00h)

(20h)

M1. Fetch and Decode

M2. Read address (least significant byte)

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX2) <- (RD)

M3. Read address (most significant byte)

M4. Read operand

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4 machine

Instruction example: (A) <- (2000h)

Instruction format:

4 machine cycles:

 

code

addr low

addr high

   

(00h)

(20h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX1) <- (RD)

M4. Read operand

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (A) <- (2000h)  Instruction format:  4 machine

Instruction example: (A) <- (2000h)

Instruction format:

4 machine cycles:

 

code

addr low

addr high

   

(00h)

(20h)

M1. Fetch and Decode

M2. Read address (least significant byte)

M3. Read address (most significant byte)

M4. Read operand

T1. (AR) <- (AUX1, AUX2), MEM-READ

T2. (DR) <- ((AR))

T3. (A) <- (RD)

1.6 Example #6
1.6 Example #6
1.6 Example #6
1.6 Example #6
1.6 Example #6

1.6 Example #6

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3 machine

Instruction example: (PC) <- 0100h

Instruction format:

3 machine cycles:

 

code

data low

data high

   

(00h)

(01h)

M1. Fetch and Decode

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (IR) <- (DR)

T4. decode instruction code

M2. Read data (least significant byte)

M3. Read data (most significant byte) and Execute

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3 machine

Instruction example: (PC) <- 0100h

Instruction format:

3 machine cycles:

 

code

addr low

addr high

   

(00h)

(01h)

M1. Fetch and Decode

M2. Read data(least significant byte)

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX2) <- (RD)

M3. Read data (most significant byte) and Execute

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3

Instruction Execution Timing Example

Instruction Execution Timing Example  Instruction example: (PC) <- 0100h  Instruction format:  3 machine

Instruction example: (PC) <- 0100h

Instruction format:

3 machine cycles:

 

code

addr low

addr high

   

(00h)

(01h)

M1. Fetch and Decode

M2. Read data (least significant byte)

M3. Read data (most significant byte) and Execute

T1. (AR) <- (PC), MEM-READ

T2. (PC) <- (PC) + 1, (DR) <- ((AR))

T3. (AUX1) <- (RD)

T4. (PC) <- (AUX1, AUX2)