Design of Programmable Frequency Synthesizer for Remote sensing

Satellite Data reception System

Guda Uma Shanker

G.Uma Devi

Sreenidhi Institute of Science and Technology

Hyderabad, Andhra Pradesh, India
umashanker.guda@gmail.com

Head BSD/SDRS/SDAPSA
NRSC, India
umadevi_g@nrsc.gov.in

Tarun Kumar Kasturi

Radha Nayani,

Sreenidhi Institute of Science and Technology

Hyderabad, Andhra Pradesh, India

Engineer-SF, BSD/SDRS
NRSC, India
radhakgr@yahoo.com

tarunkumar.kasturi@gmail.com
V. Sai Kiranmayi
National Institute of Technology, Warangal,
Andhra Pradesh, India
sai.kiranmayi16@gmail.com

Abhijit Patil Tanaji

Engineer -SC , BSD/SDRS
NRSC, India
abhi001jit@gmail.com

Abstract Phase Locked Loop (PLL) technique

Synthesizer (FS) works as a local oscillator for up

conversion and down conversion of modulated
signals. The FS basically generates the required
range of frequencies from one or more reference
generators. Frequency Synthesizers are relatively
inexpensive and can be easily controlled by digital
circuitry. The frequency of oscillators in RF range
must be defined with absolute accuracy and the
variation in frequency needs to be small and
precise. Thus, the error in the output frequency
must be optimum. Frequency synthesizer plays a
crucial role in a transceiver. Apart from accuracy,
other factors affecting the performance of the
transceiver include phase noise, spurs, jitters,
settling time and lock time. Hence, the frequency
synthesizer must be designed such that it has
optimum phase noise and low settling time with low
spurs.

plays a key role in the realization of many

telecommunication systems and is the basic
building block of most of the Coherent receivers
in the satellite communications systems. PLL
forms an integral part of Frequency Synthesizer
circuits.
The
conventional
frequency
synthesizers have considerable phase noise and
are quite bulky. Phase noise degrades the
quality of the data in a communication system.
The power requirement and the costs involved
in the design of the conventional frequency
synthesizers are very high and the circuitry used
in the design is also quite complex. This paper
presents a design which improves the phase
noise
performance
significantly,
besides
providing flexibility and adaptability to suit
various applications. It also proves to be a
compact and cost-effective solution.
The
proposed design makes use of dual-loop
analog-digital hybrid PLL architecture to
achieve the desired objectives. In this design
approach, the RMS noise, jitter and spurs are
also reduced which enhances the performance of
the Frequency Synthesizer. Experimental results
to prove the feasibility of the technique in order
to overcome the above mentioned shortcomings
are also presented.
Keywords-Frequency Synthesizer, PLL

I.

INTRODUCTION

The field of communications has grown

considerably in the past few decades, inevitably
leading to a number of high performance
applications that can be completely integrated with
low cost technology. PLL is extensively used for
wireless applications in which the frequency
II.
Design
concepts
Continuous upgrade in the VLSI domain
has
simplified
the
realization
and
implementation of PLLs with state-of the art

Fig.1
RF Transceiver

The constituents of t h e paper are presented as

follows. Segment II deals with the design concepts,
segment III describes basic principles of PLL
technique and segment IV explains the proposed
technique. Experimental verification is presented in
segment V and segment VI concludes the paper.
techniques. Though there are plenty of applications with
Frequency Synthesizer and PLL, they do have some
constraints like, phase noise, settling time bandwidth and
power dissipation. Frequency synthesizer can be
designed using any of the three conventional techniques

viz. Direct analog (DA), Direct digital

synthesis (DDS), Phase-locked loop synthesis
(PLL). DA synthesis techniques are very
wideband and offer good switching speed and
excellent spectral purity. However, it is bulky,
expensive when compared to PLL. Direct
Digital Synthesizers have limited bandwidth.
They have simple circuitry and are compact.
Thus, frequency synthesizers are designed
using a PLL circuit p r i m a r i l y b e c a u s e
of the advantages it provides
such
as
because it offers many
advantages such as Signal-to-Noise ratio
(SNR) improvement, low phase noise, better
frequency control and phase control,
significantly low power consumption and easy
realization using VLSI technology.
Current paper mainly focuses on design
and implementation of frequency synthesizer
with optimum phase noise, relatively good
bandwidth and low power consumption. The
proposed design is compared with the
conventional FS and the merits of the former
are analyzed accordingly.

Fig. 2. Block diagram of PLL

High quality synthesizer employs multiple

loops and dividers as a means to remove
spurious signals. The mathematical equation
for PLL is given below

Where flicker noise

, flat noise and

integer noise are dependent on the N

value and the resistors value of the loop
filter

III. BASIC PRINCIPLES OF PLL

PLL is extensively used in the design of the
present-day circuits. PLL adopts the feedback
path in the circuit to lock or match the phase
of the input signal in proportion with the phase
of the output signal. The phase of the output
signal is compared with the phase of the
input signal by the phase detector. Any
difference is phase is compensated by the
output voltage produced by the PLL, which
commensurate with the phase error between
the input and the output signals. The phase
error is corrected by the voltage controlled
oscillator (VCO) which controls the output
frequency. Consequently, the input and the
output signal will be in-phase and are said
to locked or synchronized. Thus, the phase
error between the two signals is completely,
or almost eliminated. Frequency synthesizer
performs operations of multiplication or
division on the reference input (fi/p) of
frequency synthesizer, to generate required
output frequency (f0/p). This implies that

The delta sigma modulator does not add as much

phase noise as compared to the traditional
fractional N PLL because the latter uses analog
delays to compensate for the fractional spurs and
the delta sigma PLLs are digitally programmable
and reduce primary fractional spurs. The fractional
spurs can also be reduced by introducing dithering
into the system which results in the removal of
quantization noise and fractional spurs.

The PLL noise equation infers that larger the

N value, larger will be the phase noise, flat
noise and flicker noise. Hence N value must
be reduced, keeping the output frequency at
the desired levels. The fractional N PLL can
be used to achieve this objective and is
implemented with the help of traditional N
PLL and delta sigma N PLL. By
implementing the fractional N PLL,
fractional spurs are introduced. For the
traditional
fractional
PLL,
analog
compensation is used to reduce the fractional
spurs. Delta sigma PLLs aim to reduce spurs
using digital techniques so that there is
minimal added phase noise and the fractional
spurs are reduced even lower. For a
traditional N PLL or a delta sigma PLL, the
N counter value is defined by

For a delta sigma N

PLL,

IV. PROPOSED DESIGN

Ref.Clo
ck

Clock
Jitter
Clean
er

Programm
able
Frequency
synthesize
r
Control
Logic

Fig .5. Block diagram of proposed design

The proposed design basically consists of a

reference clock source, clock jitter cleaner,
programmable frequency synthesizer and control
logic circuitry . The jitter cleaner removes spurious
signals and provides a stable, clean reference clock
to the frequency synthesizer to generate a range of
desired frequencies. The control logic consists of a
micro controller based circuitry to support
configurability
and
facilitate
remote
programmability through Ethernet interface.

CLOCK
CLEANER
Fig.3. Delta Sigma N PLL

If we assume that the quantizer output is uniformly

distributed, then the spectral density of an nth order
delta sigma modulator is given below

But theoretically, the quantization noise achieves

maximum value exactly at the half the phase
detector frequency. The order of the loop filter is
directly proportional to the order of the delta sigma.
Another way of reducing the fractional and sub
fractional spurs is by introducing dithering. When
dithering is used, the noise is found to be more
randomized.

Fig. 4. Effect of Dithering on First Spur

very important contributor to the final phase noise

of the system.
A. FREQUENCY SYNTHESIZER

JITTER

Jitter is the deviation from the ideal timing of an

event. Random Jitter comes from thermal
vibrations of semiconductor crystal structure
causing mobility to vary depending on
instantaneous temperature of material. Deviation
can occur on either the leading edge or the trailing
edge of a signal. Jitter may be induced and coupled
onto a clock signal from several different sources
and is not uniform over all frequencies. Excessive
jitter can increase the bit error rate (BER) of a
communications signal by incorrectly transmitting
a data bit stream. In digital systems, jitter can lead
to a violation of timing margins, causing circuits to
behave improperly. Accurate measurement of jitter
is necessary for ensuring the reliability of a system.
A clock receives an input frequency from a source
and either distributes that frequency or generates
new frequencies to send as outputs to other devices
within the system. Non-PLL clocks are used when
the time delay between source and output, known
as a propagation delay, is not important to the
system. PLL Clocks are used when the system
needs to minimize the propagation delay. PLLs
allow a clock to eliminate propagation delay and
allow phase adjustments .PLL also removes noise
from the reference clock with jitter cleaning. Hence
any PLL-based clock that cleans the noises from
the reference clock and provides a clean and
synchronized signal for the receivers uses an
external VCO (VCXO) or internal VCO. It consists
of dual PLL architecture. Two stage jitter cleaning
process involves masking the reference noise with
a VCXO or Crystal. Therefore the phase noise
performance of the VCXO or Crystal of PLL1 is a
Fig. 6. Block Diagram of Frequency
Synthesizer

A frequency synthesizer is a device for

generating any of a range of frequencies
from
a
single fixed oscillator. A phase
locked loop, PLL, needs some additional
circuitry if it is to be converted into a
frequency synthesizer. It involves placing a
digital divider in the loop between the voltage
controlled oscillator. This means that the
voltage controlled oscillator frequency will be

divided by the division ratio of the divider, e.g.

n, and the VCO will run at n times the phase
comparison frequency. By changing the division
ratio of the divider, the output frequency of the
oscillator can be changed. This makes the
frequency synthesizer programmable. Phase noise
is generated at different points around the
synthesizer loop and depending upon where it is
generated it affects the output in different ways.
Thus, it is necessary to look at the noise
performance of each circuit block in the loop when
designing the synthesizer so that the best noise
performance is obtained
.

Fig. 7. Frequency Synthesizer

The phase detector block compares an incoming

signals phase to that of the reference and generates
an output signal that is a function of the phase
difference. This signal is conditioned by a loop
filter before reaching the voltage controlled
oscillator (VCO), which is an oscillator that
produces an output at some frequency that is a

function of the input voltage. The divider blocks, N

and M, allow for the synthesis of different
frequencies. They are related by:

By adjusting the M divide factor, different output

frequencies can be obtained. Fractional spurs at the
VCO are independent of VCO frequency, but when
the VCO frequency is divided down by a factor ,
the fractional spurs improve. Also, the fractional
channel spacing can be made wider at the VCO,
which makes the fractional spurs farther from the
carrier. The fractional noise of the modulator is
divided down in a similar way as fractional
spurs. For an integrated wideband PLL in SiGe
BiCMOS technology the spur power levels are
measured and compared with theoretical
expectations. The power in these spurs is
minimized by layout techniques shielding the
reference input buffer. Spur minimization using
variable reference frequency is experimented and
hence it is concluded that a programmable integerN PLL for driving the fractional-N synthesizer is
suggested to reduce the worst-case spur level
significantly.
V. EXPERIMENTAL RESULTS
The proposed design was implemented using LMX
2541and tested. The following output plots were
found on the spectrum analyzer.
The figure shown below is the spectrum analyzer
output plot at a centre frequency of 2.9 GHz. No inband spurs are found even at 0 dB attenuation and a
reference level of -10 dB. The practical results were
compared with the conventional synthesized signal
generator performance and found to emulate the
performance satisfactorily.

Fig.8. Spectrum Analyzer Output Plot at 2.9 GHz

The figure below shows the phase noise plot at a

centre frequency of 2.9 GHz. At a n o f f s e t o f
100 KHz, the phase noise was found to be
approximately -110 dBc/Hz

Fig. 9 Phase Noise plot

VI. CONCLUSION
In this paper, the proposed Programmable
frequency synthesizer has been designed and
implemented, with all the key design parameters
being programmable and it is aimed at usage in
the remote sensing ground station for down
conversion of RF signals to the desired IF band.
The frequency synthesizer has low phase noise and
the results are verified experimentally and
compared with the conventional designs. The
complexity in the circuit is also reduced
considerably. The proposed frequency synthesizer
not only reduces the size of the circuit, but also
proves to be a cost effective, high performance
device.
VIII. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]

Bar-Giora Goldberg, Digital Frequency Synthesis

Demystified
Texas Instruments User Guide
Micheal H.Perrot, Digital Phase looked loops
Gursharan Reehal, A Digital Frequency Synthesizer
Using Phase Locked Loop Technique
A. David Williams, A new Frequency Synthesizer
for Satellite Communications in Ku band
Sung Tae Moon,Ari Yakov Valero-Lopez,Edgar
Sanchez-Sinencio,Fully Integrated Frequency
Synthesizers: A tutorial