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28072016001
1. An OR gate has 4 inputs. One input is high and the other three are low. The output
A) is low
B) is high
C) is alternatively high and low
D) may be high or low
depending upon relative magnitude of inputs
2. A device which converts BCD to seven segment is call
A) Encoder
B) Decoder
C) Multiplexer
D) None
3. A decade counter skips binary states
A) 1000 to 1111
B) 0000 to 0011
C) 1010 to 1111
D)1111 to higher
Explnation: A decade counter counts from 0 to 9. It has 4 flip-flops. The states skipped are 10 to 15
or 1010 to 1111.
C) 32 states
D) infinite states
5. Explanation:
If A = 0, Y = 1 and A = 1, Y = 0
Therefore Y = A.
A) 0
B) 1
C) A
D) A
6. In the expression the total number of minterms will be
A) 2
B) 3
C) 4
D) 5
7. The circuit in the given figure is
6. Explanation:
The min terms are ABC + ABC +
AB C + ABC + ABC.
7. Explanation:
Since V(1) is lower state than V(0) it is a negative logic circuit.
Since diodes are in parallel, it is an OR gate.
A) Y=(A+B) C + DE
B)Y= A+B+C+D+E
C) 1476
D) 12166
11. The greatest negative number which can be stored is 8 bit computer using 2s complement
arithmetic is
A) -256
B) -128
C) -255
D) -127
12. The basic storage element in a digital system is
A) Flipflop B) Counter
C) Multiplexer
D) Encoder
13. In a ripple counter
A) Whenever a flipflop sets to 1, the next higher FF toggles
B) Whenever a flipflop sets to 0, the next higher FF remains unchanged
C) Whenever a flipflop sets to 1, the next higher FF faces race condition
D) Whenever a flipflop sets to 0, the next higher FF faces race condition
14. A Full adder can be made out of
A) 2 half adders
B) 2 half adders and a OR gate
18. Explanation:In
ahead
adder
is directly
C) 2 half look
adders
andcarry
a NOT
gatethe carry
D) three
half derived
adders from the gates when original inputs
are being added. Hence the addition is fast. This process requires more gates and is costly.
A) Mod 3
B) Mod 6
C) Mod 8
D)Mod 7
20. AB + AB
20. Explanation:
A) B
B) A
C) 1
D) 0
AB + AB = A(B + B) = A . 1 = A.
21. Max term designation for A+B+C is
A) M0
B) M1
C) M2
D) M3
22. In a D latch
A) Data bit D is fed to S input and D to R input
B) Data bit D is fed to R input and D to S input
23. Explanation:
C) Data bit D is fed to both R and S inputs
22 = 4. Hence 2 select lines.
D) Data bit D is not fed to any input
23. A 4:1 multiplexer requires _______ data select lines
E) 1
B) 2
C) 3
D) 4
24. Explanation:
24. The number of un used states in Johnson counter is
Total state = 2n = 24 = 16
A) 2
B) 4
C) 8
D) 12
Used state = 2n = 2 x 4 = 8
25. A Karnaugh map with 4 variables has
A) 2 cells
B) 4 cells
C) 8 cells
D) 16 cells Unused state = 16 - 8 = 8.
26. An 8 bit data is to be entered into a parallel in register. The number of clock pulses required A) 8
B)4
C)2
D)1
27. Which of the following is error correcting code
A) EBCDIC
B) Grey
C) Hamming
D) ASCII
28. A universal shift register can shift
A) From left to right B) from right to left C) both a and b
D) none
29. A XOR gate has inputs A and B and output Y, then the output equation is
A) Y=AB
B) Y=AB+AB
C) Y=AB+AB
D) Y=AB+AB
30. The Boolean expression for the circuit given below figure is
A) S, R, J, K only
B) S, R, Preset, Clear only C) Preset, Clear only D) S, R only
33. Which if these are two state devices
A) Lamp
B) Punched card
C) Magnetic tape
D) All of the above
34. The minimum number of NAND gates required to implement the Boolean function A+AB+ABC
A) 0
B) 1
C) 4
D) 7
35. For the K map of the given figure, the simplified Boolean expression is
A C + A D + ABC