Fundamentals of Data

Converters
DAVID KRESS
Director of Technical Marketing

9/14/2016

Analog to Electronic Signal Processing

Sensor
(INPUT)

Actuator
(OUTPUT)

Amp

Amp

Converter

Converter

Digital Processor

Analog to Electronic Signal Processing

Sensor
(INPUT)

Actuator
(OUTPUT)

Amp

Amp

Converter

Converter

Digital Processor

Outline
Sampled

data system types

Digitizing

processes

Data

converters for measurement systems and errors

Data

converters for dynamic systems and errors

Sampling

system problems

Structure

and use of digital-analog converters

Structure

and use of analog-digital converters

Many Types of Sampled Data Systems

Analog
Digital

to digital converters

Samples

to analog converters

Domain

Sample
Peak

and hold amplifiers

detectors

Comparators
Switched

cap filters

a continuous signal

conversion

Analog to digital
Digital to analog
Continuous time to discrete time
Continuous frequency to
discrete frequency

Sampling

rate

Continuous, discontinuous

Analog and Digital Domains

Why Convert to Digital?
Analog
Digital
Why

signals are continuous and provide the entire signal

signals capture only a portion of the signal

digitize?

Improved signal analysis potential

More robust storage
More accurate transmission
Development

objective of sampled data systems is to minimize

effect of the sampling process

Sampled Data System: Sampling and Quantization

fs

fa

LPF
OR
BPF

N-BIT
ADC

AMPLITUDE
QUANTIZATION

fs

DSP

LPF
OR
BPF

N-BIT
DAC

DISCRETE
TIME SAMPLING

fa

ts= f
s
t

Transfer Functions for Ideal 3-Bit DAC and ADC

DAC

ADC

FS
111
110

DIGITAL
OUTPUT

ANALOG
OUTPUT

101
100
011

QUANTIZATION
UNCERTAINTY
010

QUANTIZATION
UNCERTAINTY

001
000

000

001

010

011

100

101

DIGITAL INPUT

110

111

ANALOG INPUT

FS

Unipolar Binary Code, 4-bit Converter

BASE 10
NUMBER
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
0

SCALE
+FS 1 LSB = 15/16 FS
+7/8 FS
+13/16 FS
+3/4 FS
+11/16 FS
+5/16 FS
+9/16 FS
+1/2 FS
+7/16 FS
+3/8 FS
+5/16 FS
+1/4 FS
+3/16 FS
+1/8 FS
1 LSB = +1/16 FS
0

+10 V FS

BINARY

9.375
8.750
8.125
7.500
6.875
6.250
5.625
5.000
4.375
3.750
3.125
2.500
1.875
1.250
0.625
0.000

1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

Bipolar Codes, 4-bit Converter

BASE 10
NUMBER

SCALE

5V FS

OFFSET
BINARY

TWOS
COMP.

+7
+6
+5
+4
+3
+2
+1
0
1
2
3
4
5
6
7
8

+FS 1LSB = +7/8 FS

+3/4 FS
+5/8 FS
+1/2 FS
+3/8 FS
+1/4 FS
+1/8 FS
0
1/8 FS
1/4 FS
3/8 FS
1/2 FS
5/8 FS
3/4 FS
FS + 1LSB = 7/8 FS
FS

+4.375
+3.750
+3.125
+2.500
+1.875
+1.250
+0.625
0.000
0.625
1.250
1.875
2.500
3.125
3.750
4.375
5.000

1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000

CODES NOT NORMALLY USED

IN COMPUTATIONS (SEE TEXT)

0+
0

ONES
COMP.

0111
0110
0101
0100
0011
0010
0001
*0 0 0 0
1110
1101
1100
1011
1010
1001
1000
ONES
COMP.
0000
1111

SIGN
MAG.

0111
0110
0101
0100
0011
0010
0001
*1 0 0 0
1001
1010
1011
1100
1101
1110
1111
SIGN
MAG.
0000
1000

Quantization: The Size of a Least Significant Bit (LSB)

RESOLUTION
N

VOLTAGE
(10V FS)

ppm FS

% FS

dB FS

2N

2-bit

2.5 V

250,000

25

12

4-bit

16

625 mV

62,500

6.25

24

6-bit

64

156 mV

15,625

1.56

36

8-bit

256

39.1 mV

3,906

0.39

48

10-bit

1,024

9.77 mV (10 mV)

977

0.098

60

12-bit

4,096

2.44 mV

244

0.024

72

14-bit

16,384

610 V

61

0.0061

84

16-bit

65,536

153 V

15

0.0015

96

18-bit

262,144

38 V

0.0004

108

20-bit

1,048,576

9.54 V (10 V)

0.0001

120

22-bit

4,194,304

2.38 V

0.24

0.000024

132

24-bit

16,777,216

596 nV*

0.06

0.000006

144

*600nV is the Johnson Noise in a 10kHz BW of a 2.2k Resistor @ 25C

Remember: 10-bits and 10V FS yields an LSB of 10mV, 1000ppm, or 0.1%.
All other values may be calculated by powers of 2.

Practical Resolution Needs for Data Converters

Instrumentation

measurements

Sensor resolution/accuracy of 0.5% = 1/200

8 bits equivalent to 1/256 -- digitizing will lose information
10x sensor resolution = 1/2000 -- 12 bits is 1/4096
Allows discrimination of small changes
Can also be driven by display requirements

Dynamic

signal measurements

Audio systems need better than 0.1% distortion at 5% of full scale

Equivalent to 1/20,000 -- 16 bits is 1/65,536

Primary Errors in Data Converters

Instrumentation

and measurement

Described in LSBs(least-significant-bit), % of FS, ppm of FS

Offset error the input level needed to change the first code
Gain/full-scale error the input level need to change the last code
Nonlinearity deviation of codes from the line from zero to FS
Differential nonlinearity code-to-code deviation from 1 LSB
Transition noise ADC uncertainty in code center point

Transfer Functions for Non-Ideal 3-Bit DAC and ADC

DAC

ADC

FS
111
110

ANALOG
OUTPUT

DIGITAL
OUTPUT
NON-MONOTONIC

101
100

MISSING CODE

011
010
001
000

000

001

010

011

100

101

DIGITAL INPUT

110

111

ANALOG INPUT

FS

Combined Effects of Code Transition Noise and DNL

CODE TRANSITION NOISE

DNL

TRANSITION NOISE
AND DNL

ADC
OUTPUT
CODE

ADC INPUT

ADC INPUT

ADC INPUT

Primary Errors in Data Converters

Dynamic
SINAD

systems

(Signal-to-Noise-and-Distortion Ratio):

The ratio of the rms signal amplitude to the mean value of the root-sumsquares (RSS) of all other spectral components, including harmonics, but
excluding DC.
ENOB

(Effective Number of Bits):

ENOB =

SINAD 1.76dB
6.02dB

SNR

(Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without

Harmonics:
The ratio of the rms signal amplitude to the mean value of the root-sumsquares (RSS) of all other spectral components, excluding the first 5
harmonics and DC

SFDR

(Spurious-Free-Dynamic-Range) Signal dynamic range in

the bandwidth of interest containing no frequency noise spurs

Quantization & Quantization Noise

DIGITAL OUTPUT

111
110
101
100

011
010
001
1/8

2/8

3/8

4/8

5/8

6/8

7/8

FS

NORMALIZED ANALOG INPUT

Quantization Error
Function
quantization noise error: RMS value is LSB/3.464

Quantization Noise as a Function of Time

e(t)
+q
2

t
q
2

SLOPE = s

q
2s
ERROR = e(t) = st,

+q
2s
q
+q
<t<
2s
2s

MEAN-SQUARE ERROR =

e2(t)

ROOT-MEAN-SQUARE ERROR =

s
q

+q/2s

(st)
q/2s

e2(t) =

q
12

dt

q2
12

Ideal ADC Sampling

3 Different Frequencies, Sampled the Same

Ideal ADC Sampling

Once Sampled, Information is Lost

Nyquist's Criteria
A signal

with a maximum frequency fa must be sampled at a rate fs > 2fa

or information about the signal will be lost because of aliasing.

Aliasing

occurs whenever fs < 2fa

A signal

which has frequency components between fa and fb must be

sampled at a rate fs > 2 (fb fa) in order to prevent alias components
from overlapping the signal frequencies

The

concept of aliasing is widely used in communications applications

such as direct IF-to-digital conversion.

Aliasing occurs in Many Domains

Spatial, Temporal, etc.

Image Source : Wikipedia

Sampling & Aliasing in the Time Domain

ALIASED SIGNAL = fs fa

INPUT = fa

1
fs

NOTE: fa IS SLIGHTLY LESS THAN fs

Baseband Antialiasing Filter Requirements

fa

A
fa

fs - fa

Kfs - f a

Anti-Alias Filter Prevents Aliasing

Contributes to Dynamic Range

DR

Anti-Alias Filter Objectives

Brick Wall (Steep/Deep Rolloff)
Linear Passband
Linear Phase
fs
2

fs

STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to fs - fa

Kfs
2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to Kfs - fa

CORNER FREQUENCY: fa

CORNER FREQUENCY: fa

Kfs

Oversampling Relaxes Requirements

on Baseband Antialiasing Filter

fa

A
fs - fa

fa

Kfs - f
a

DR

fs
fs
2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to fs - fa

Kfs
2
STOPBAND ATTENUATION = DR
TRANSITION BAND: fa to Kfs - fa

CORNER FREQUENCY: fa

CORNER FREQUENCY: fa

Kfs

Sample-and-Hold Function
Required for Digitizing AC Signals
SAMPLING
CLOCK

TIMING

ANALOG
INPUT
SW
CONTROL

ADC
ENCODER
C
ENCODER CONVERTS
DURING HOLD TIME

HOLD
SW
CONTROL

SAMPLE

SAMPLE

Input Frequency Limitations of

Non-Sampling ADC (Encoder)

ANALOG INPUT
v(t) = q

2N
2

sin (2 f t )

2N
dv
q
2 f cos (2 f t )
dt =
2
dv
dt max

= q 2(N1) 2 f
dv
dt max

fmax =

2(N1) 2 q
dv
dt max

fmax =

q 2N

N-BIT
SAR ADC ENCODER
CONVERSION TIME = 8s

fs = 100 kSPS
EXAMPLE:
dv = 1 LSB = q
dt = 8s
N = 12, 2N = 4096
fmax = 9.7 Hz

Effective Aperture Delay Time

Measured with Respect to ADC Input

+FS
ZERO CROSSING

ANALOG INPUT
SINEWA VE

0V

-FS
t e '

+t e '
SAMPLING
CL OCK
t e'

Effects of Aperture Jitter

and Sampling Clock Jitter
dv
Dv =
dt

ANALOG
INPUT
dv
= SLOPE
dt

Dt

D v RMS = APERTURE JITTER ERROR

NOMINAL
HELD
OUTPUT

D t RMS = APERTURE JITTER

HOLD
TRACK

Theoretical SNR and ENOB Due to Jitter

vs. Fullscale Sinewave Analog Input Frequency
tj = 50fs

120

tj = 0.1ps
10 0

SNR = 20log 10

1
2 f t j

tj = 1ps

18
16
14

tj = 10ps

80

12
ENOB

SNR
(d B )

tj = 100ps

60

10
8

tj = 1ns

40

6
4

20
1

3
100
10
30
FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)

1-Bit DAC:
Changeover Switch (SPDT)

VREF
OUTPUT

Simplest Voltage Output Thermometer DAC:

The Kelvin Divider ( AKA - "String DAC")
VREF
R
R

3-TO-8
DECODER

TO
SWITCHES

R
R
R

3-BIT
DIGITAL
INPUT

ANALOG
OUTPUT

The Simplest Current Output

Thermometer (Fully-Decoded) DAC
VREF
R

3-TO-7
DECODER
7

3-BIT
DIGITAL
INPUT

TO
SWITCHES

CURRENT
OUTPUT INTO
VIRTUAL
GROUND
(USUALLY AN
OP-AMP I-V
CONVERTER)

Voltage-Mode Binary Weighted Resistor DAC

V
OUT

R/8

R/4

LSB
VREF

R/2

MSB

Current-Mode R-2R Ladder Network

Resistor-Based DAC
VREF

<< R

2R

2R
MSB

2R

2R

2R

LSB
CURRENT
OUTPUT
INTO
VIRTUAL
GROUND

* GAIN TRIM IF REQUIRED

Segmented Voltage Output DACs

(A)
VREF

KELVIN-VARLEY DIVIDER
("STRING DAC")
A

(B)
A

VREF

KELVIN DIVIDER AND

R-2R LADDER NETWORK
OUTPUT

B
A

OUTPUT
A

NOTE:
MSB OF R-2R LADDER
ON RIGHT

B
A

IF THE R-2R LADDER NETWORK

IS MONOTONIC, THE
WHOLE DAC IS
MONOTONIC

Circuits from the Lab

Multiplying DAC attenuates AC signal
+10V
VIN
10V
R1

RCOM

R1
+5V

REF
R2

ROFS
ROFS

RFB

C8
2.2pF

+12V
C4
0.1F

RFB

VDD
C2
0.1F

U1

IOUT

16/14-BIT

AD5546/AD5556

C5
1F
V+
U2

AD8610
GND

VOUT

16/14 DATA

C6
0.1F
WR LDAC RS MSB

WR
LDAC
RS
MSB

C7
1F

12V

08344-001

C1
1F

Digital Potentiometer Applications

Amplifier

and other component adjustment

Connect across offset-adjust pins

Gain adjustment or fine tuning
System

calibration

Digital pots inserted in strategic system locations

System tune-up automatically or manually
Non-volatile RAM setting returns on system power-up
RAM can be one-time program or re-programmable
Settings can be stored centrally and transmitted for system re-adjustment

Circuits from the Lab

Digital Potentiometer Gain Adjustment

1-Bit DAC:
Highly-sophisticated Digital-Audio DAC

VREF
OUTPUT

Sampled Data System: Sampling and Quantization

Sampled Data System: Sampling and Quantization

Basic ADC with External Reference

VDD

SAMPLING
CLOCK

VREF

ANALOG
INPUT

ADC

DIGITAL
OUTPUT

EOC, DATA READY, ETC.

VSS
GROUND
(MAY BE INTERNALLY
CONNECTED TO VSS)

The Comparator: A 1-Bit ADC

LATCH
ENABLE
+
DIFFERENTIAL
ANALOG INPUT

LOGIC
OUTPUT

COMPARATOR
OUTPUT
"1"

VHYSTERESIS
"0"
0
DIFFERENTIAL ANALOG INPUT

Basic Successive Approximation ADC

(Feedback Subtraction ADC)
CONVERT
START
TIMING
ANALOG
INPUT

COMPARATOR
SHA

DAC

CONTROL
LOGIC:
SUCCESSIVE
APPROXIMATION
REGISTER
(SAR)

OUTPUT

EOC,
DRDY,
OR BUSY

Successive Approximation ADC Algorithm

Analogy Using Binary Weights
ASSUME X = 45
TEST

TOTALS:

IS X 32 ?

YES RETAIN 32

IS X (32 +16) ?

NO REJECT 16

IS X (32 +8) ?

YES RETAIN 8

IS X (32 +8 + 4) ?

YES RETAIN 4

IS X (32 +8 + 4 + 2) ?

NO REJECT 2

IS X (32 +8 + 4 + 2 + 1) ?

YES RETAIN 1

X = 32 + 8 + 4 + 1 = 4510

1011012

3-bit All-Parallel (Flash) Converter

STROBE
+

ANALOG
INPUT
+VREF

1.5R

0.5R

PRIORITY
ENCODER
AND LATCH

DIGITAL
OUTPUT

Sigma-Delta ADC - First-Order Modulator

CLOCK
Kfs

INTEGRATOR

VIN

fs

A
+

DIGITAL
FILTER
AND
DECIMATOR

LATCHED
COMPARATOR
(1-BIT ADC)

+VREF

1-BIT
DAC

1-BIT DATA
STREAM
VREF

SIGMA-DELTA MODULATOR

1-BIT,
Kfs

N-BITS

fs

Thank You For Watching!

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