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EC-703

Pages - 4

(Following Paper ID and Roll No. to be filled in your Answer Book)

I

Roll No.

B.Tech.
SEVENTH

SEMESTER EXAMINATION,

2006-07

VLSI DESIGN
Total Marks : 100

Time : 3 Hours

Note:

1.

2.

(i)

Attempt

(ii)

All questions carry equal marks.

(iii)

In case of numerical problems assume data wherever

not provided.

(iv)

Be precise in your answer.

Attempt

ALL questions.

any two parts of the following:

(10x2=20)

(a)

Differentiate between a discrete component circuit

and an Integrated circuit. Classify the ICs on the
basis of scale of integration.

(b)

Write a comparison
technologies.

(c)

Explain the process of PHOTOLITHOGRAPHY

with the help of suitable diagram.

Attempt
(a)

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among

TTL, ECL and IlL

any two parts of the following:

(10x2=20)

Calculate the threshold voltage VIa at VSB =0 for

a polysilicon gate n-channel MOS transistor, with

[Turn Over

..

the following ftarameters;

substrate doping
density NA = 10 61cm3. Polysilicon gate doping
density No = 2 X 10181cm3 gate oxide thickness
tax = 5000A and oxide interface charge density
Nox=4Xl01O/cm2.

3.

(b)

Explain working principle of NMOS transistor

with the help of its cross sectional view and VI
characteristics.

(c)

Explain constant field scaling model of MOS and

illustrate
its effect
on the following
electrical parametery : Threshold voltage, power
dissipation, Drain current and delay.

Attempt allY two parts of the following:

(a)

(b)

Design a CMOS inverter under following heads:

(i)

circuit diagram

(ii)

stick diagram

(iii)

layout based an LAMBDA based design

ruler

Calculate channel resistance of the following

CMOS inverter and calculate overall delay of the
circuit when two inverters based on 5 fJ.m
technology are cascaded (shown in fig.) typical
sheet resistances
of MOS layers for 5 fJ.m
technology is shown in the following table.
Layer
Sheet resistance in n/o
for 5 fJ.m technology
n mas channel
104
p mas channel

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(lOx2=20)

2.5 x 104

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';'

Typical area capacitance value for MOS layers is

as follows for (5 fLm technology)

Layers

Area capacitance

Gate to channel

4 (1.0)

Metal 1 to substrate

0.3 (0.075)

Metal 2 to substrate

0.2 (0.05)

in

PF x 10-4/mm2

VDD

r/r-~

CMOS inverter
(c)

'-../

4.

Draw and explain equivalent

circuit of SPICE
model of level 2 of MOS transistor used for circuit
simulation.

Attempt
(a)

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any two parts of the following:

(10x2=20)

Design a 4 : 1 multiplexer

underfollowing

(i)

Block level design

verification.

and VHDL code for its

(ii)

Logic level design

verification

and VHDL code for its

heads:

[Turn Over

. (b)
(c)

5.

Draw and explain operation of S~AM cell and

EEROM cell.
Discuss about different VLSI design styles.

Attempt any two parts of the following:

(10x2=20)

(a)

What is VLSI testing? Explain different types of

fault models used in VLSI testing.

(b)

Explain programmable
VLSI design style.

(c)

Discuss about the use of CAD softwares used for

different steps of VLSI design.

-000-

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gate array design style of

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