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Data Sheet
28/40/44-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt XLP Technology
Preliminary
DS41364B
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS41364B-page ii
Preliminary
PIC16F193X/LF193X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
LCD Driver with nano Watt XLPTM Technology
Devices Included In This Data Sheet:
PIC16F193X Devices:
Standby Current:
- 60 nA @ 1.8V, typical
Operating Current:
- 7.0 A @ 32 kHz, 1.8V, typical
- 150 A @ 1 MHz, 1.8V, typical
Timer1 Oscillator Current:
- 600 nA @ 32 kHz, 1.8V, typical
Low-Power Watchdog Timer Current:
- 500 nA @ 1.8V, typical
PIC16F1933
PIC16F1934
PIC16F1936
PIC16F1937
PIC16F1938
PIC16F1939
PIC16LF193X Devices:
PIC16LF1933
PIC16LF1934
PIC16LF1936
PIC16LF1937
PIC16LF1938
PIC16LF1939
Peripheral Features:
Preliminary
DS41364B-page 1
PIC16F193X/LF193X
Peripheral Features (Continued):
Master Synchronous Serial Port (MSSP) with SPI
and I2 CTM with:
- 7-bit address masking
- SMBUS/PMBUSTM compatibility
- Auto-wake-up on start
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS 485 and LIN compatible
- Auto-Baud Detect
SR Latch (555 Timer):
- Multiple Set/Reset input options
2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
Device
Program Memory
Flash (words)
Data EEPROM
(bytes)
SRAM (bytes)
I/Os
10-bit A/D
(ch)
CapSense
(ch)
Comparators
Timers
8/16-bit
EUSART
I2C/SPI
ECCP
CCP
LCD
PIC16F1933
PIC16LF1933
4096
256
256
25
11
4/1
Yes
Yes
16(1)/4
PIC16F1934
PIC16LF1934
4096
256
256
36
14
16
4/1
Yes
Yes
24/4
PIC16F1936
PIC16LF1936
8192
256
512
25
11
4/1
Yes
Yes
16(1)/4
PIC16F1937
PIC16LF1937
8192
256
512
36
14
16
4/1
Yes
Yes
24/4
PIC16F1938
16384
PIC16LF1938
256
1024
25
11
4/1
Yes
Yes
16(1)/4
PIC16F1939
16384
PIC16LF1939
256
1024
36
14
16
4/1
Yes
Yes
24/4
Note 1:
COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore,
SEG15 is not available when using 1/4 multiplex displays.
DS41364B-page 2
Preliminary
PIC16F193X/LF193X
Pin Diagram 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
28-pin SPDIP, SOIC, SSOP
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCLK/SEG14
SEG7/C12IN1-/AN1/RA1
26
RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
25
SEG15/COM3/VREF+/C1IN+/AN3/RA3
24
RB4/AN11/CPS4/P1D/COM0
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
23
RB2/AN8/CPS2/P1B/VLCD2
SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5
VSS
7
8
9
22
21
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
20
VDD
19
VSS
18
RC7/RX/DT/P3B/SEG8
(1)
(1)
SEG2/CLKIN/OSC1/RA7
Note
PIC16LF1933/1936/1938
28
27
(1)
PIC16F1933/1936/1938
VPP/MCLR/RE3
(2)
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
P2B(1)/T1CKI/T1OSO/RC0
10
11
P2A(1)/CCP2(1)/T1OSI/RC1
12
17
RC6/TX/CK/CCP3(1)/P3A(1)/SEG9
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
13
16
RC5/SDO/SEG10
14
15
RC4/SDI/SDA/T1G(1)/SEG11
1:
2:
Preliminary
DS41364B-page 3
PIC16F193X/LF193X
28
27
26
25
24
23
22
RA1/AN1/C12IN1-/SEG7
RA0/AN0/C12IN0-/C2OUT(1)/SRNQ(1)/SS(1)/VCAP(2)/SEG12
28-pin QFN
RE3/MCLR/VPP
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1
RB4/AN11/CPS4/P1D/COM0
1
21
2
20
3 PIC16F1933/1936/1938 19
4 PIC16LF1933/1936/1938 18
5
17
6
16
7
15
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
RB2/AN8/CPS2/P1B/VLCD2
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
VDD
VSS
RC7/RX/DT/P3B/SEG8
DS41364B-page 4
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
SEG11/T1G(1)/SDA/SDI/RC4
SEG10/SDO/RC5
SEG9/P3A(1)/CCP3(1)/CK/TX/RC6
P2B(1)/T1CKI/T1OSO/RC0
Note
(1)P2A/(1)CCP2/T1OSI/RC1
8
9
10
11
12
13
14
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
SEG15/COM3/VREF+/C1IN+/AN3/RA3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5(1)/VCAP(2)/SS(1)/SRNQ/CPS7/C2OUT(1)/AN4/RA5
VSS
SEG2/CLKIN/OSC1/RA7
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
1:
2:
Preliminary
PIC16F193X/LF193X
SRNQ(1)
AN1
C12IN1-
AN2/
VREF-
C2IN+/
DACOUT
AN3/
VREF+
C1IN+
Basic
C12IN0-/
C2OUT(1)
Pull-up
Interrupt
AN0
LCD
MSSP
RA3
EUSART
CCP
28
Timers
RA2
SR Latch
RA1
Comparator
27
Cap Sense
A/D
28-Pin QFN
RA0
ANSEL
28-Pin SIP
I/O
TABLE 1:
SS(1)
SEG12
VCAP(2)
SEG7
COM2
SEG15/
COM3
RA4
CPS6
C1OUT
SRQ
T0CKI
CCP5
SEG4
RA5
AN4
CPS7
C2OUT(1)
SRNQ(1)
SS(1)
SEG5
VCAP(2)
RA6
10
SEG1
OSC2/
CLKOUT
VCAP(2)
RA7
SEG2
OSC1/
CLKIN
RB0
21 18
AN12
CPS0
SRI
CCP4
SEG0
INT/
IOC
RB1
22 19
AN10
CPS1
C12IN3-
P1C
VLCD1
IOC
RB2
23 20
AN8
CPS2
P1B
VLCD2
IOC
RB3
24 21
AN9
CPS3
C12IN2-
CCP2(1)/
P2A(1)
VLCD3
IOC
RB4
25 22
AN11
CPS4
P1D
COM0
IOC
RB5
26 23
AN13
CPS5
T1G(1)
P2B(1)
CCP3(1)/
P3A(1)
COM1
IOC
RB6
27 24
SEG14
IOC
ICSPCLK/
ICDCLK
RB7
28 25
SEG13
IOC
ICSPDAT/
ICDDAT
RC0
11
T1OSO/
T1CKI
P2B(1)
RC1
12
T1OSI
CCP2(1)/
P2A(1)
RC2
13 10
CCP1/
P1A
SEG3
RC3
14 11
SCK/SCL
SEG6
RC4
15 12
T1G(1)
SDI/SDA
SEG11
RC5
16 13
SDO
SEG10
RC6
17 14
CCP3(1)
P3A(1)
TX/CK
SEG9
RC7
18 15
P3B
RX/DT
SEG8
RE3
MCLR/VPP
VDD
20 17
VDD
Vss
8, 5,
19 16
VSS
Note
1:
2:
26
Preliminary
DS41364B-page 5
PIC16F193X/LF193X
Pin Diagram 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
40-Pin PDIP
VPP/MCLR/RE3
40
RB7/ICSPDAT/ICDDAT/SEG13
SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0
39
RB6/ICSPCLK/ICDCLK/SEG14
SEG7/C12IN1-/AN1/RA1
38
RB5/AN13/CPS5/CCP3(1)/P3A(1)/T1G(1)/COM1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
37
RB4/AN11/CPS4/COM0
SEG15/VREF+/C1IN+/AN3/RA3
36
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
35
RB2/AN8/CPS2/VLCD2
34
RB1/AN10/C12IN3-/CPS1/VLCD1
SEG21/CCP3(1)/P3A(1)/AN5/RE0
33
RB0/AN12/CPS0/SRI/INT/SEG0
SEG22/P3B/AN6/RE1
32
VDD
31
VSS
30
RD7/CPS15/P1D/SEG20
29
RD6/CPS14/P1C/SEG19
28
RD5/CPS13/P1B/SEG18
SEG23/CCP5/AN7/RE2
10
VDD
11
VSS
12
SEG2/CLKIN/OSC1/RA7
13
CAP(2)/CLKOUT/OSC2/RA6
14
27
RD4/CPS12/P2D/SEG17
(1)/T1CKI/T1OSO/RC0
15
26
RC7/RX/DT/SEG8
P2A(1)/CCP2(1)/T1OSI/RC1
16
25
RC6/TX/CK/SEG9
SEG3/P1A/CCP1/RC2
17
24
RC5/SDO/SEG10
SEG6/SCK/SCL/RC3
18
23
RC4/SDI/SDA/T1G(1)/SEG11
COM3/CPS8/RD0
19
22
RD3/CPS11/P2C/SEG16
20
21
RD2/CPS10/P2B(1)
SEG1/V
P2B
CCP4/CPS9/RD1
Note
DS41364B-page 6
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5
1:
2:
Preliminary
PIC16F193X/LF193X
Pin Diagram 44-Pin QFN (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
12
13
14
15
16
17
18
19
20
21
22
1
33
2
32
3
31
4
30
5 PIC16F1934/1937/1939 29
6 PIC16LF1934/1937/1939 28
7
27
8
26
9
25
10
24
11
23
RA6/OSC2/CLKOUT/VCAP(2)/SEG1
RA7/OSC1/CLKIN/SEG2
VSS
VSS
NC
VDD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
RE0/AN5/CCP3(1)/P3A(1)/SEG21
RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3
NC
COM0/CPS4/AN11/RB4
COM1/T1G(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5
SEG14/ICDCLK/ICSPCLK/RB6
SEG13/ICDDAT/ICSPDAT/RB7
VPP/MCLR/RE3
(1)
(1)
(2)
SEG12/VCAP /SS /SRNQ /C2OUT(1)/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
SEG15VREF+/C1IN+/AN3/RA3
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
VSS
VDD
VDD
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
VLCD2/CPS2/AN8/RB2
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK/SEG9
RC5/SDO/SEG10
RC4/SDI/SDA/T1G(1)/SEG11
RD3/CPS11/P2C/SEG16
RD2/CPS10/P2B(1)
RD1/CPS9/CCP4
RD0/CPS8/COM3
RC3/SCL/SCK/SEG6
RC2/CCP1/P1A/SEG3
RC1/T1OSI/CCP2(1)/P2A(1)
RC0/T1OSO/T1CKI/P2B(1)
44-pin QFN
Note
1:
2:
Preliminary
DS41364B-page 7
PIC16F193X/LF193X
Pin Diagram 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5 PIC16F1934/1937/1939
6 PIC16LF1934/1937/1939
7
8
9
10
11
NC
RC0/T1OSO/T1CKI/P2B(1)
RA6/OSC2/CLKOUT/VCAP(2)/SEG1
RA7/OSC1/CLKIN/SEG2
VSS
VDD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
RE0/AN5/CCP3(1)/P3A(1)/SEG21
RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
NC
NC
COM0/CPS4/AN11/RB4
(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5
COM1/T1G
SEG14/ICDCLK/ICSPCLK/RB6
SEG13/ICDDAT/ICSPDAT/RB7
VPP/MCLR/RE3
SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
COM2/DACOUT/VREF-/C2IN+/AN2/RA2
SEG15/VREF+/C1IN+/AN3/RA3
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
VSS
VDD
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
VLCD2/CPS2/AN8/RB2
VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK/SEG9
RC5/SDO/SEG10
RC4/SDI/SDA/T1G(1)/SEG11
RD3/CPS11/P2C/SEG16
RD2/CPS10/P2B(1)
RD1/CPS9/CCP4
RD0/CPS8/COM3
RC3/SCL/SCK/SEG6
RC2/CCP1/P1A/SEG3
RC1/T1OSI/CCP2(1)/P2A(1)
NC
44-pin TQFP
Note
1:
2:
DS41364B-page 8
Preliminary
PIC16F193X/LF193X
22
SRNQ(1)
AN1
C12IN1-
AN2/
VREF-
C2IN+/
DACOUT
AN3/
VREF+
C1IN+
Basic
22
C12IN0-/
C2OUT(1)
Pull-up
Interrupt
RA3
AN0
LCD
21
MSSP
20
21
EUSART
20
CCP
RA2
Timers
RA1
SR Latch
19
Comparator
19
Cap Sense
44-Pin QFN
A/D
44-Pin TQFP
RA0
ANSEL
40-Pin PDIP
I/O
TABLE 2:
SS(1)
SEG12
VCAP
SEG7
COM2
SEG15
RA4
23
23
CPS6
C1OUT
SRQ
T0CKI
SEG4
RA5
24
24
AN4
CPS7
C2OUT(1)
SRNQ(1)
SS(1)
SEG5
VCAP
RA6
14
31
33
SEG1
OSC2/
CLKOUT
VCAP
RA7
13
30
32
SEG2
OSC1/
CLKIN
RB0
33
AN12
CPS0
SRI
SEG0
INT/
IOC
RB1
34
10
AN10
CPS1
C12IN3-
VLCD1
IOC
RB2
35
10
11
AN8
CPS2
VLCD2
IOC
RB3
36
11
12
AN9
CPS3
C12IN2-
CCP2(1)/
P2A(1)
VLCD3
IOC
RB4
37
14
14
AN11
CPS4
COM0
IOC
RB5
38
15
15
AN13
CPS5
T1G(1)
CCP3(1)/
P3A(1)
COM1
IOC
RB6
39
16
16
SEG14
IOC
ICSPCLK/
ICDCLK
RB7
40
17
17
SEG13
IOC
ICSPDAT/
ICDDAT
RC0
15
32
34
T1OSO/
T1CKI
P2B(1)
RC1
16
35
35
T1OSI
CCP2(1)/
P2A(1)
RC2
17
36
36
CCP1/
P1A
SEG3
RC3
18
37
37
SCK/SCL
SEG6
RC4
23
42
42
T1G(1)
SDI/SDA
SEG11
RC5
24
43
43
SDO
SEG10
RC6
25
44
44
TX/CK
SEG9
RC7
26
RX/DT
SEG8
RD0
19
38
38
CPS8
COM3
RD1
20
39
39
CPS9
CCP4
RD2
21
40
40
CPS10
P2B(1)
RD3
22
41
41
CPS11
P2C
SEG16
RD4
27
CPS12
P2D
SEG17
RD5
28
CPS13
P1B
SEG18
RD6
29
CPS14
P1C
SEG19
RD7
30
CPS15
P1D
SEG20
RE0
25
25
AN5
CCP3(1)
P3A(1)
SEG21
RE1
26
26
AN6
P3B
SEG22
RE2
10
27
27
AN7
CCP5
SEG23
RE3
18
18
MCLR/VPP
VDD
11,
32
7,
28
7,8,
28
VDD
Vss
12, 6, 6,30,
31 29
31
VSS
Note 1:
Preliminary
DS41364B-page 9
PIC16F193X/LF193X
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Memory Organization ................................................................................................................................................................. 19
10.0 Device Configuration ................................................................................................................................................................ 123
8.0 Oscillator Module (With Fail-Safe Clock Monitor)..................................................................................................................... 105
3.0 Resets ........................................................................................................................................................................................ 55
4.0 Interrupts .................................................................................................................................................................................... 67
24.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 333
23.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 321
6.0 I/O Ports ..................................................................................................................................................................................... 81
7.0 Interrupt-on-Change ................................................................................................................................................................. 101
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 153
11.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129
13.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149
12.0 Comparator Module.................................................................................................................................................................. 141
9.0 SR Latch................................................................................................................................................................................... 119
15.0 Timer0 Module ......................................................................................................................................................................... 155
16.0 Timer1 Module ......................................................................................................................................................................... 159
17.0 Timer2/4/6 Modules.................................................................................................................................................................. 171
19.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4, CCP5) Modules .......................................................................... 181
22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 273
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 211
18.0 Capacitive Sensing Module ...................................................................................................................................................... 175
21.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 239
25.0 In-Circuit Serial Programming (ICSP) ................................................................................................................................ 335
5.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79
26.0 Instruction Set Summary .......................................................................................................................................................... 337
28.0 Electrical Specifications............................................................................................................................................................ 355
29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 389
27.0 Development Support............................................................................................................................................................... 351
30.0 Packaging Information.............................................................................................................................................................. 391
Appendix A: Revision History............................................................................................................................................................. 403
Appendix B: Device Differences......................................................................................................................................................... 403
Index .................................................................................................................................................................................................. 405
The Microchip Web Site ..................................................................................................................................................................... 413
Customer Change Notification Service .............................................................................................................................................. 413
Customer Support .............................................................................................................................................................................. 413
Reader Response .............................................................................................................................................................................. 414
Product Identification System............................................................................................................................................................. 415
DS41364B-page 10
Preliminary
PIC16F193X/LF193X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Preliminary
DS41364B-page 11
PIC16F193X/LF193X
NOTES:
DS41364B-page 12
Preliminary
PIC16F193X/LF193X
1.0
DEVICE OVERVIEW
FIGURE 1-1:
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Direct Addr
PORTA
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RAM
Program Memory
Read (PMR)
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM Addr
PORTB
Addr MUX
12
15
Indirect
Addr
FSR0reg
Reg
FSR
FSR1reg
Reg
FSR
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
Instruction
Decodeand
&
Decode
Control
Oscillator
Start-up Timer
OSC2/CLKOUT
Timing
Generation
PORTD
Watchdog
Timer
Brown-out
Reset
RD0
RC1
RD1
RD2
RD3
RD4
RD5
RD6
RD7
W Reg
reg
W
PORTE
VDD
Comparators
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
MUX
Internal
Oscillator
Block
Timer0
PORTC
ALU
Power-on
Reset
OSC1/CLKIN
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Timer1
CCP4/5
RE0
RE1
RE2
RE3/MCLR
VSS
Timer2/4/6
ECCP1/2/3
MSSP
Timer1
Addressable
EUSART
Preliminary
Data EEPROM
256 bytes
SR Latch
LCD
DS41364B-page 13
PIC16F193X/LF193X
1.1
1.1.1
1.1.2
1.1.3
INSTRUCTION SET
DS41364B-page 14
Preliminary
PIC16F193X/LF193X
TABLE 1-1:
Name
RA0/AN0/C12IN0-/C2OUT(1)/
SRNQ(1)/SS(1)/VCAP(2)/SEG12
RA1/AN1/C12IN1-/SEG7
RA2/AN2/C2IN+/VREF-/CVREF/
COM2
RA3/AN3/C1IN+/VREF+/
COM3(3)/SEG15
RA4/C1OUT/CPS6/T0CKI/SRQ/
CCP5/SEG4
RA5/AN4/C2OUT(1)/CPS7/
SRNQ(1)/SS(1)/VCAP(2)/SEG5
Function
Input
Type
Output
Type
RA0
TTL
AN0
AN
C12IN0-
AN
C2OUT
SRNQ
SS
ST
Description
VCAP
Power
Power
SEG12
AN
RA1
TTL
AN1
AN
C12IN1SEG7
RA2
TTL
AN2
AN
AN
AN
C2IN+
AN
VREF-
AN
CVREF
AN
COM2
AN
RA3
TTL
AN3
AN
C1IN+
AN
VREF+
AN
COM3(3)
AN
SEG15
AN
RA4
TTL
C1OUT
CPS6
AN
T0CKI
ST
SRQ
CCP5
ST
CMOS Capture/Compare/PWM5.
SEG4
RA5
TTL
AN4
AN
AN
C2OUT
CPS7
AN
SRNQ
SS
ST
VCAP
Power
Power
SEG5
AN
Preliminary
DS41364B-page 15
PIC16F193X/LF193X
TABLE 1-1:
Name
RA6/OSC2/CLKOUT/VCAP(2)/
SEG1
RA7/OSC1/CLKIN/SEG2
RB0/AN12/CPS0/CCP4/SRI/INT/
SEG0
RB1/AN10/C12IN3-/CPS1/P1C/
VLCD1
RB2/AN8/CPS2/P1B/VLCD2
RB3/AN9/C12IN2-/CPS3/
CCP2(1)/P2A(1)/VLCD3
Function
Input
Type
RA6
TTL
Output
Type
Description
OSC2
CLKOUT
XTAL
VCAP
Power
Power
SEG1
AN
RA7
TTL
OSC1
XTAL
CLKIN
CMOS
SEG2
AN
RB0
TTL
AN12
AN
CPS0
AN
CCP4
ST
CMOS Capture/Compare/PWM4.
SRI
ST
SR Latch input.
INT
ST
External interrupt.
AN
SEG0
RB1
TTL
AN10
AN
C12IN3-
AN
CPS1
AN
P1C
VLCD1
AN
RB2
TTL
AN8
AN
CPS2
AN
P1B
VLCD2
AN
RB3
TTL
AN9
AN
C12IN2-
AN
CPS3
AN
CCP2
ST
CMOS Capture/Compare/PWM2.
P2A
VLCD3
AN
DS41364B-page 16
Preliminary
PIC16F193X/LF193X
TABLE 1-1:
Name
RB4/AN11/CPS4/P1D/COM0
RB5/AN13/CPS5/P2B/CCP3(1)/
P3A(1)/T1G(1)/COM1
RB6/ICSPCLK/ICDCLK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13
RC0/T1OSO/T1CKI/P2B
RC1/T1OSI/CCP2
(1)
(1)
(1)
/P2A
RC2/CCP1/P1A/SEG3
RC3/SCK/SCL/SEG6
Function
Input
Type
RB4
TTL
Output
Type
Description
AN11
AN
CPS4
AN
P1D
COM0
RB5
TTL
AN13
AN
CPS5
AN
P2B
CCP3
ST
CMOS Capture/Compare/PWM3.
P3A
T1G
ST
COM1
AN
RB6
TTL
ICSPCLK
ST
ICDCLK
SEG14
RB7
TTL
ST
AN
ICSPDAT
ST
ICDDAT
ST
SEG13
AN
RC0
ST
T1OSO
XTAL
T1CKI
ST
P2B
RC1
ST
T1OSI
XTAL
CCP2
ST
CMOS Capture/Compare/PWM2.
P2A
XTAL
RC2
ST
CCP1
ST
CMOS Capture/Compare/PWM1.
CMOS PWM output.
P1A
SEG3
AN
RC3
ST
SCK
ST
SCL
I2C
OD
I2C clock.
SEG6
AN
Preliminary
DS41364B-page 17
PIC16F193X/LF193X
TABLE 1-1:
Name
RC4/SDI/SDA/T1G(1)/SEG11
RC5/SDO/SEG10
RC6/TX/CK/CCP3/P3A/SEG9
RC7/RX/DT/P3B/SEG8
RD0(4)/CPS8/COM3
RD1(4)/CPS9/CCP4
RD2(4)/CPS10/P2B
RD3(4)/CPS11/P2C/SEG16
RD4(4)/CPS12/P2D/SEG17
RD5(4)/CPS13/P1B/SEG18
Function
Input
Type
RC4
ST
Output
Type
Description
SDI
ST
SDA
I2C
OD
T1G
ST
SEG11
AN
RC5
ST
SDO
SEG10
RC6
ST
AN
TX
CK
ST
CCP3
ST
CMOS Capture/Compare/PWM3.
P3A
SEG9
RC7
ST
AN
RX
ST
DT
ST
P3B
SEG8
RD0
ST
CPS8
AN
AN
AN
COM3
RD1
ST
CPS9
AN
CCP4
ST
CMOS Capture/Compare/PWM4.
CMOS General purpose I/O.
RD2
ST
CPS10
AN
P2B
RD3
ST
CPS11
AN
P2C
SEG16
RD4
ST
CPS12
AN
P2D
SEG17
RD5
ST
CPS13
AN
P1D
SEG18
DS41364B-page 18
Preliminary
PIC16F193X/LF193X
TABLE 1-1:
Name
RD6(4)/CPS14/P1C/SEG19
RD7(4)/CPS15/P1D/SEG20
RE0(5)/AN5/P3A(1)/CCP3(1)/
SEG21
RE1
RE2
(5)
/AN6/P3B/SEG22
(5)
/AN7/CCP5/SEG23
Function
Input
Type
RD6
ST
CPS14
AN
P1C
SEG19
RD7
ST
CPS15
AN
P1D
Output
Type
Description
SEG20
RE0
ST
AN5
AN
P3A
CCP3
ST
CMOS Capture/Compare/PWM3.
SEG21
RE1
ST
AN6
AN
P3B
SEG22
AN
AN
RE2
ST
AN7
AN
CCP5
ST
SEG23
AN
CMOS Capture/Compare/PWM5.
RE3
TTL
MCLR
ST
VPP
HV
Programming voltage.
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
RE3/MCLR/VPP
Preliminary
DS41364B-page 19
PIC16F193X/LF193X
NOTES:
DS41364B-page 20
Preliminary
PIC16F193X/LF193X
2.0
MEMORY ORGANIZATION
2.1
TABLE 2-1:
PIC16F1933/PIC16LF1933
4,096
0FFFh
PIC16F1934/PIC16LF1934
4,096
0FFFh
PIC16F1936/PIC16LF1936
8,192
1FFFh
PIC16F1937/PIC16LF1937
8,192
1FFFh
PIC16F1938/PIC16LF1938
16,384
3FFFh
PIC16F1939/PIC16LF1939
16,384
3FFFh
Preliminary
DS41364B-page 21
PIC16F193X/LF193X
FIGURE 2-1:
FIGURE 2-2:
PC<14:0>
CALL, CALLW
RETURN, RETLW
INTERRUPT, RETFIE
On-chip
Program
Memory
15
CALL, CALLW
RETURN, RETLW
INTERRUPT, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 15
Stack Level 15
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
Page 0
Page 0
07FFh
0800h
07FFh
0800h
Page 1
Rollover to Page 0
0FFFh
1000h
On-chip
Program
Memory
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
Rollover to Page 0
Rollover to Page 1
DS41364B-page 22
Rollover to Page 3
7FFFh
Preliminary
1FFFh
2000h
7FFFh
PIC16F193X/LF193X
FIGURE 2-3:
2.1.1
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
2.1.1.1
CALL, CALLW
15
RETURN, RETLW
INTERRUPT, RETFIE
Stack Level 0
Stack Level 1
RETLW Instruction
EXAMPLE 2-1:
constants
brw
retlw
retlw
retlw
retlw
Stack Level 15
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
Page 4
Page 7
Rollover to Page 0
Rollover to Page 7
1FFFh
2000h
3FFFh
4000h
RETLW INSTRUCTION
DATA1
DATA2
DATA3
DATA4
my_function
; LOTS OF CODE
movlw
DATA_INDEX
call constants
; THE CONSTANT IS IN W
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
2.1.1.2
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 2-2 demonstrates accessing the program memory via an FSR.
7FFFh
EXAMPLE 2-2:
ACCESSING PROGRAM
MEMORY VIA FSR
bsf FSR1H,7
moviw 0[INDF1]
;THE PROGRAM MEMORY IS IN W
Preliminary
DS41364B-page 23
PIC16F193X/LF193X
2.2
2.2.1
2.2.2
DS41364B-page 24
Preliminary
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
(1)
BANK 5
BANK 6
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUB
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Preliminary
2009 Microchip Technology Inc.
20Fh
28Fh
30Fh
38Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
PIR2
PIR3
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
CPSCON0
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
PIE2
PIE3
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
APFCON
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
CCPR4L
CCPR4H
CCP4CON
CCPR5L
CCPR5H
CCP5CON
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCBP
IOCBN
IOCBF
01Fh
020h
CPSCON1
09Fh
0A0h
11Fh
120h
19Fh
1A0h
BAUDCTR
21Fh
220h
29Fh
2A0h
CCPTMRS1
31Fh
320h
39Fh
3A0h
06Fh
070h
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
0EFh
0F0h
16Fh
170h
Accesses
70h 7Fh
07Fh
Legend:
Note 1:
General
Purpose
Register
80 Bytes
Unimplemented
Read as 0
1EFh
1F0h
Accesses
70h 7Fh
0FFh
17Fh
= Unimplemented data memory locations, read as 0.
Unimplemented
Read as 0
26Fh
270h
Accesses
70h 7Fh
1FFh
Unimplemented
Read as 0
27Fh
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
Unimplemented
Read as 0
Accesses
70h 7Fh
2FFh
Unimplemented
Read as 0
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16F193X/LF193X
DS41364B-page 25
TABLE 2-2:
BANK 8
Preliminary
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TMR4
PR4
T4CON
TMR6
PR6
T6CON
BANK 9
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as 0
46Fh
470h
Legend:
BANK 10
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
Unimplemented
Read as 0
4EFh
4F0h
Accesses
70h 7Fh
47Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 11
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
Unimplemented
Read as 0
56Fh
570h
Accesses
70h 7Fh
4FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
5EFh
5F0h
Accesses
70h 7Fh
57Fh
BANK 12
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
BANK 13
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
Unimplemented
Read as 0
66Fh
670h
Accesses
70h 7Fh
5FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 14
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Unimplemented
Read as 0
6EFh
6F0h
Accesses
70h 7Fh
67Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 15
INDF0
780h
INDF1
781h
PCL
782h
STATUS
783h
FSR0L
784h
FSR0H
785h
FSR1L
786h
FSR1H
787h
BSR
788h
WREG
789h
PCLATH
78Ah
INTCON
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
See Table 2-10 or
79Bh
Table 2-11
79Ch
79Dh
79Eh
79Fh
7A0h
Unimplemented
Read as 0
76Fh
770h
Accesses
70h 7Fh
6FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
7EFh
7F0h
Accesses
70h 7Fh
77Fh
Accesses
70h 7Fh
7FFh
PIC16F193X/LF193X
DS41364B-page 26
TABLE 2-3:
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
(1)
BANK 5
BANK 6
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUB
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Preliminary
2009 Microchip Technology Inc.
20Fh
28Fh
30Fh
38Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
PIR2
PIR3
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
TxCON
CPSCON0
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
PIE2
PIE3
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
APFCON
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
CCPR4L
CCPR4H
CCP4CON
CCPR5L
CCPR5H
CCP5CON
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCBP
IOCBN
IOCBF
01Fh
020h
CPSCON1
09Fh
0A0h
11Fh
120h
19Fh
1A0h
BAUDCON
21Fh
220h
29Fh
2A0h
CCPTMRS1
31Fh
39Fh
320h General Purpose 3A0h
Register
16 Bytes
32Fh
06Fh
070h
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
0EFh
0F0h
16Fh
170h
Accesses
70h 7Fh
07Fh
Legend:
Note 1:
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
1EFh
1F0h
Accesses
70h 7Fh
0FFh
17Fh
= Unimplemented data memory locations, read as 0.
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
Accesses
70h 7Fh
2FFh
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Unimplemented
Read as 0
Unimplemented
Read as 0
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
330h
Accesses
70h 7Fh
3FFh
PIC16F193X/LF193X
DS41364B-page 27
TABLE 2-4:
BANK 8
Preliminary
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TMR4
PR4
T4CON
TMR6
PR6
T6CON
BANK 9
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as 0
46Fh
470h
Legend:
BANK 10
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
Unimplemented
Read as 0
4EFh
4F0h
Accesses
70h 7Fh
47Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 11
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
Unimplemented
Read as 0
56Fh
570h
Accesses
70h 7Fh
4FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
5EFh
5F0h
Accesses
70h 7Fh
57Fh
BANK 12
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
BANK 13
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
Unimplemented
Read as 0
66Fh
670h
Accesses
70h 7Fh
5FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 14
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Unimplemented
Read as 0
6EFh
6F0h
Accesses
70h 7Fh
67Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 15
INDF0
780h
INDF1
781h
PCL
782h
STATUS
783h
FSR0L
784h
FSR0H
785h
FSR1L
786h
FSR1H
787h
BSR
788h
WREG
789h
PCLATH
78Ah
INTCON
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
See Table 2-10 or
79Bh
Table 2-11
79Ch
79Dh
79Eh
79Fh
7A0h
Unimplemented
Read as 0
76Fh
770h
Accesses
70h 7Fh
6FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
7EFh
7F0h
Accesses
70h 7Fh
77Fh
Accesses
70h 7Fh
7FFh
PIC16F193X/LF193X
DS41364B-page 28
TABLE 2-5:
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
(1)
BANK 5
BANK 6
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUB
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Preliminary
2009 Microchip Technology Inc.
20Fh
28Fh
30Fh
38Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
PIR2
PIR3
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
CPSCON0
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
PIE2
PIE3
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
APFCON
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
RC1REG
TX1REG
SPBRGL1
SPBRGH1
RCSTA1
TXSTA1
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
CCPR4L
CCPR4H
CCP4CON
CCPR5L
CCPR5H
CCP5CON
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
IOCBP
IOCBN
IOCBF
01Fh
020h
CPSCON1
09Fh
0A0h
11Fh
120h
19Fh
1A0h
BAUDCTL1
21Fh
220h
29Fh
2A0h
CCPTMRS1
31Fh
320h
39Fh
3A0h
06Fh
070h
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
0EFh
0F0h
16Fh
170h
Accesses
70h 7Fh
07Fh
Legend:
Note 1:
0FFh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
1EFh
1F0h
Accesses
70h 7Fh
17Fh
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h 7Fh
1FFh
General
Purpose
Register
80 Bytes
27Fh
Accesses
70h 7Fh
2FFh
General
Purpose
Register
80 Bytes
36Fh
370h
2EFh
2F0h
Accesses
70h 7Fh
32Fh
330h
General
Purpose
Register
80 Bytes
3EFh
3F0h
Accesses
70h 7Fh
37Fh
Accesses
70h 7Fh
3FFh
PIC16F193X/LF193X
DS41364B-page 29
TABLE 2-6:
BANK 8
Preliminary
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TMR4
PR4
T4CON
TMR6
PR6
T6CON
BANK 9
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
General
Purpose
Register
80 Bytes
46Fh
470h
Legend:
BANK 10
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
General
Purpose
Register
80 Bytes
4EFh
4F0h
Accesses
70h 7Fh
47Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 11
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
General
Purpose
Register
80 Bytes
56Fh
570h
Accesses
70h 7Fh
4FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
General
Purpose
Register
80 Bytes
5EFh
5F0h
Accesses
70h 7Fh
57Fh
BANK 12
INDF0
600h
INDF1
601h
PCL
602h
STATUS
603h
FSR0L
604h
FSR0H
605h
FSR1L
606h
FSR1H
607h
BSR
608h
WREG
609h
PCLATH
60Ah
INTCON
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h General Purpose
Register
48 Bytes
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 14
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Unimplemented
Read as 0
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 15
INDF0
780h
INDF1
781h
PCL
782h
STATUS
783h
FSR0L
784h
FSR0H
785h
FSR1L
786h
FSR1H
787h
BSR
788h
WREG
789h
PCLATH
78Ah
INTCON
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
See Table 2-10 or
79Bh
Table 2-11
79Ch
79Dh
79Eh
79Fh
7A0h
Unimplemented
Read as 0
Unimplemented
Read as 0
66Fh
670h
Accesses
70h 7Fh
5FFh
BANK 13
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
Accesses
70h 7Fh
67Fh
76Fh
770h
Accesses
70h 7Fh
6FFh
7EFh
7F0h
Accesses
70h 7Fh
77Fh
Accesses
70h 7Fh
7FFh
PIC16F193X/LF193X
DS41364B-page 30
TABLE 2-7:
TABLE 2-8:
BANK 16
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 17
880h
881h
882h
883h
884h
885h
886h
887h
888h
889h
88Ah
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
89Fh
8A0h
Unimplemented
Read as 0
DS41364B-page 31
86Fh
870h
Legend:
BANK 18
900h
901h
902h
903h
904h
905h
906h
907h
908h
909h
90Ah
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
91Fh
920h
Unimplemented
Read as 0
8EFh
8F0h
8FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 19
980h
981h
982h
983h
984h
985h
986h
987h
988h
989h
98Ah
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
99Fh
9A0h
Unimplemented
Read as 0
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
97Fh
BANK 20
A00h
A01h
A02h
A03h
A04h
A05h
A06h
A07h
A08h
A09h
A0Ah
A0Bh
A0Ch
A0Dh
A0Eh
A0Fh
A10h
A11h
A12h
A13h
A14h
A15h
A16h
A17h
A18h
A19h
A1Ah
A1Bh
A1Ch
A1Dh
A1Eh
A1Fh
A20h
Unimplemented
Read as 0
9EFh
9F0h
96Fh
970h
Accesses
70h 7Fh
Accesses
70h 7Fh
87Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 21
A80h
A81h
A82h
A83h
A84h
A85h
A86h
A87h
A88h
A89h
A8Ah
A8Bh
A8Ch
A8Dh
A8Eh
A8Fh
A90h
A91h
A92h
A93h
A94h
A95h
A96h
A97h
A98h
A99h
A9Ah
A9Bh
A9Ch
A9Dh
A9Eh
A9Fh
AA0h
Unimplemented
Read as 0
BANK 22
B00h
B01h
B02h
B03h
B04h
B05h
B06h
B07h
B08h
B09h
B0Ah
B0Bh
B0Ch
B0Dh
B0Eh
B0Fh
B10h
B11h
B12h
B13h
B14h
B15h
B16h
B17h
B18h
B19h
B1Ah
B1Bh
B1Ch
B1Dh
B1Eh
B1Fh
B20h
Unimplemented
Read as 0
Accesses
70h 7Fh
A7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
AEFh
AF0h
A6Fh
A70h
Accesses
70h 7Fh
9FFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 23
B80h
B81h
B82h
B83h
B84h
B85h
B86h
B87h
B88h
B89h
B8Ah
B8Bh
B8Ch
B8Dh
B8Eh
B8Fh
B90h
B91h
B92h
B93h
B94h
B95h
B96h
B97h
B98h
B99h
B9Ah
B9Bh
B9Ch
B9Dh
B9Eh
B9Fh
BA0h
Unimplemented
Read as 0
Unimplemented
Read as 0
Accesses
70h 7Fh
B7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BEFh
BF0h
B6Fh
B70h
Accesses
70h 7Fh
AFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Accesses
70h 7Fh
BFFh
PIC16F193X/LF193X
Preliminary
800h
801h
802h
803h
804h
805h
806h
807h
808h
809h
80Ah
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
81Fh
820h
BANK 24
Preliminary
C00h
C01h
C02h
C03h
C04h
C05h
C06h
C07h
C08h
C09h
C0Ah
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 25
C80h
C81h
C82h
C83h
C84h
C85h
C86h
C87h
C88h
C89h
C8Ah
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
C6Fh
C70h
Legend:
BANK 26
D00h
D01h
D02h
D03h
D04h
D05h
D06h
D07h
D08h
D09h
D0Ah
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as 0
CEFh
CF0h
Accesses
70h 7Fh
CFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 27
D80h
D81h
D82h
D83h
D84h
D85h
D86h
D87h
D88h
D89h
D8Ah
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Unimplemented
Read as 0
D6Fh
D70h
Accesses
70h 7Fh
CFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
DEFh
DF0h
Accesses
70h 7Fh
D7Fh
BANK 28
E00h
E01h
E02h
E03h
E04h
E05h
E06h
E07h
E08h
E09h
E0Ah
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
BANK 29
E80h
E81h
E82h
E83h
E84h
E85h
E86h
E87h
E88h
E89h
E8Ah
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
Unimplemented
Read as 0
E6Fh
E70h
Accesses
70h 7Fh
DFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 30
F00h
F01h
F02h
F03h
F04h
F05h
F06h
F07h
F08h
F09h
F0Ah
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
Unimplemented
Read as 0
EEFh
EF0h
Accesses
70h 7Fh
E7Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
BANK 31
F80h
F81h
F82h
F83h
F84h
F85h
F86h
F87h
F88h
F89h
F8Ah
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
F98h
F99h
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
Unimplemented
Read as 0
F6Fh
F70h
Accesses
70h 7Fh
EFFh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
FEFh
FF0h
Accesses
70h 7Fh
F7Fh
Accesses
70h 7Fh
FFFh
PIC16F193X/LF193X
DS41364B-page 32
TABLE 2-9:
PIC16F193X/LF193X
TABLE 2-10:
PIC16F1933/1936/1938
MEMORY MAP, BANK 15
TABLE 2-11:
Bank 15
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
PIC16F1934/1937/1939
MEMORY MAP, BANK 15
Bank 15
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
LCDSE0
LCDSE1
LCDDATA0
LCDDATA1
LCDDATA3
LCDDATA4
LCDDATA6
LCDDATA7
LCDDATA9
LCDDATA10
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
LCDSE0
LCDSE1
LCDSE2
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
Unimplemented
Read as 0
Unimplemented
Read as 0
7EFh
7EFh
Legend:
Legend:
= Unimplemented data memory locations,
read as 0.
Preliminary
DS41364B-page 33
PIC16F193X/LF193X
TABLE 2-12:
PIC16F193X/LF193X MEMORY
MAP, BANK 31
Bank 31
F8Ch
Unimplemented
Read as 0
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
= Unimplemented data memory locations,
read as 0.
DS41364B-page 34
Preliminary
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 0
000h(2)
INDF0
001h(2)
INDF1
002h(2)
PCL
003h(2)
STATUS
004h(2)
FSR0L
005h(2)
FSR0H
006h(2)
FSR1L
007h(2)
FSR1H
008h(2)
BSR
009h(2)
WREG
00Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
00Bh(2)
INTCON
00Ch
PORTA
00Dh
PORTB
00Eh
PORTC
00Fh(3)
PORTD
010h
PORTE
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
RE3
RE2(3)
RE1(3)
RE0(3)
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
012h
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
013h
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
014h
PIR4
Unimplemented
015h
TMR0
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
018h
T1CON
TMR1CS1 TMR1CS0
019h
T1GCON
TMR1GE
01Ah
TMR2
01Bh
PR2
01Ch
T2CON
T1GPOL
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
01Dh
01Eh
CPSCON0
CPSON
01Fh
CPSCON1
Legend:
Note 1:
2:
3:
Unimplemented
Preliminary
CPSCH2
CPSCH1
T0XCS
DS41364B-page 35
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 1
080h(2)
INDF0
081h(2)
INDF1
082h(2)
PCL
083h(2)
STATUS
084h(2)
FSR0L
085h(2)
FSR0H
086h(2)
FSR1L
087h(2)
FSR1H
088h(2)
BSR
089h(2)
WREG
08Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
08Bh(2)
INTCON
08Ch
TRISA
08Dh
TRISB
08Eh
TRISC
08Fh(3)
TRISD
090h
TRISE
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
TRISE3
091h
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
092h
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
093h
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
094h
095h
OPTION_REG
WPUEN
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
096h
PCON
STKOVF
STKUNF
RMCLR
RI
POR
BOR
097h
WDTCON
WDTPS4
WDTPS3
WDTPS2
WDTPS1
098h
OSCTUNE
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
099h
OSCCON
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
SCS1
SCS0
09Ah
OSCSTAT
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFR
09Bh
ADRESL
09Ch
ADRESH
09Dh
ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
09Eh
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
ADNREF
09Fh
Legend:
Note 1:
2:
3:
DS41364B-page 36
Unimplemented
Unimplemented
GO/DONE
ADON
Preliminary
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 2
100h(2)
INDF0
101h(2)
INDF1
102h(2)
PCL
103h(2)
STATUS
104h(2)
FSR0L
105h(2)
FSR0H
106h(2)
FSR1L
107h(2)
FSR1H
108h(2)
BSR
109h(2)
WREG
10Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
10Bh(2)
INTCON
10Ch
LATA
10Dh
LATB
10Eh
LATC
10Fh(3)
LATD
110h
LATE
111h
CM1CON0
C1ON
C1OUT
112h
CM1CON1
C1INTP
C1INTN
113h
CM2CON0
C2ON
C2OUT
114h
CM2CON1
C2INTP
115h
CMOUT
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
LATE3
LATE2(3)
C1OE
C1POL
C1PCH1
C1PCH0
C2OE
C2POL
C2INTN
C2PCH1
IOCIF
INTF
LATE1(3)
C1SP
C1HYS
C1NCH1
C2SP
C2HYS
C2PCH0
C2NCH1
116h
BORCON
SBOREN
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0 ADFVR1
118h
DACCON0
DACEN
DACLPS
DACOE
---
DACPSS1
DACPSS0
---
119h
DACCON1
---
---
---
DACR4
DACR3
DACR2
DACR1
DACR0
11Ah
SRCON0
SRLEN
SRCLK2
SRCLK1
SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
11Bh
SRCON1
SRSPE
SRSCKE
SRSC2E
SRSC1E
SRRPE
SRRCKE
SRRC2E
T1GSEL
P2BSEL
SSSEL
11Ch
11Dh
APFCON
11Eh
Unimplemented
11Fh
Unimplemented
Legend:
Note 1:
2:
3:
Unimplemented
CCP3SEL
SRNQSEL C2OUTSEL
Preliminary
DS41364B-page 37
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 3
180h(2)
INDF0
181h(2)
INDF1
182h(2)
PCL
183h(2)
STATUS
184h(2)
FSR0L
185h(2)
FSR0H
186h(2)
FSR1L
187h(2)
FSR1H
188h(2)
BSR
189h(2)
WREG
18Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
18Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
18Ch
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
18Dh
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
18Eh
18Fh(3)
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
ANSE2
ANSE1
ANSE0
190h(3)
ANSELE
191h
EEADRL
192h
EEADRH
Unimplemented
193h
EEDATL
194h
EEDATH
195h
EECON1
EEPGD
CFGS
196h
EECON2
197h
Unimplemented
198h
Unimplemented
199h
RCREG
19Ah
TXREG
19Bh
SPBRGL
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
19Ch
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
Legend:
Note 1:
2:
3:
DS41364B-page 38
FREE
WRERR
WREN
WR
Preliminary
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 4
200h(2)
INDF0
201h(2)
INDF1
202h(2)
PCL
203h(2)
STATUS
204h(2)
FSR0L
205h(2)
FSR0H
206h(2)
FSR1L
207h(2)
FSR1H
208h(2)
BSR
209h(2)
WREG
20Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
20Bh(2)
INTCON
20Ch
20Dh
WPUB
20Eh
Unimplemented
20Fh
Unimplemented
210h
WPUE
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
Unimplemented
WPUB7
WPUB6
WPUE3
211h
SSPBUF
212h
SSPADD
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
213h
SSPMSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
214h
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
215h
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
216h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
217h
SSPCON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
218h
Unimplemented
219h
Unimplemented
21Ah
Unimplemented
21Bh
Unimplemented
21Ch
Unimplemented
21Dh
Unimplemented
21Eh
Unimplemented
21Fh
Unimplemented
Legend:
Note 1:
2:
3:
Preliminary
DS41364B-page 39
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 5
280h(2)
INDF0
281h(2)
INDF1
282h(2)
PCL
283h(2)
STATUS
284h(2)
FSR0L
285h(2)
FSR0H
286h(2)
FSR1L
287h(2)
FSR1H
288h(2)
BSR
289h(2)
WREG
28Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
28Bh(2)
INTCON
28Ch
Unimplemented
28Dh
Unimplemented
28Eh
Unimplemented
28Fh
Unimplemented
290h
Unimplemented
291h
CCPR1L
292h
CCPR1H
293h
CCP1CON
294h
PWM1CON
295h
CCP1AS
296h
PSTR1CON
297h
Unimplemented
298h
CCPR2L
299h
CCPR2H
29Ah
CCP2CON
29Bh
PWM2CON
29Ch
CCP2AS
GIE
PEIE
P1M1
P1M0
P1RSEN
P1DC6
CCP1ASE CCP1AS2
TMR0IE
DC1B1
INTE
IOCIE
TMR0IF
INTF
IOCIF
DC1B0
CCP1M3
P1DC5
P1DC4
P1DC3
CCP1AS1
CCP1AS0
PSS1AC1
STR1SYNC
STR1D
CCP1M2
CCP1M1
P1DC2
P1DC1
STR1B
STR1A
P2M1
P2M0
P2RSEN
P2DC6
CCP2ASE CCP2AS2
DC2B1
DC2B0
CCP2M3
P2DC5
P2DC4
P2DC3
CCP2AS1
CCP2AS0
PSS2AC1
CCP2M2
CCP2M1
P2DC2
P2DC1
29Dh
PSTR2CON
STR2SYNC
STR2D
29Eh
CCPTMRS0
C4TSEL1
C4TSEL0
C3TSEL1
C3TSEL0
C2TSEL1
29Fh
CCPTMRS1
Legend:
Note 1:
2:
3:
DS41364B-page 40
Preliminary
STR2C
STR2B
STR2A
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 6
300h(2)
INDF0
301h(2)
INDF1
302h(2)
PCL
303h(2)
STATUS
304h(2)
FSR0L
305h(2)
FSR0H
306h(2)
FSR1L
307h(2)
FSR1H
308h(2)
BSR
309h(2)
WREG
30Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
30Bh(2)
INTCON
30Ch
Unimplemented
30Dh
Unimplemented
30Eh
Unimplemented
30Fh
Unimplemented
310h
Unimplemented
311h
CCPR3L
312h
CCPR3H
313h
CCP3CON
314h
PWM3CON
315h
CCP3AS
316h
PSTR3CON
317h
Unimplemented
318h
CCPR4L
319h
CCPR4H
31Ah
CCP4CON
GIE
PEIE
P3M1
P3M0
P3RSEN
P3DC6
CCP3ASE CCP3AS2
TMR0IE
DC3B1
INTE
DC3B0
IOCIE
TMR0IF
INTF
IOCIF
P3DC5
P3DC4
P3DC3
CCP3AS1
CCP3AS0
PSS3AC1
STR3SYNC
STR3D
CCP3M2
CCP3M1
P3DC2
P3DC1
STR3B
STR3A
DC4B1
DC4B0
CCP4M2
CCP4M1
31Bh
Unimplemented
31Ch
CCPR5L
31Dh
CCPR5H
31Eh
CCP5CON
31Fh
Legend:
Note 1:
2:
3:
DC5B1
DC5B0
Unimplemented
CCP5M2
CCP5M1
Preliminary
DS41364B-page 41
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 7
380h(2)
INDF0
381h(2)
INDF1
382h(2)
PCL
383h(2)
STATUS
384h(2)
FSR0L
385h(2)
FSR0H
386h(2)
FSR1L
387h(2)
FSR1H
388h(2)
BSR
389h(2)
WREG
38Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
38Bh(2)
INTCON
38Ch
Unimplemented
38Dh
Unimplemented
38Eh
Unimplemented
38Fh
Unimplemented
390h
Unimplemented
391h
Unimplemented
392h
Unimplemented
393h
Unimplemented
394h
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
395h
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
396h
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
397h
Unimplemented
398h
Unimplemented
399h
Unimplemented
39Ah
Unimplemented
39Bh
Unimplemented
39Ch
Unimplemented
39Dh
Unimplemented
39Eh
Unimplemented
39Fh
Unimplemented
Legend:
Note 1:
2:
3:
DS41364B-page 42
GIE
PEIE
TMR0IE
INTE
IOCIE
Preliminary
TMR0IF
INTF
IOCIF
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 8
400h(2)
INDF0
401h(2)
INDF1
402h(2)
PCL
403h(2)
STATUS
404h(2)
FSR0L
405h(2)
FSR0H
406h(2)
FSR1L
407h(2)
FSR1H
408h(2)
BSR
409h(2)
WREG
40Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
40Bh(2)
INTCON
40Ch
Unimplemented
40Dh
Unimplemented
40Eh
Unimplemented
40Fh
Unimplemented
410h
Unimplemented
411h
Unimplemented
412h
Unimplemented
413h
Unimplemented
414h
Unimplemented
415h
TMR4
416h
PR4
417h
T4CON
418h
Unimplemented
419h
Unimplemented
41Ah
Unimplemented
41Bh
Unimplemented
41Ch
TMR6
41Dh
PR6
41Eh
T6CON
41Fh
Legend:
Note 1:
2:
3:
GIE
PEIE
T4OUTPS3
T6OUTPS3
TMR0IE
INTE
IOCIE
INTF
IOCIF
T4OUTPS1
T4OUTPS0
T6OUTPS1
T6OUTPS0
Unimplemented
TMR0IF
Preliminary
DS41364B-page 43
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Banks 9-14
x00h/
x80h(2)
INDF0
x00h/
x81h(2)
INDF1
x02h/
x82h(2)
PCL
x03h/
x83h(2)
STATUS
x04h/
x84h(2)
FSR0L
x05h/
x85h(2)
FSR0H
x06h/
x86h(2)
FSR1L
x07h/
x87h(2)
FSR1H
x08h/
x88h(2)
BSR
x09h/
x89h(2)
WREG
x0Ah/
PCLATH
x8Ah(1),(2)
TO
BSR4
PD
BSR3
BSR2
DC
BSR1
BSR0
Working Register
x0Bh/
x8Bh(2)
INTCON
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note 1:
2:
3:
DS41364B-page 44
GIE
PEIE
TMR0IE
INTE
IOCIE
Unimplemented
TMR0IF
INTF
IOCIF
Preliminary
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 15
780h(2)
INDF0
781h(2)
INDF1
782h(2)
PCL
783h(2)
STATUS
784h(2)
FSR0L
785h(2)
FSR0H
786h(2)
FSR1L
787h(2)
FSR1H
788h(2)
BSR
789h(2)
WREG
78Ah(1, 2) PCLATH
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
78Bh(2)
INTCON
78Ch
Unimplemented
78Dh
Unimplemented
78Eh
Unimplemented
78Fh
Unimplemented
790h
Unimplemented
791h
LCDCON
792h
LCDPS
793h
LCDREF
794h
LCDCST
795h
LCDRL
796h
Unimplemented
797h
Unimplemented
798h
LCDSE0
GIE
PEIE
LCDEN
SLPEN
WFT
LCDIRE
TMR0IE
INTE
IOCIE
WERR
BIASMD
LCDA
WA
LP3
LCDIRS
LCDIRI
VLCD3PE
LRLAP1
LRLAP0
LRLBP1
LRLBP0
SE7
SE6
SE5
SE4
CS1
SE3
TMR0IF
INTF
IOCIF
CS0
LMUX1
LMUX0
LP2
LP1
LP0
VLCD2PE VLCD1PE
SE2
LRLAT1
SE1
LRLAT0
SE0
799h
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
79Ah
LCDSE2(3)
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16
79Bh
Unimplemented
79Ch
Unimplemented
79Dh
Unimplemented
79Eh
Unimplemented
79Fh
Unimplemented
7A0h
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
7A1h
LCDDATA1
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
7A2h
LCDDATA2(3)
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
7A3h
LCDDATA3
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
7A4h
LCDDATA4
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
7A5h
LCDDATA5(3)
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
Legend:
Note 1:
2:
3:
Preliminary
DS41364B-page 45
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 15 (Continued)
7A6h
LCDDATA6
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
7A7h
LCDDATA7
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
7A8h
LCDDATA8(3)
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
7A9h
LCDDATA9
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
7AAh
LCDDATA10
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
7ABh
LCDDATA11(3)
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
7ACh
7EFh
Legend:
Note 1:
2:
3:
DS41364B-page 46
Unimplemented
Preliminary
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Banks 16-30
x00h/
x80h(2)
INDF0
x00h/
x81h(2)
INDF1
x02h/
x82h(2)
PCL
x03h/
x83h(2)
STATUS
x04h/
x84h(2)
FSR0L
x05h/
x85h(2)
FSR0H
x06h/
x86h(2)
FSR1L
x07h/
x87h(2)
FSR1H
x08h/
x88h(2)
BSR
x09h/
x89h(2)
WREG
x0Ah/
PCLATH
x8Ah(1),(2)
TO
BSR4
PD
BSR3
BSR2
DC
BSR1
BSR0
Working Register
x0Bh/
x8Bh(2)
INTCON
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note 1:
2:
3:
GIE
PEIE
TMR0IE
INTE
IOCIE
Unimplemented
TMR0IF
INTF
IOCIF
Preliminary
DS41364B-page 47
PIC16F193X/LF193X
TABLE 2-13:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other
Resets
Bank 31
F80h(2)
INDF0
F81h(2)
INDF1
F82h(2)
PCL
F83h(2)
STATUS
F84h(2)
FSR0L
F85h(2)
FSR0H
F86h(2)
FSR1L
F87h(2)
FSR1H
F88h(2)
BSR
F89h(2)
WREG
F8Ah(1),(2 PCLATH
)
F8Bh(2)
INTCON
F8Ch
FE3h
FE4h
TO
BSR4
DC
BSR2
BSR1
BSR0
Working Register
GIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
Unimplemented
STATUS_
DC
SHAD
FE5h
WREG_
SHAD
FE6h
BSR_
SHAD
FE7h
PCLATH_
SHAD
FE8h
FSR0L_
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
Unimplemented
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend:
Note 1:
2:
3:
DS41364B-page 48
Preliminary
PIC16F193X/LF193X
2.2.3
CORE REGISTERS
INDF0
INDF1
PCL
STATUS
FSR0 Low
FSR0 High
FSR1 Low
FSR1 High
BSR
WREG
PCLATH
INTCON
Note:
Preliminary
DS41364B-page 49
PIC16F193X/LF193X
2.2.3.1
STATUS Register
REGISTER 2-1:
U-0
U-0
R-1/q
TO
R-1/q
PD
R/W-x/x
R/W-x/x
R/W-x/x
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41364B-page 50
Preliminary
PIC16F193X/LF193X
2.2.3.2
OPTION register
REGISTER 2-2:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Preliminary
DS41364B-page 51
PIC16F193X/LF193X
2.3
2.3.3
FIGURE 2-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
14
PCH
PCL
PC
Instruction with
PCL as
Destination
ALU Result
PCLATH
14
PCH
PCL
PC
GOTO, CALL
PCLATH
14
11
PCH
PCL
0
CALLW
PCLATH
14
PCH
PCL
BRW
15
PC + W
14
PCH
PCL
PC
2.4
0
BRA
15
PC + OPCODE <8:0>
2.3.1
MODIFYING PCL
2.3.2
COMPUTED GOTO
DS41364B-page 52
BRANCHING
PC
2.3.4
OPCODE <10:0>
PC
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
Stack
Preliminary
PIC16F193X/LF193X
2.4.1
2.5
2.4.2
OVERFLOW/UNDERFLOW RESET
Preliminary
DS41364B-page 53
PIC16F193X/LF193X
FIGURE 2-5:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
Reserved
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
DS41364B-page 54
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for
memory limits.
Preliminary
PIC16F193X/LF193X
2.5.1
FIGURE 2-6:
BSR
Indirect Addressing
From Opcode
0
Bank Select
Location Select
0000
FSRxH
0
FSRxL
0
Bank Select
0001 0010
Location Select
1111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Preliminary
Bank 31
DS41364B-page 55
PIC16F193X/LF193X
2.5.2
2.5.3
FIGURE 2-7:
7
FSRnH
0 0 1
FSRnL
FIGURE 2-8:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS41364B-page 56
0xFFFF
0x7FFF
0xF6F
Preliminary
PIC16F193X/LF193X
3.0
RESETS
The PIC16F193X/LF193X
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
differentiates
between
FIGURE 3-1:
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset
BOR
Enable
OST/PWRT
OST(2)
1024 Cycles
Chip_Reset
OSC1
PWRT(2) 64 ms
LFINTOSC
Enable PWRT
Enable OST(1)
Note 1:
2:
Preliminary
DS41364B-page 57
PIC16F193X/LF193X
TABLE 3-1:
STKOVF STKUNF
RMCLR
RI
POR
BOR
TO
PD
Condition
Brown-out Reset
WDT Reset
TABLE 3-2:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
PC + 1
(1)
0000h
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS41364B-page 58
Preliminary
PIC16F193X/LF193X
3.1
MCLR
3.3
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
VDD
3.4
(Section 28.0
PIC MCU
R1
10 k
MCLR
C1
0.1 F
3.4.1
3.2
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 28.0 Electrical Specifications for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
Brown-Out Reset (BOR)).
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz internal
oscillator.
Note:
Preliminary
DS41364B-page 59
PIC16F193X/LF193X
3.4.2
WDT CONTROL
FIGURE 3-3:
WDTE<1:0> = 00
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 01
SWDTEN
WDTPS<4:0>
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep
TABLE 3-3:
WDT STATUS
Conditions
WDT
WDTE<1:0> = 00
Cleared
DS41364B-page 60
Unaffected
Preliminary
PIC16F193X/LF193X
REGISTER 3-1:
U-0
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
=
=
=
=
=
=
=
Preliminary
DS41364B-page 61
PIC16F193X/LF193X
3.5
TABLE 3-4:
BOREN
Config bits
SBOREN
Device Mode
BOR Mode
Device
Device
Operation upon
Operation upon
wake- up from
release of POR
Sleep
BOR_ON (11)
Active
BOR_NSLEEP (10)
Awake
Active
BOR_NSLEEP (10)
Sleep
Disabled
BOR_SBOREN (01)
Active
Begins immediately
BOR_SBOREN (01)
Disabled
Begins immediately
BOR_OFF (00)
Disabled
Begins immediately
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
startup.
FIGURE 3-4:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
VBOR
Internal
Reset
Note 1:
64 ms(1)
DS41364B-page 62
Preliminary
PIC16F193X/LF193X
REGISTER 3-2:
R/W-1/u
U-0
U-0
U-0
U-0
U-0
U-0
R/W-q/u
SBOREN
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-1
Unimplemented: Read as 0
bit 0
Preliminary
DS41364B-page 63
PIC16F193X/LF193X
3.5.1
BOR HIBERNATE/REARM
The BOR circuit has an output that feeds into the POR
circuit and rearms the POR within the operating range
of the BOR. This early rearming of the POR ensures
that the device will remain in Reset in the event that
VDD falls below the operating range of the BOR
circuitry.
3.6
Reset Instruction
3.7
Stack Overflow/Underflow
3.8
DS41364B-page 64
Preliminary
PIC16F193X/LF193X
3.9
3.9.1
PCON REGISTER
REGISTER 3-3:
R/W-0/q
R/W-0/q
U-0
U-0
R/W-1/q
R/W-1/q
R/W-q/u
R/W-q/u
STKOVF
STKUNF
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41364B-page 65
PIC16F193X/LF193X
TABLE 3-5:
PWRTE = 1
XT, HS, LP
64 ms + 1024 TOSC
1024 TOSC
1024 TOSC
External RC
64 ms
EC
64 ms
64 ms
1 s
1 s
Oscillator Configuration
INTOSC
Note 1:
TABLE 3-6:
STKOVF STKUNF
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
Legend:
u = unchanged, x = unknown
FIGURE 3-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS41364B-page 66
Preliminary
PIC16F193X/LF193X
FIGURE 3-6:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 3-7:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
Preliminary
DS41364B-page 67
PIC16F193X/LF193X
RESET CONDITION FOR SPECIAL REGISTERS(2)
TABLE 3-7:
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
Condition
PC + 1
(1)
0000h
---u uuuu
uu-- u0uu
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
TABLE 3-8:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORRDY
63
PCON
STKOVF
STKUNF
RMCLR
RI
POR
BOR
65
STATUS
TO
PD
DC
50
WDTCON
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0 SWDTEN
61
DS41364B-page 68
Preliminary
PIC16F193X/LF193X
4.0
INTERRUPTS
FIGURE 4-1:
INTERRUPT LOGIC
Interrupt to CPU
INTE
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 4-2)
PEIE
GIE
Preliminary
DS41364B-page 69
PIC16F193X/LF193X
FIGURE 4-2:
TMR1GIF
TMR1GIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
CCP5IF
CCP5IE
OSFIF
OSFIE
TMR1IF
TMR1IE
To Interrupt Logic
(Figure 4-1)
TMR6IF
TMR6IE
C2IF
C2IE
C1IF
C1IE
EEIF
EEIE
BCLIF
BCLIE
LCDIF
LCDIE
DS41364B-page 70
Preliminary
PIC16F193X/LF193X
4.1
Operation
4.2
FIGURE 4-3:
Interrupt Latency
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON<1>)
(5)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 28.0 Electrical Specifications.
5:
Preliminary
DS41364B-page 71
PIC16F193X/LF193X
4.3
4.5
4.4
INT Pin
Context Saving
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exit from the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. Depending
on the users application, other registers may also need
to be saved.
DS41364B-page 72
Preliminary
PIC16F193X/LF193X
4.5.1
INTCON REGISTER
Note:
REGISTER 4-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF(1)
INTF
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing TMR0IF bit.
Preliminary
DS41364B-page 73
PIC16F193X/LF193X
4.5.2
PIE1 REGISTER
REGISTER 4-2:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41364B-page 74
Preliminary
PIC16F193X/LF193X
4.5.3
PIE2 REGISTER
REGISTER 4-3:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Preliminary
DS41364B-page 75
PIC16F193X/LF193X
4.5.4
PIE3 REGISTER
REGISTER 4-4:
Note:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Unimplemented: Read as 0
DS41364B-page 76
Preliminary
PIC16F193X/LF193X
4.5.5
PIR1 REGISTER
REGISTER 4-5:
Note:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41364B-page 77
PIC16F193X/LF193X
4.5.6
PIR2 REGISTER
REGISTER 4-6:
Note:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS41364B-page 78
Preliminary
PIC16F193X/LF193X
4.5.7
PIR3 REGISTER
REGISTER 4-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
Unimplemented: Read as 0
Preliminary
DS41364B-page 79
PIC16F193X/LF193X
TABLE 4-1:
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
51
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
OPTION_REG WPUEN
PIE1
TMR1GIE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
79
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
Interrupts.
DS41364B-page 80
Preliminary
PIC16F193X/LF193X
5.0
Preliminary
DS41364B-page 81
PIC16F193X/LF193X
NOTES:
DS41364B-page 82
Preliminary
PIC16F193X/LF193X
6.0
I/O PORTS
FIGURE 6-1:
Read LATx
D
Write LATx
Write PORTx
TRISx
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTx
To peripherals
VSS
ANSELx
Preliminary
DS41364B-page 83
PIC16F193X/LF193X
6.1
SS (Slave Select)
CCP2
CCP3
Timer1 Gate
SR Latch SRNQ output
Comparator C2 output
REGISTER 6-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCP3SEL
T1GSEL
P2BSEL
SRNQSEL
C2OUTSEL
SSSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41364B-page 84
Preliminary
PIC16F193X/LF193X
6.2
PORTA Registers
Note:
EXAMPLE 6-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
REGISTER 6-2:
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
0Ch
TRISA
INITIALIZING PORTA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<3:2> as inputs
;and set RA<7:4,1:0>
;as outputs
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
RA<7:0>: PORTA I/O Value bits(1)
bit 7-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 6-3:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
Preliminary
DS41364B-page 85
PIC16F193X/LF193X
6.2.1
ANSELA REGISTER
REGISTER 6-4:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 6-5:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS41364B-page 86
Preliminary
PIC16F193X/LF193X
6.2.2
RA1
1.
2.
SEG7 (LCD)
RA1
RA2
1.
2.
3.
COM2 (LCD)
DACOUT (DAC)
RA2
RA3
1.
2.
3.
RA4
1.
2.
3.
4.
5.
SEG4 (LCD)
SRQ (SR Latch)
C1OUT (Comparator)
CCP5 (CCP), 28-pin only
RA4
RA5
1.
2.
3.
4.
5.
RA6
1.
2.
3.
4.
5.
RA7
1.
2.
3.
Preliminary
DS41364B-page 87
PIC16F193X/LF193X
TABLE 6-1:
Name
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
137
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
ADREF
ADREF1
ADREF0
138
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
86
APFCON
CCP3SEL
T1GSEL
P2BSEL
SSSEL
CCP2SEL
84
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
148
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2HYS
C2SYNC
148
CPSCON0
CPSON
CPSCON1
CONFIG2(1)
DACCON0
DACEN
DACLPS
VCAPEN1 VCAPEN0
DACOE
---
SRNQSEL C2OUTSEL
CPSRNG1 CPSRNG0
CPSOUT
T0XCS
180
CPSCH3
CPSCH2
CPSCH1
CPSCH0
181
128
---
DACNSS
153
DACPSS1 DACPSS0
LATA
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
85
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
247
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
247
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
51
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
85
SRCON0
SRLEN
SRCLK2
SRCLK1
SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
122
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
277
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
OPTION_REG
PORTA
TRISA
Legend:
Note 1:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
PIC16F193X only.
DS41364B-page 88
Preliminary
PIC16F193X/LF193X
6.3
6.3.1
WEAK PULL-UPS
6.3.2
INTERRUPT-ON-CHANGE
EXAMPLE 6-2:
INITIALIZING PORTB
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
PORTB
PORTB
ANSELB
ANSELB
TRISB
B11110000
MOVWF
TRISB
Note:
;
;Init PORTB
;Make RB<7:0> digital
;
;Set RB<7:4> as inputs
;and RB<3:0> as outputs
;
Preliminary
DS41364B-page 89
PIC16F193X/LF193X
REGISTER 6-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 6-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
LATB<7:0>: PORTB Output Latch Value bits(1)
bit 7-0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 6-8:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
DS41364B-page 90
Preliminary
PIC16F193X/LF193X
6.3.3
ANSELB REGISTER
REGISTER 6-9:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 6-10:
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Preliminary
DS41364B-page 91
PIC16F193X/LF193X
6.3.4
CCP2/P2A
RB3
RB4
1.
2.
3.
COM0
P1D, 28-pin only
RB4
RB5
COM1
P2B, 28-pin only
P3A
RB5
RB6
1.
2.
3.
4.
RB2
1.
2.
1.
2.
1.
2.
3.
4.
SEG0 (LCD)
CCP4, 28-pin only
RB0
RB1
1.
2.
RB3
RB7
1.
2.
3.
4.
TABLE 6-2:
ICSPCLK (Programming)
ICDCLK (enabled by Configuration Word)
SEG14 (LCD)
RB6
ICSPDAT (Programming)
ICDDAT (enabled by Configuration Word)
SEG13 (LCD)
RB7
Name
Bit 7
Bit 6
Bit 5
Bit 4
ADCON0
CHS4
CHS3
CHS2
ANSELB
ANSB5
ANSB4
Bit 3
Bit 0
Register
on Page
GO/DONE
ADON
137
ANSB1
ANSB0
91
Bit 2
Bit 1
CHS1
CHS0
ANSB3
ANSB2
CCP3SEL
T1GSEL
P2BSEL
SRNQSEL
C2OUTSEL
SSSEL
CCP2SEL
84
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
CPSCON0
CPSON
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
180
CPSCON1
CPSCH3
CPSCH2
CPSCH1
CPSCH0
181
APFCON
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
104
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
104
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
104
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
90
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
247
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
247
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
51
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
90
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/DONE
T1GVAL
T1GSS1
T1GSS0
170
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
90
OPTION_REG
PORTB
T1GCON
TRISB
WPUB
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTB.
DS41364B-page 92
Preliminary
PIC16F193X/LF193X
6.4
REGISTER 6-11:
EXAMPLE 6-3:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTC
PORTC
PORTC
TRISC
B00001100
TRISC
;
;Init PORTC
;
;Set RC<3:2> as inputs
;and set RC<7:4,1:0>
;as outputs
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 6-12:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
Preliminary
DS41364B-page 93
PIC16F193X/LF193X
REGISTER 6-13:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS41364B-page 94
Preliminary
PIC16F193X/LF193X
6.4.1
RC5
SEG10 (LCD)
SDL (MSSP)
RC5
RC6
1.
2.
3.
4.
5.
SEG9 (LCD)
TX (EUSART)
CK (EUSART)
P3A (CCP), 28-pin only
RC6
RC7
1.
2.
3.
4.
RC1
1.
2.
3.
1.
2.
3.
SEG8 (LCD)
DT (EUSART)
P3B (CCP), 28 pin only
RC7
RC1
1.
2.
3.
SEG3 (LCD)
P1A (CCP)
RC2
RC3
1.
2.
3.
4.
SEG6 (LCD)
SCL (MSSP)
SCK (MSSP)
RC3
RC4
1.
2.
3.
SEG11 (LCD)
SDA (MSSP)
RC4
TABLE 6-3:
Name
APFCON
CCPxCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CCP3SEL
T1GSEL
P2BSEL
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
SRNQSEL C2OUTSEL
Register
on Page
Bit 1
Bit 0
SSSEL
CCP2SEL
84
CCPxM1
CCPxM0
184
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
93
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
247
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
247
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
93
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
277
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
276
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
169
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
222
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TRISC
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTC.
Preliminary
DS41364B-page 95
PIC16F193X/LF193X
6.5
EXAMPLE 6-4:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTD
PORTD
PORTD
ANSELD
ANSELD
TRISD
B00001100
TRISD
;
;Init PORTD
;Make PORTD digital
;
;Set RD<3:2> as inputs
;and set RD<7:4,1:0>
;as outputs
REGISTER 6-14:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
REGISTER 6-15:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
LATD<7:0>: PORTD Output Latch Value bits(1,2)
bit 7-0
Note 1:
2:
Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
DS41364B-page 96
Preliminary
PIC16F193X/LF193X
6.5.1
ANSELD REGISTER
REGISTER 6-16:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
REGISTER 6-17:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
2:
3:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELD register is not implemented on the PIC16F1933/1936/1938. Read as 0.
PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
Preliminary
DS41364B-page 97
PIC16F193X/LF193X
6.5.2
RD4
1.
2.
3.
RD5
1.
2.
3.
RD0
RD6
1.
2.
COM3 (LCD)
RD0
1.
2.
3.
CCP4 (CCP)
RD1
RD7
RD1
1.
2.
1.
2.
3.
RD2
1.
2.
P2B (CCP)
RD2
SEG17 (LCD)
P2D (CCP)
RD4
SEG18 (LCD)
P1B (CCP)
RD5
SEG19 (LCD)
P1C (CCP)
RD6
SEG20 (LCD)
P1D (CCP)
RD7
RD3
1.
2.
3.
SEG16 (LCD)
P2C (CCP)
RD3
TABLE 6-4:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
97
CCPxCON
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CPSCON0
CPSON
Name
ANSELD
CPSCON1
CPSRNG1 CPSRNG0
CCPxM1
CCPxM0
184
CPSOUT
T0XCS
180
CPSCH3
CPSCH2
CPSCH1
CPSCH0
181
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
96
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
LCDSE2
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16
247
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
96
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
97
Legend:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTD.
Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as 0.
DS41364B-page 98
Preliminary
PIC16F193X/LF193X
6.6
EXAMPLE 6-5:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
REGISTER 6-18:
INITIALIZING PORTE
PORTE
PORTE
ANSELE
ANSELE
TRISE
B00001100
TRISE
;
;Init PORTE
;
;digital I/O
;
;Set RE<3:2> as inputs
;and set RE<1:0>
;as outputs
U-0
U-0
U-0
U-0
R-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RE3
RE2(1)
RE1(1)
RE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
REGISTER 6-19:
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATE3
LATE2
LATE1
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is
return of actual I/O pin values.
Preliminary
DS41364B-page 99
PIC16F193X/LF193X
REGISTER 6-20:
U-0
U-0
U-0
R/W-1/1
U-0
U-0
U-0
WPUE3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2-0
Note 1:
2:
Unimplemented: Read as 0
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
DS41364B-page 100
Preliminary
PIC16F193X/LF193X
6.6.1
ANSELE REGISTER
Note:
REGISTER 6-21:
U-0
U-0
U-0
U-0
R-1
R/W-1
R/W-1
R/W-1
TRISE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2-0
Note 1:
REGISTER 6-22:
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
ANSE2(2)
ANSE1(2)
ANSE0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as 0
Preliminary
DS41364B-page 101
PIC16F193X/LF193X
6.6.2
SEG21 (LCD)
CCP3/P3A (CCP)
RE0
RE1
1.
2.
3.
SEG22 (LCD)
P3B (CCP)
RE1
RE2
1.
2.
3.
SEG23 (LCD)
CCP5 (CCP)
RE2
TABLE 6-5:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
137
ANSELE
ANSE2
ANSE1
ANSE0
101
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
LATE3
LATE2
LATE1
LATE0
99
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
247
Name
CCPxCON
LATE
LCDSE2
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16
PORTE
RE3
RE2
RE1
RE0
99
TRISE
TRISE3
TRISE2
TRISE1
TRISE0
101
WPUE
WPUE3
100
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
PORTE.
Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as 0.
DS41364B-page 102
Preliminary
PIC16F193X/LF193X
7.0
INTERRUPT-ON-CHANGE
7.4
EXAMPLE 7-1:
MOVLW
XORWF
ANDWF
7.1
0xff
IOCBF, W
IOCBF, F
7.2
7.5
Operation in Sleep
7.3
Interrupt Flags
Preliminary
DS41364B-page 103
PIC16F193X/LF193X
REGISTER 7-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 7-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 7-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS41364B-page 104
Preliminary
PIC16F193X/LF193X
FIGURE 7-1:
IOCIE
IOCBNx
IOCBFx
CK
R
IOC Interrupt to
CPU Core
RBx
IOCBPx
CK
R
Q2 Clock Cycle
TABLE 7-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
91
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
104
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
104
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
104
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
Interrupt-on-Change.
Preliminary
DS41364B-page 105
PIC16F193X/LF193X
NOTES:
DS41364B-page 106
Preliminary
PIC16F193X/LF193X
8.0
8.1
Overview
1.
2.
3.
4.
5.
6.
FIGURE 8-1:
EC External clock.
LP 32 kHz Low-Power Crystal mode.
XT Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
HS High Gain Crystal or Ceramic Resonator
mode.
RC External Resistor-Capacitor (RC).
INTOSC Internal oscillator.
OSC2
Sleep
4 x PLL
Sleep
Oscillator Timer1
FOSC<2:0> = 100
T1OSO
31 kHz
Source
500 kHz
Source
16 MHz
(HFINTOSC)
500 kHz
(MFINTOSC)
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
MUX
Internal
Oscillator
Block
16 MHz
Source
IRCF<3:0>
Postscaler
T1OSI
T1OSCEN
Enable
Oscillator
31 kHz
31 kHz (LFINTOSC)
T1OSC
CPU and
Peripherals
MUX
OSC1
Internal Oscillator
Clock
Control
FOSC<2:0> SCS<1:0>
Clock Source Option
for other modules
Preliminary
DS41364B-page 107
PIC16F193X/LF193X
8.2
Oscillator Control
REGISTER 8-1:
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
U-0
R/W-0/0
R/W-0/0
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
31 kHz LF
31.25 kHz MF
31.25 kHz HF(2)
62.5 kHz MF
125 kHz MF
250 kHz MF
500 kHz MF (default upon Reset)
125 kHz HF(2)
250 kHz HF(2)
500 kHz HF(2)
1 MHz HF
2 MHz HF
4 MHz HF
8 MHz HF
16 MHz HF
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
2:
DS41364B-page 108
Preliminary
PIC16F193X/LF193X
8.3
TABLE 8-1:
8.4
8.4.1
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
Sleep/POR
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
EC, RC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC, RC(1)
DC 32 MHz
1 cycle of each
Sleep/POR
Timer1 Oscillator
LP, XT, HS(1)
32 kHz-20 MHz
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
1 cycle of each
Timer1 Oscillator
32 kHz
PLL inactive
PLL active
16-32 MHz
2 ms (approx.)
Note 1:
8.4.2
PLL inactive.
EC MODE
FIGURE 8-2:
Clock from
Ext. System
FOSC/4 or
I/O(1)
Note 1:
Preliminary
DS41364B-page 109
PIC16F193X/LF193X
8.4.3
FIGURE 8-3:
FIGURE 8-4:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC MCU
OSC1/CLKIN
C1
PIC MCU
OSC1/CLKIN
C1
To Internal
Logic
RP(3)
RF(2)
Sleep
To Internal
Logic
Quartz
Crystal
C2
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
RS(1)
RF(2)
C2 Ceramic
RS(1)
Resonator
Sleep
Note 1:
OSC2/CLKOUT
Note 1:
2:
DS41364B-page 110
Preliminary
OSC2/CLKOUT
PIC16F193X/LF193X
8.4.4
EXTERNAL RC MODE
8.5
FIGURE 8-5:
VDD
2.
EXTERNAL RC MODES
PIC MCU
REXT
OSC1/CLKIN
3.
Internal
Clock
CEXT
OSC2/CLKOUT
VSS
FOSC/4 or
I/O(1)
8.5.1
INTOSC MODE
Preliminary
DS41364B-page 111
PIC16F193X/LF193X
8.5.2
HFINTOSC
8.5.4
8.5.3
MFINTOSC
The
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 8-3).
LFINTOSC
LCD
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
DS41364B-page 112
Preliminary
PIC16F193X/LF193X
8.5.5
OSCSTAT REGISTER
REGISTER 8-2:
R-0/q
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
HFIOFL: High Frequency Internal Oscillator Status Locked bit (2% Stable)
1 = 16 MHz Internal Oscillator (HFINTOSC) is in lock
0 = 16 MHz Internal Oscillator (HFINTOSC) has not yet locked
bit 2
MFIOFR: Medium Frequency Internal Oscillator (500 kHz HFINTOSC Output) Ready bit
1 = 500 kHz Internal Oscillator (MFINTOSC) is ready and can be switched to
0 = 500 kHz Internal Oscillator (MFINTOSC) is not ready
bit 1
bit 0
Preliminary
DS41364B-page 113
PIC16F193X/LF193X
8.5.6
OSCTUNE REGISTER
REGISTER 8-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
000001 =
000000 = Oscillator module is running at the factory-calibrated frequency.
111111 =
DS41364B-page 114
Preliminary
PIC16F193X/LF193X
8.5.7
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz (Default after Reset)
250 kHz
125 kHz
31 kHz (LFINTOSC)
Note:
8.5.8
4.
5.
6.
7.
Preliminary
DS41364B-page 115
PIC16F193X/LF193X
FIGURE 8-6:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
=0
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
=0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
System Clock
DS41364B-page 116
Preliminary
PIC16F193X/LF193X
8.6
Clock Switching
8.7
8.6.1
8.6.2
8.6.3
8.7.1
Preliminary
DS41364B-page 117
PIC16F193X/LF193X
8.7.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
8.7.3
FIGURE 8-7:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
DS41364B-page 118
Preliminary
PIC16F193X/LF193X
8.8
8.8.3
FIGURE 8-8:
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
8.8.1
8.8.4
Clock Monitor
Latch
Note:
FAIL-SAFE DETECTION
8.8.2
FAIL-SAFE OPERATION
Preliminary
DS41364B-page 119
PIC16F193X/LF193X
FIGURE 8-9:
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
TABLE 8-2:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG1(2)
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
126
OSCCON
SPLLEN
IRCF3
IRCF2
IRCF1
IRCF0
SCS1
SCS0
108
OSCSTAT
T1OSCR
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
113
OSCTUNE
PIE2
PIR2
T1CON
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
114
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
OSFIF
C2IF
TMR1CS1 TMR1CS0
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
169
Legend: x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by
oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word Register 1 (Register 10-1) for operation of all register bits.
DS41364B-page 120
Preliminary
PIC16F193X/LF193X
9.0
SR LATCH
9.2
9.1
The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR
latch outputs may be directly output to an I/O pin at the
same time.
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
9.3
Latch Operation
FIGURE 9-1:
Latch Output
Effects of a Reset
SRPS
Pulse
Gen(2)
SRQEN
SRI
S
SRSPE
SRCLK
Q
SRQ
SRSCKE
SYNCC2OUT(3)
SRSC2E
SYNCC1OUT(3)
SRSC1E
SRPR
SR
Latch(1)
Pulse
Gen(2)
SRI
R
SRRPE
SRCLK
Q
SRNQ
SRRCKE
SYNCC2OUT(3)
SRRC2E
SRLEN
SRNQEN
SYNCC1OUT(3)
SRRC1E
Note 1:
2:
3:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1
Pulse generator causes a 1 Q-state pulse width.
Name denotes the connection point at the comparator output.
Preliminary
DS41364B-page 121
PIC16F193X/LF193X
TABLE 9-1:
SRCLK
Divider
FOSC = 32 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 4 MHz
FOSC = 1 MHz
111
512
110
256
62.5 kHz
39.0 kHz
31.3 kHz
7.81 kHz
1.95 kHz
125 kHz
78.1 kHz
62.5 kHz
15.6 kHz
3.90 kHz
101
100
128
250 kHz
156 kHz
125 kHz
31.25 kHz
7.81 kHz
64
500 kHz
313 kHz
250 kHz
62.5 kHz
15.6 kHz
011
32
1 MHz
625 kHz
500 kHz
125 kHz
31.3 kHz
010
16
2 MHz
1.25 MHz
1 MHz
250 kHz
62.5 kHz
001
4 MHz
2.5 MHz
2 MHz
500 kHz
125 kHz
000
8 MHz
5 MHz
4 MHz
1 MHz
250 kHz
REGISTER 9-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/S-0/0
R/S-0/0
SRLEN
SRCLK2
SRCLK1
SRCLK0
SRQEN
SRNQEN
SRPS
SRPR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
DS41364B-page 122
Preliminary
PIC16F193X/LF193X
REGISTER 9-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SRSPE
SRSCKE
SRSC2E
SRSC1E
SRRPE
SRRCKE
SRRC2E
SRRC1E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41364B-page 123
PIC16F193X/LF193X
NOTES:
DS41364B-page 124
Preliminary
PIC16F193X/LF193X
10.0
DEVICE CONFIGURATION
10.1
Configuration Words
Preliminary
DS41364B-page 125
PIC16F193X/LF193X
REGISTER 10-1:
CONFIGURATION WORD 1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
FCMEN
IESO
CLKOUTEN
BOREN1
BOREN0
CPD
CP
bit 13
bit 7
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
MCLRE
PWRTE
WDTE1
WDTE0
FOSC2
FOSC1
FOSC0
bit 6
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1:
2:
3:
DS41364B-page 126
Preliminary
PIC16F193X/LF193X
REGISTER 10-1:
bit 2-0
Note 1:
2:
3:
Preliminary
DS41364B-page 127
PIC16F193X/LF193X
REGISTER 10-2:
CONFIGURATION WORD 2
R/P-1/1
R/P-1/1
U-1
R/P-1/1
R/P-1/1
R/P-1/1
U-1
LVP
DEBUG
BORV
STVREN
PLLEN
bit 13
bit 7
U-1
R/P-1/1
R/P-1/1
U-1
U-1
R/P-1/1
R/P-1/1
VCAPEN1
VCAPEN0
WRT1
WRT0
bit 6
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 13
bit 12
bit 11
Unimplemented: Read as 1
bit 10
bit 9
bit 8
bit 7-6
Unimplemented: Read as 1
bit 5-4
bit 3-2
Unimplemented: Read as 1
bit 1-0
Note 1:
2:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
Reads as 11 on PIC16LF193X only.
DS41364B-page 128
Preliminary
PIC16F193X/LF193X
10.2
Code Protection
10.3
User ID
Preliminary
DS41364B-page 129
PIC16F193X/LF193X
NOTES:
DS41364B-page 130
Preliminary
PIC16F193X/LF193X
11.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 11-1:
VREF-
ADNREF = 0
AVDD
AVSS
ADPREF = 0X
ADPREF = 11
VREF+
AN0
00000
AN1
00001
AN2
00010
AN3
00011
AN4
00100
AN5
00101
AN6
00110
AN7
00111
AN8
01000
AN9
01001
AN10
01010
AN11
01011
AN12
01100
AN13
01101
Temp Sens
11101
DAC(2)
11110
FVR Buffer1
11111
ADPREF = 10
ADC
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
16
ADON
VSS
ADRESH
ADRESL
CHS<4:0>
Note 1:
2:
Preliminary
DS41364B-page 131
PIC16F193X/LF193X
11.1
11.1.4
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
11.1.1
11.1.2
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
PORT CONFIGURATION
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
CHANNEL SELECTION
CONVERSION CLOCK
11.1.3
DS41364B-page 132
Preliminary
PIC16F193X/LF193X
TABLE 11-1:
ADCS<2:0>
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
125 ns
(2)
(2)
(2)
(2)
1.0 s
4.0 s
Fosc/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
1.0 s
2.0 s
8.0 s(3)
Fosc/16
101
800 ns
800 ns
1.0 s
2.0 s
4.0 s
16.0 s(3)
Fosc/32
010
1.0 s
1.6 s
2.0 s
4.0 s
8.0 s(3)
32.0 s(3)
s(3)
64.0 s(3)
Fosc/64
FRC
Legend:
Note 1:
2:
3:
4:
110
2.0 s
x11
1.0-6.0 s
200 ns
3.2 s
(1,4)
1.0-6.0 s
250 ns
4.0 s
(1,4)
1.0-6.0 s
500 ns
8.0
(1,4)
s(3)
1.0-6.0 s
(1,4)
16.0
1.0-6.0 s
(1,4)
1.0-6.0 s(1,4)
FIGURE 11-2:
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Preliminary
DS41364B-page 133
PIC16F193X/LF193X
11.1.5
INTERRUPTS
11.1.6
RESULT FORMATTING
FIGURE 11-3:
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as 0
DS41364B-page 134
bit 0
bit 7
bit 0
10-bit A/D Result
Preliminary
PIC16F193X/LF193X
11.2
11.2.1
11.2.4
ADC Operation
STARTING A CONVERSION
11.2.2
COMPLETION OF A CONVERSION
11.2.3
TERMINATING A CONVERSION
11.2.5
Preliminary
DS41364B-page 135
PIC16F193X/LF193X
11.2.6
EXAMPLE 11-1:
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
DS41364B-page 136
Preliminary
PIC16F193X/LF193X
11.2.7
REGISTER 11-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
Preliminary
DS41364B-page 137
PIC16F193X/LF193X
REGISTER 11-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
ADFM
ADCS2
ADCS1
ADCS0
ADNREF
ADPREF1
ADPREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3
Unimplemented: Read as 0
bit 2
bit 1-0
REGISTER 11-3:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS41364B-page 138
Preliminary
PIC16F193X/LF193X
REGISTER 11-4:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
REGISTER 11-5:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 11-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Preliminary
DS41364B-page 139
PIC16F193X/LF193X
11.3
EQUATION 11-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
(2
)1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
(2
)1
T C = C HOLD ( R IC + R SS + R S ) ln(1/511)
= 10pF ( 1k + 7k + 10k ) ln(0.001957)
= 1.12 s
Therefore:
T ACQ = 2S + 1.12 S + [ ( 50C- 25C ) ( 0.05S /C ) ]
= 4.42 S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41364B-page 140
Preliminary
PIC16F193X/LF193X
FIGURE 11-4:
ANx
Rs
CPIN
5 pF
VA
VT 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
CHOLD = 10 pF
VSS/VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
= Sampling Switch
VT
= Threshold Voltage
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
FIGURE 11-5:
Full-Scale Range
FFh
FEh
FDh
ADC Output Code
FCh
1 LSB ideal
FBh
Full-Scale
Transition
04h
03h
02h
01h
00h
VSS
Zero-Scale
Transition
Preliminary
VREF
DS41364B-page 141
PIC16F193X/LF193X
TABLE 11-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ADCON0
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
137
ADCON1
ADFM
ADCS2
ADCS1
ADCS0
ADNREF
ADPREF1
ADPREF0
138
ADRESH
ADRESL
138
139
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
91
ANSELE
ANSE2
ANSE1
ANSE0
101
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
184
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
CCP2CON
INTCON
86
TRISE3
TRISE2
TRISE1
TRISE0
101
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
156
DACCON0
DACEN
DACLPS
DACOE
---
DACPSS1
DACPSS0
---
DACNSS
153
---
---
---
DACR4
DACR3
DACR2
DACR1
DACR0
153
TRISE
DACCON1
Legend:
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not
used for ADC module.
DS41364B-page 142
Preliminary
PIC16F193X/LF193X
12.0
COMPARATOR MODULE
FIGURE 12-1:
12.1
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
Comparator Overview
Preliminary
DS41364B-page 143
PIC16F193X/LF193X
FIGURE 12-2:
CxNCH<1:0>
CxON(1)
CxINTP
Interrupt
det
CXIN0-
CXIN1-
1
MUX
2 (2)
CXIN2CXIN3-
Set CxIF
det
CXPOL
CxVN
Cx(3)
CxVP
0
MUX
1 (2)
CXIN+
DAC
CxINTN
Interrupt
CXOUT
MCXOUT
To Data Bus
+
EN
Q1
CxHYS
CxSP
FVR Buffer2
CXSYNC
CxON
VSS
CXPCH<1:0>
CXOE
TRIS bit
CXOUT
2
D
(from Timer1)
T1CLK
Note
1:
2:
3:
1
To Timer1
SYNCCXOUT
DS41364B-page 144
Preliminary
PIC16F193X/LF193X
12.2
12.2.3
Comparator Control
Enable
Output selection
Output polarity
Speed/Power selection
Hysteresis enable
Output synchronization
TABLE 12-1:
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
12.2.1
CxPOL
CxOUT
12.2.4
COMPARATOR ENABLE
12.2.2
COMPARATOR OUTPUT
SELECTION
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control
bit. The default state for this bit is 1 which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to 0.
Preliminary
DS41364B-page 145
PIC16F193X/LF193X
12.3
Comparator Hysteresis
TABLE 12-2:
CxSP
HYSTERESIS LEVELS
CxHYS Enabled
CxHYS Disabled
3mV
<< 1mV
20mV
3mV
12.4
12.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
12.5
Comparator Interrupt
12.6
12.7
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
DS41364B-page 146
Preliminary
PIC16F193X/LF193X
12.8
12.9
FIGURE 12-3:
Rs < 10K
RIC
To Comparator
AIN
CPIN
5 pF
VA
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
RS
= Source Impedance
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1:
Preliminary
DS41364B-page 147
PIC16F193X/LF193X
REGISTER 12-1:
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS41364B-page 148
Preliminary
PIC16F193X/LF193X
REGISTER 12-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
CxINTP
CxINTN
CxPCH1
CxPCH0
CxNCH1
CxNCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
Note 1:
Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port
TRIS bit = 0.
REGISTER 12-3:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Preliminary
DS41364B-page 149
PIC16F193X/LF193X
TABLE 12-3:
Name
Register
on Page
C1HYS
C1SYNC
148
C2HYS
C2SYNC
148
C1NCH1
C1NCH0
149
C2NCH1
C2NCH0
149
MC2OUT
MC1OUT
149
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
156
DACPSS1
DACPSS0
DACNSS
153
DACR4
DACR3
DACR2
DACR1
DACR0
153
Bit 7
Bit 6
Bit 5
Bit 4
CM1CON0
C1ON
C1OUT
C1OE
C1POL
---
C1SP
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
CM1CON1
C1NTP
C1INTN
C1PCH1
C1PCH0
CM2CON1
C2NTP
C2INTN
C2PCH1
C2PCH0
CMOUT
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
DACCON0
DACEN
DACLPS
DACOE
DACCON1
INTCON
Bit 3
Bit 2
Bit 1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
93
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
93
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
86
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
91
PORTC
Legend:
DS41364B-page 150
Preliminary
PIC16F193X/LF193X
13.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
13.1
13.5
13.6
Effects of a Reset
EQUATION 13-1:
DACR<4:0>
VOUT = ( VSOURCE+ VSOURCE- ) -------------------------------
25
+ VSOURCEVSOURCE+ = VDD, VREF+ or FVR1
VSOURCE+ = VSS or VREF-
13.2
13.3
13.4
Preliminary
DS41364B-page 151
PIC16F193X/LF193X
FIGURE 13-1:
VDD
DACR<4:0>
VREF+
DACPSS<1:0>
R
2
R
DACEN
R
32
Steps
R
32-to-1 MUX
DAC
(To Comparator and
ADC Modules)
R
R
DACNSS<1:0>
CVREF
DACOE
VREF-
DS41364B-page 152
Preliminary
PIC16F193X/LF193X
REGISTER 13-1:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
DACEN
DACLPS
DACOE
---
DACPSS1
DACPSS0
---
DACNSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-2
bit 1
Unimplemented: Read as 0
bit 0
REGISTER 13-2:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
---
---
---
DACR4
DACR3
DACR2
DACR1
DACR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
Note 1:
The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
Preliminary
DS41364B-page 153
PIC16F193X/LF193X
TABLE 13-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
156
DACCON0
DACEN
DACLPS
DACOE
---
DACPSS1
DACPSS0
---
DACNSS
153
DACCON1
---
---
---
DACR4
DACR3
DACR2
DACR1
DACR0
153
Name
Legend:
DS41364B-page 154
Preliminary
PIC16F193X/LF193X
14.0
14.1
FIGURE 14-1:
14.2
CDAFVR<1:0>
2
X1
X2
X4
FVR_BUFFER1
(To ADC Module)
X1
X2
X4
FVR_BUFFER2
(To Comparators, DAC)
FVR_VREF
(To LCD Bias Generator)
FVREN
FVRRDY
FIGURE 14-2:
+
_
1.024V Fixed
Reference
CVREF
Module
R
Voltage
Reference
Output
Impedance
CVREF
Preliminary
DS41364B-page 155
PIC16F193X/LF193X
REGISTER 14-1:
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
FVREN
FVRRDY(1)
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3-2
CDAFVR<1:0>: Comparator and D/A Converter Fixed Voltage Reference Selection bit
00 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is off.
01 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
bit 1-0
Note 1:
2:
TABLE 14-1:
Name
FVRCON
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1
CDAFVR0
ADFVR1
ADFVR0
156
DS41364B-page 156
Preliminary
PIC16F193X/LF193X
15.0
TIMER0 MODULE
Note:
15.1.2
Timer0 Operation
15.1.1
FIGURE 15-1:
15.1
FOSC/4
Data Bus
0
T0CKI
1
0
Sync
2 TCY
1
0
From CPSCLK
TMR0SE
TMR0CS
8-bit
Prescaler
PSA
TMR0
Set Flag bit TMR0IF
on Overflow
Overflow to Timer1
T0XCS
PS<2:0>
Preliminary
DS41364B-page 157
PIC16F193X/LF193X
15.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
15.1.4
TIMER0 INTERRUPT
15.1.5
15.1.6
DS41364B-page 158
Preliminary
PIC16F193X/LF193X
REGISTER 15-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 15-1:
Name
CPSCON0
INTCON
TRISA
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
CPSON
GIE
PEIE
TMR0IE
INTE
OPTION_REG WPUEN
TMR0
Bit Value
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
T0XCS
180
RBIE
TMR0IF
INTF
RBIF
73
PSA
PS2
PS1
PS0
51
TRISA3
TRISA2
TRISA1
TRISA0
TRISA6
TRISA5
157*
TRISA4
86
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
* Page provides register information.
Preliminary
DS41364B-page 159
PIC16F193X/LF193X
NOTES:
DS41364B-page 160
Preliminary
PIC16F193X/LF193X
16.0
FIGURE 16-1:
T1GSS<1:0>
T1GSPM
00
T1G
From Timer0
Overflow
01
Comparator 1
SYNCC1OUT
10
Comparator 2
SYNCC2OUT
11
T1G_IN
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
CK
R
Q1
Acq. Control
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
T1GTM
TMR1GE
TMR1ON
To Comparator Module
TMR1(2)
EN
Synchronized
clock input
0
TMR1H
TMR1L
T1CLK
1
TMR1CS<1:0>
T1OSO
OUT
T1OSC
T1OSI
Cap. Sensing
Oscillator
T1SYNC
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To LCD and Clock Switching Modules
Preliminary
DS41364B-page 161
PIC16F193X/LF193X
16.1
Timer1 Operation
16.2
16.2.1
16.2.2
Timer1
Operation
TMR1GE
Off
Off
Always On
Count Enabled
TIMER1 ENABLE
SELECTIONS
TMR1ON
TABLE 16-1:
TABLE 16-2:
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
DS41364B-page 162
Preliminary
PIC16F193X/LF193X
16.3
Timer1 Prescaler
16.6
16.6.1
16.4
Timer1 Oscillator
16.5
Timer1 Operation in
Asynchronous Counter Mode
16.5.1
Timer1 Gate
TABLE 16-3:
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
16.6.2
Timer1 Operation
TABLE 16-4:
T1GSS
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
Preliminary
DS41364B-page 163
PIC16F193X/LF193X
16.6.2.1
16.6.4
16.6.2.2
16.6.2.3
16.6.2.4
16.6.3
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 16-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
16.6.5
16.6.6
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
DS41364B-page 164
Preliminary
PIC16F193X/LF193X
16.7
Timer1 Interrupt
16.9
16.8
When any of the CCPs are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1
interrupt. The CCP module may still be configured to
generate a CCP interrupt.
FIGURE 16-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Preliminary
DS41364B-page 165
PIC16F193X/LF193X
FIGURE 16-3:
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
FIGURE 16-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
DS41364B-page 166
N+4
Preliminary
N+8
PIC16F193X/LF193X
FIGURE 16-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
N+1
Set by hardware on
falling edge of T1GVAL
Cleared by software
N+2
Preliminary
Cleared by
software
DS41364B-page 167
PIC16F193X/LF193X
FIGURE 16-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
DS41364B-page 168
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
Preliminary
N+4
Cleared by
software
PIC16F193X/LF193X
16.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 16-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 16-1:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
U-0
R/W-0/u
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
bit 1
Unimplemented: Read as 0
bit 0
Preliminary
DS41364B-page 169
PIC16F193X/LF193X
16.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 16-2, is used to control Timer1 Gate.
REGISTER 16-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R-x/x
R/W-0/u
R/W-0/u
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS41364B-page 170
Preliminary
PIC16F193X/LF193X
TABLE 16-5:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
91
CCP1CON
DC1B1
DC1B0
CCP1M3
184
CCP2CON
DC2B1
DC2B0
CCP2M3
184
73
Name
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
90
PORTB
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
165*
165*
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TMR1ON
169
T1GSS1
T1GSS0
170
T1CON
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
91
Legend: x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Timer1
module.
* Page provides register information.
Preliminary
DS41364B-page 171
PIC16F193X/LF193X
NOTES:
DS41364B-page 172
Preliminary
PIC16F193X/LF193X
17.0
TIMER2/4/6 MODULES
FIGURE 17-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMRx
Sets Flag
bit TMRxIF
Reset
Postscaler
1:1 to 1:16
Comparator
EQ
TxCKPS<1:0>
4
PRx
TxOUTPS<3:0>
Preliminary
DS41364B-page 173
PIC16F193X/LF193X
17.1
Timer2/4/6 Operation
17.3
Timer2/4/6 Output
17.4
17.2
Timer2/4/6 Interrupt
DS41364B-page 174
Preliminary
PIC16F193X/LF193X
REGISTER 17-1:
U-0
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMRxON
TxCKPS1
TxCKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
Preliminary
DS41364B-page 175
PIC16F193X/LF193X
TABLE 17-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
184
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
184
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
76
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
79
INTCON
PR2
173*
TMR2
173*
T2CON
175
Legend: x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
DS41364B-page 176
Preliminary
PIC16F193X/LF193X
18.0
CAPACITIVE SENSING
MODULE
FIGURE 18-1:
TMR0CS
T0XCS
FOSC/4
T0CKI
0
TMR0
Overflow
1
1
CPSCH<3:0>(2)
CPSON(3)
CPS0
CPS1
CPS2
CPS3
Timer1 Module
CPS4
CPSON
T1CS<1:0>
CPS5
CPS6
CPS8(1)
Capacitive
Sensing
Oscillator
CPS9(1)
CPSOSC
CPS7
CPS10(1)
CPS11
(1)
FOSC
FOSC/4
CPSCLK
T1OSC/
T1CKI
CPSOUT
TMR1H:TMR1L
T1GSEL<1:0>
CPSRNG<1:0>
(1)
EN
CPS12
T1G
CPS13(1)
(1)
CPS14
SYNCC1OUT
CPS15(1)
CPS16(1)
Note 1:
2:
3:
Timer1 Gate
Control Logic
SYNCC2OUT
Preliminary
DS41364B-page 177
PIC16F193X/LF193X
18.1
18.4.1
Analog MUX
TIMER0
18.2
18.4.2
TABLE 18-1:
TMR1ON
TMR1GE
Timer1 Operation
Off
Off
On
18.3
TIMER1
Timer resources
18.4
DS41364B-page 178
Preliminary
PIC16F193X/LF193X
18.5
18.5.3
Software Control
18.5.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
18.6
18.5.2
FREQUENCY THRESHOLD
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
Preliminary
DS41364B-page 179
PIC16F193X/LF193X
REGISTER 18-1:
R/W-0/0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
CPSON
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3-2
bit 1
bit 0
DS41364B-page 180
Preliminary
PIC16F193X/LF193X
REGISTER 18-2:
U-0
U-0
U-0
R/W-0/0(1, 2)
R/W-0/0(1)
R/W-0/0
R/W-0/0
R/W-0/0
CPSCH4
CPSCH3
CPSCH2
CPSCH1
CPSCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
2:
TABLE 18-2:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
86
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
91
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
97
INTCON
OPTION_REG
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS2
PS1
PS0
51
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
169
TxCON
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMRXON
TXCKPS1
TXCKPS0
175
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
97
Legend: - = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the capacitive
sensing module.
Preliminary
DS41364B-page 181
PIC16F193X/LF193X
NOTES:
DS41364B-page 182
Preliminary
PIC16F193X/LF193X
19.0
CAPTURE/COMPARE/PWM
MODULES (ECCP1, ECCP2,
ECCP3, CCP4, CCP5)
This
device
contains
three
Enhanced
Capture/Compare/PWM (ECCP1, ECCP2, ECCP3)
and two standard Capture/Compare/PWM module
(CCP4 and CCP5). The CCP4 and CCP5 modules are
identical in operation. The ECCP1, ECCP2 and ECCP3
modules may also be referred to as CCP1, CCP2,
CCP3, as required.
Preliminary
DS41364B-page 183
PIC16F193X/LF193X
19.1
TABLE 19-1:
Capture/Compare/PWM
REQUIRED TIMER
RESOURCES
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2 or 4 or 6
REGISTER 19-1:
R/W-00
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxM1(1)
PxM0(1)
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-0
Note 1:
DS41364B-page 184
Preliminary
PIC16F193X/LF193X
19.2
REGISTER 19-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
C4TSEL1
C4TSEL0
C3TSEL1
C3TSEL0
C2TSEL1
C2TSEL0
C1TSEL1
C1TSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
Preliminary
DS41364B-page 185
PIC16F193X/LF193X
REGISTER 19-3:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
C5TSEL1
C5TSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1-0
DS41364B-page 186
Preliminary
PIC16F193X/LF193X
19.3
19.3.2
Capture Mode
19.3.1
19.3.3
Note:
Note:
FIGURE 19-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
CCPx
pin
CCPRxH
and
Edge Detect
TMR1H
19.3.4
CCP PRESCALER
EXAMPLE 19-1:
CCPRxL
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CLRF
MOVLW
Capture
Enable
CCPxCON<3:0>
System Clock (FOSC)
TMR1L
MOVWF
19.3.5
Preliminary
DS41364B-page 187
PIC16F193X/LF193X
TABLE 19-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCPxCON
PxM1(1)
PxM0(1)
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
CCPRxL
CCPRxH
187
187
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
148
CM1CON1
C1INTP
C1INTN
C1PCH1
C1PCH0
C1NCH1
C1NCH0
149
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2HYS
C2SYNC
148
CM2CON1
C2INTP
C2INTN
C2PCH1
C2PCH0
C2NCH1
C2NCH0
149
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
INTCON
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
79
T1OSCEN
T1SYNC
TMR1ON
169
T1GVAL
T1GSS1
T1GSS0
170
PIR3
T1CON
T1GCON
T1GPOL
T1GTM
T1GSPM T1GGO/DONE
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
165
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
165
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
94
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
TRISE
TRISE3
97
101
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture
and Compare.
Note 1: Applies to ECCP modules only.
DS41364B-page 188
Preliminary
PIC16F193X/LF193X
19.4
19.4.2
Compare Mode
FIGURE 19-2:
19.4.4
CCPxCON<3:0>
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
Q
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
19.4.1
19.4.3
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPx
Pin
19.4.5
Preliminary
DS41364B-page 189
PIC16F193X/LF193X
TABLE 19-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CCPxCON
PxM1(1)
PxM0(1)
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
CCPRxL
CCPRxH
187
187
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
148
CM1CON1
C1INTP
C1INTN
C1PCH1
C1PCH0
C1NCH1
C1NCH0
149
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2HYS
C2SYNC
148
CM2CON1
C2INTP
C2INTN
C2PCH1
C2PCH0
C2NCH1
C2NCH0
149
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
INTCON
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR4IF
79
T1OSCEN
T1SYNC
TMR1ON
169
T1GVAL
T1GSS1
T1GSS0
170
PIR3
T1CON
T1GCON
T1GPOL
T1GTM
T1GSPM T1GGO/DONE
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
165
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
165
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
94
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
TRISE
TRISE3
97
101
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture
and Compare.
Note 1: Applies to ECCP modules only.
2: These bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as 0.
DS41364B-page 190
Preliminary
PIC16F193X/LF193X
19.5
FIGURE 19-3:
PWM Mode
CCPxCON<5:4>
PRx
TxCON
CCPRxL
CCPxCON
CCPRxL
CCPRxH(2) (Slave)
CCPx
Comparator
ECCPxAS
PSTRxCON
PWMxCON
TMRx
(1)
S
TRIS
Comparator
PRx
Note 1:
Clear Timerx,
toggle CCPx pin and
latch duty cycle
2:
FIGURE 19-4:
Period
Pulse Width
TMRx = PRx
TMRx\2 = CCPRxH:CCPxCON<5:4>
TMRX = 0
Preliminary
DS41364B-page 191
PIC16F193X/LF193X
19.5.1
PWM PERIOD
19.5.2
EQUATION 19-1:
PWM PERIOD
TOSC = 1/FOSC
TMRx is cleared
The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
EQUATION 19-2:
PULSE WIDTH
EQUATION 19-3:
( CCPRxL:CCPxCON<5:4> )
Duty Cycle Ratio = ----------------------------------------------------------------------4 ( PRx + 1 )
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMRx register is concatenated with either
the 2-bit internal system clock (FOSC), or 2 bits of the
prescaler, to create the 10-bit time base. The system
clock is used if the Timerx prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 19-3).
DS41364B-page 192
Preliminary
PIC16F193X/LF193X
19.5.3
PWM RESOLUTION
EQUATION 19-4:
TABLE 19-4:
Note:
1.95 kHz
7.81 kHz
31.25 kHz
125 kHz
250 kHz
333.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
Timer Prescale (1, 4, 16)
PRx Value
Maximum Resolution (bits)
TABLE 19-6:
log [ 4 ( PRx + 1 ) ]
Resolution = ------------------------------------------ bits
log ( 2 )
PWM Frequency
TABLE 19-5:
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
PWM Frequency
Timer Prescale (1, 4, 16)
PRx Value
Maximum Resolution (bits)
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
Preliminary
DS41364B-page 193
PIC16F193X/LF193X
19.5.4
19.5.7
19.5.5
4.
5.
19.5.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
6.
Note:
DS41364B-page 194
Preliminary
PIC16F193X/LF193X
19.6
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Single PWM
Half-Bridge PWM
Full-Bridge PWM, Forward mode
Full-Bridge PWM, Reverse mode
FIGURE 19-5:
DCxB<1:0>
CCPxM<3:0>
4
PxM<1:0>
2
CCPRxL
CCPx/P1A
CCPx/P1A
TRISx
CCPRxH (Slave)
P1B
R
Comparator
Output
Controller
P1B
TRISx
P1C
TMRx
(1)
S
P1D
Comparator
Clear Timerx,
toggle PWM pin and
latch duty cycle
PRx
Note
1:
P1C
TRISx
P1D
TRISx
PWMxCON
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 19-7:
ECCP Mode
PxM<1:0>
CCPx/P1A
Single
00
Yes(1)
Half-Bridge
10
Yes
Yes
No
No
Full-Bridge, Forward
01
Yes
Yes
Yes
Yes
Full-Bridge, Reverse
11
Yes
Yes
Yes
Yes
Note 1:
P1B
Yes
(1)
P1C
Yes
(1)
P1D
Yes(1)
Preliminary
DS41364B-page 195
PIC16F193X/LF193X
FIGURE 19-6:
PxM<1:0>
Signal
PRX+1
Pulse
Width
Period
00
(Single Output)
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 Programmable Dead-Band Delay
Mode).
DS41364B-page 196
Preliminary
PIC16F193X/LF193X
FIGURE 19-7:
PxM<1:0>
PRx+1
Pulse
Width
Period
00
(Single Output)
P1A Modulated
P1A Modulated
Delay(1)
10
(Half-Bridge)
Delay(1)
P1B Modulated
P1A Active
01
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
11
(Full-Bridge,
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note
1:
Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 Programmable Dead-Band Delay
Mode).
Preliminary
DS41364B-page 197
PIC16F193X/LF193X
19.6.1
HALF-BRIDGE MODE
FIGURE 19-8:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 19-9:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
P1A
Load
FET
Driver
P1B
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
DS41364B-page 198
Preliminary
PIC16F193X/LF193X
19.6.2
FULL-BRIDGE MODE
FIGURE 19-10:
FET
Driver
QC
QA
FET
Driver
P1A
Load
P1B
FET
Driver
P1C
FET
Driver
QD
QB
VP1D
Preliminary
DS41364B-page 199
PIC16F193X/LF193X
FIGURE 19-11:
Forward Mode
Period
P1A
(2)
Pulse Width
P1B(2)
P1C(2)
P1D(2)
(1)
(1)
Reverse Mode
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
(1)
Note 1:
2:
(1)
DS41364B-page 200
Preliminary
PIC16F193X/LF193X
19.6.2.1
FIGURE 19-12:
Signal
Period
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
(2)
P1D (Active-High)
Pulse Width
Note 1:
2:
The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is four Timerx counts.
Preliminary
DS41364B-page 201
PIC16F193X/LF193X
FIGURE 19-13:
t1
Reverse Period
P1A
P1B
PW
P1C
P1D
PW
TON
External Switch C
TOFF
External Switch D
Potential
Shoot-Through Current
Note 1:
T = TOFF TON
2:
3:
TOFF is the turn off delay of power switch QD and its driver.
DS41364B-page 202
Preliminary
PIC16F193X/LF193X
19.6.3
START-UP CONSIDERATIONS
19.6.4
ENHANCED PWM
AUTO-SHUTDOWN MODE
Preliminary
DS41364B-page 203
PIC16F193X/LF193X
REGISTER 19-4:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCPxASE
CCPxAS2
CCPxAS1
CCPxAS0
PSSxAC1
PSSxAC0
PSSxBD1
PSSxBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
bit 1-0
Note 1:
DS41364B-page 204
Preliminary
PIC16F193X/LF193X
FIGURE 19-14:
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
Shutdown
Event Occurs
19.6.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the PWMxCON register.
FIGURE 19-15:
Shutdown
Event Clears
PWM
Resumes
CCPxASE
Cleared by
Firmware
Timer
Overflow
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
Preliminary
CCPxASE
Cleared by
Hardware
DS41364B-page 205
PIC16F193X/LF193X
19.6.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 19-16:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
FIGURE 19-17:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
2:
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS41364B-page 206
Preliminary
PIC16F193X/LF193X
REGISTER 19-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PxRSEN
PxDC6
PxDC5
PxDC4
PxDC3
PxDC2
PxDC1
PxDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
Note 1:
Bit resets to 0 with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Preliminary
DS41364B-page 207
PIC16F193X/LF193X
19.6.7
Note:
REGISTER 19-6:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
STRxSYNC
STRxD
STRxC
STRxB
STRxA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11 and
PxM<1:0> = 00.
DS41364B-page 208
Preliminary
PIC16F193X/LF193X
FIGURE 19-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRxA
P1A Signal
CCPxM1
PORT Data
P1A pin
STRxB
CCPxM0
PORT Data
CCPxM1
PORT Data
P1C pin
TRIS
STRxD
PORT Data
P1B pin
TRIS
STRxC
CCPxM0
TRIS
P1D pin
1
0
TRIS
Note 1:
2:
Preliminary
DS41364B-page 209
PIC16F193X/LF193X
19.6.7.1
Steering Synchronization
FIGURE 19-19:
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 19-20:
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS41364B-page 210
Preliminary
PIC16F193X/LF193X
TABLE 19-8:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PxM1(1)
PxM0(1)
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
CCPxAS
CCPxASE
CCPxAS2
CCPxAS1
CCPxAS0
PSSxAC1
PSSxAC0
PSSxBD1
PSSxBD0
204
CCPTMRS0
C4TSEL1
C4TSEL0
C3TSEL1
C3TSEL0
C2TSEL1
C2TSEL0
C1TSEL1
C1TSEL0
185
CCPTMRS1
C5TSEL1
C5TSEL0
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
STRxSYNC
STRxD
STRxC
STRxB
STRxA
208
PxDC6
PxDC5
PxDC4
PxDC3
Name
CCPxCON
INTCON
PRx
PSTRxCON
PWMxCON
PxRSEN
TxCON
TMRx
173*
PxDC2
PxDC1
PxDC0
207
TMRxON
TxCKPS1
TxCKPS0
175
173
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
91
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
97
Legend: = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
Note 1: Applies to ECCP modules only.
* Page provides register information.
Preliminary
DS41364B-page 211
PIC16F193X/LF193X
NOTES:
DS41364B-page 212
Preliminary
PIC16F193X/LF193X
20.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 20-1:
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
TXEN
Baud Rate Generator
FOSC
TX9
BRG16
+1
SPBRGH
SPBRG
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
Preliminary
DS41364B-page 213
PIC16F193X/LF193X
FIGURE 20-2:
CREN
RX/DT pin
Data
Recovery
FOSC
SPBRGH
SPBRG
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
(8)
LSb
0 START
RX9
BRG16
Multiplier
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
FERR
RX9D
RCREG Register
FIFO
8
Data Bus
RCIF
RCIE
Interrupt
DS41364B-page 214
Preliminary
PIC16F193X/LF193X
20.1
20.1.1.2
20.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
20.1.1.1
Transmitting Data
20.1.1.3
TXEN = 1
SYNC = 0
SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output.
Preliminary
DS41364B-page 215
PIC16F193X/LF193X
20.1.1.4
TSR Status
20.1.1.6
20.1.1.5
1.
2.
3.
5.
6.
7.
FIGURE 20-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
Start bit
FIGURE 20-4:
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
bit 0
1 TCY
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
DS41364B-page 216
Preliminary
PIC16F193X/LF193X
TABLE 20-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
224
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
77
Name
BAUDCON
INTCON
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
225*
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
225*
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
SYNC
SENDB
BRGH
TRMT
TX9D
TRISC
TXREG
TXSTA
TX9
TXEN
215*
222
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for Asynchronous Transmission.
* Page provides register information.
Preliminary
DS41364B-page 217
PIC16F193X/LF193X
20.1.2
EUSART ASYNCHRONOUS
RECEIVER
20.1.2.2
20.1.2.1
Receiving Data
20.1.2.3
Receive Interrupts
DS41364B-page 218
Preliminary
PIC16F193X/LF193X
20.1.2.4
20.1.2.7
20.1.2.5
Address Detection
20.1.2.6
Preliminary
DS41364B-page 219
PIC16F193X/LF193X
20.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
20.1.2.9
FIGURE 20-5:
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
bit 0
Word 1
RCREG
Start
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41364B-page 220
Preliminary
PIC16F193X/LF193X
TABLE 20-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
224
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
RCREG
Name
BAUDCON
INTCON
PIE1
218*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
225*
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
225*
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
222
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for Asynchronous Reception.
* Page provides register information.
Preliminary
DS41364B-page 221
PIC16F193X/LF193X
20.2
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
REGISTER 20-1:
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41364B-page 222
Preliminary
PIC16F193X/LF193X
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
REGISTER 20-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-x/x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41364B-page 223
PIC16F193X/LF193X
REGISTER 20-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS41364B-page 224
Preliminary
PIC16F193X/LF193X
20.3
EXAMPLE 20-1:
CALCULATING BAUD
RATE ERROR
16000000
-----------------------9600
= ------------------------ 1
64
= [ 25.042 ] = 25
16000000
Calculated Baud Rate = --------------------------64 ( 25 + 1 )
= 9615
Calc. Baud Rate Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
( 9615 9600 )
= ---------------------------------- = 0.16%
9600
Preliminary
DS41364B-page 225
PIC16F193X/LF193X
TABLE 20-3:
Configuration Bits
BRG/EUSART Mode
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
FOSC/[16 (n+1)]
1
Legend:
FOSC/[4 (n+1)]
TABLE 20-4:
Name
BAUDCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
224
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
225*
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
225*
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
222
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS41364B-page 226
Preliminary
PIC16F193X/LF193X
TABLE 20-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
57.6k
55.55k
-3.55
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
Preliminary
DS41364B-page 227
PIC16F193X/LF193X
TABLE 20-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
-0.01
4166
300.0
0.00
3839
300.0
0.00
2303
1200
1200
-0.02
3332
1200
-0.03
1041
1200
0.00
959
1200
0.00
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
71
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
115.2k
0.00
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS41364B-page 228
Preliminary
PIC16F193X/LF193X
TABLE 20-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
832
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
Preliminary
DS41364B-page 229
PIC16F193X/LF193X
20.3.1
AUTO-BAUD DETECT
FIGURE 20-6:
TABLE 20-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
1
Note:
BRG Value
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRG
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS41364B-page 230
Preliminary
PIC16F193X/LF193X
20.3.2
AUTO-BAUD OVERFLOW
20.3.3.1
20.3.3
AUTO-WAKE-UP ON BREAK
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
Preliminary
DS41364B-page 231
PIC16F193X/LF193X
FIGURE 20-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
Note 1:
FIGURE 20-8:
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS41364B-page 232
Preliminary
PIC16F193X/LF193X
20.3.4
5.
20.3.5
20.3.4.1
FIGURE 20-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
Preliminary
DS41364B-page 233
PIC16F193X/LF193X
20.4
20.4.1
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
20.4.1.3
20.4.1.4
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
20.4.1.1
20.4.1.2
2.
3.
4.
5.
6.
Master Clock
7.
8.
Clock Polarity
DS41364B-page 234
Preliminary
PIC16F193X/LF193X
FIGURE 20-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 20-11:
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 20-7:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
224
IOCIE
TMR0IF
INTF
IOCIF
73
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
225*
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
225*
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISC
TXREG
TXSTA
Legend:
*
TX9
TXEN
94
215*
SYNC
SENDB
BRGH
TRMT
TX9D
222
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Master Transmission.
Page provides register information.
Preliminary
DS41364B-page 235
PIC16F193X/LF193X
20.4.1.5
20.4.1.6
Slave Clock
20.4.1.7
20.4.1.8
20.4.1.9
1.
DS41364B-page 236
Preliminary
PIC16F193X/LF193X
FIGURE 20-12:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 20-8:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
224
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
RCREG
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
225*
SPBRGH
BRG15
BRG14
BRG13
BRG12
BRG11
BRG10
BRG9
BRG8
225*
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
222
Name
BAUDCON
INTCON
218*
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Master
Reception.
* Page provides register information.
Preliminary
DS41364B-page 237
PIC16F193X/LF193X
20.4.2
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
20.4.2.1
5.
20.4.2.2
1.
2.
3.
4.
5.
6.
7.
TABLE 20-9:
Name
BAUDCON
Bit 6
ABDOVF
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
224
IOCIE
TMR0IF
INTF
IOCIF
73
74
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
INTE
GIE
PEIE
TMR0IE
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
INTCON
TXREG
TXSTA
TX9
TXEN
215*
SYNC
SENDB
BRGH
TRMT
TX9D
222
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Slave
Transmission.
* Page provides register information.
DS41364B-page 238
Preliminary
PIC16F193X/LF193X
20.4.2.3
20.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 7
Bit 6
ABDOVF
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
224
IOCIE
TMR0IF
INTF
IOCIF
73
74
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
INTE
GIE
PEIE
TMR0IE
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCREG
INTCON
77
218*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
223
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
222
Legend: x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Slave
Reception.
* Page provides register information.
Preliminary
DS41364B-page 239
PIC16F193X/LF193X
20.5
20.5.1
20.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
DS41364B-page 240
Preliminary
PIC16F193X/LF193X
21.0
FIGURE 21-1:
21.1
LCD Registers
Data Bus
SEG<23:0>(1, 3)
LCDDATAx
To I/O Pads(1)
MUX
Registers
Timing Control
LCDCON
COM<3:0>(3)
LCDPS
To I/O Pads(1)
LCDSEn
FOSC/256
T1OSC
LFINTOSC
Note 1:
2:
3:
Clock Source
Select and
Prescaler
These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
SEG<23:0> on PIC16F1934/1937/1939, SEG<15:0> on PIC16F1933/1936/1938/
PIC16LF1933/1936/1938.
COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938,
therefore SEG15 is not available when using 1/4 multiplex displays.
Preliminary
DS41364B-page 241
PIC16F193X/LF193X
TABLE 21-1:
Device
Segment
Enable
Data
PIC16F1933/1936/1938/
PIC16LF1933/1936/1938
PIC16F1934/1937/1939/
PIC16LF1934/1937/1939
12
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
SEG<7:0>COM0
SEG<15:8>COM0
SEG<23:16>COM0(1)
SEG<7:0>COM1
SEG<15:8>COM1
SEG<23:16>COM1(1)
SEG<7:0>COM2
SEG<15:8>COM2
SEG<23:16>COM2(1)
SEG<7:0>COM3
SEG<15:8>COM3
SEG<23:16>COM3(1)
Note 1: PIC16F1934/1937/1939/
PIC16LF1934/1937/1939 only.
As an example,
Register 21-6.
LCDDATAx
is
detailed
in
DS41364B-page 242
Preliminary
PIC16F193X/LF193X
REGISTER 21-1:
R/W-0/0
R/W-0/0
R/C-0/0
U-0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-2
bit 1-0
Multiplex
PIC16F1933/1936/1938/
PIC16LF1933/1936/1938
PIC16F1934/1937/1939/
PIC16LF1934/1937/1939
Bias
00
Static (COM0)
16
24
Static
01
1/2 (COM<1:0>)
32
48
1/2 or 1/3
10
1/3 (COM<2:0>)
48
72
1/2 or 1/3
96
1/3
11
Note 1:
1/4 (COM<3:0>)
60
(1)
On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.
Preliminary
DS41364B-page 243
PIC16F193X/LF193X
REGISTER 21-2:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-1/1
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
DS41364B-page 244
Preliminary
PIC16F193X/LF193X
REGISTER 21-3:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
LCDIRE
LCDIRS
LCDIRI
VLCD3PE
VLCD2PE
VLCD1PE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as 0
Note 1:
Preliminary
DS41364B-page 245
PIC16F193X/LF193X
REGISTER 21-4:
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
LCDCST2
LCDCST1
LCDCST0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
DS41364B-page 246
Preliminary
PIC16F193X/LF193X
REGISTER 21-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SEn
SEn
SEn
SEn
SEn
SEn
SEn
SEn
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 21-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Preliminary
DS41364B-page 247
PIC16F193X/LF193X
21.2
21.2.1
FOSC/256
T1OSC
LFINTOSC
LCD PRESCALER
FOSC
To Reference
Ladder Control
256
T1OSC 32 kHz
Crystal Osc.
Static
1/2
5
4-bit Prog
Prescaler
32
1, 2, 3, 4
Ring Counter
1/3,
1/4
LFINTOSC
Nominal = 31 kHz
LP<3:0>
(LCDPS<3:0>)
CS<1:0>
(LCDCON<3:2>)
DS41364B-page 248
COM0
COM1
COM2
COM3
FIGURE 21-2:
LMUX<1:0>
(LCDCON<1:0>)
LMUX<1:0>
(LCDCON<1:0>)
Preliminary
PIC16F193X/LF193X
21.3
TABLE 21-2:
FIGURE 21-3:
1/2 Bias
1/3 Bias
LCD Bias 0
VSS
VSS
VSS
LCD Bias 1
1/2 VDD
1/3 VDD
LCD Bias 2
1/2 VDD
2/3 VDD
LCD Bias 3
VLCD3
VLCD3
VLCD3
So that the user is not forced to place external components and use up to three pins for bias voltage generation,
internal contrast control and an internal reference ladder
are provided internally to the PIC16F193X/LF193X. Both
of these features may be used in conjunction with the
external VLCD<3:1> pins, to provide maximum flexibility.
Refer to Figure 21-3.
VDD
1.024V from
FVR
3.072V
x3
LCDRLP1
LCDRLP0
LCDIRE
LCDIRS
LCDA
LCDCST<2:0>
VLCD3PE
LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0
Preliminary
DS41364B-page 249
PIC16F193X/LF193X
21.4
21.4.2
POWER MODES
TABLE 21-3:
21.4.1
Power
Mode
Nominal
IDD
3 Mohm
300 kohm
30 kohm
1 A
10 A
100 A
Low
Medium
High
DS41364B-page 250
Preliminary
PIC16F193X/LF193X
21.4.3
As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage
is switching. To minimize total device current, the LCD
internal reference ladder can be operated in a different
power mode for the transition portion of the duration.
This is controlled by the LCDRL Register
(Register 21-7).
FIGURE 21-4:
32kHz_clk
cnt[4:0]
H00
H01
H02
H03
H04
H05
H06
H07
H0E
H0F
H00
H01
lcd_clk
H3
LRLAT[2:0]
Segment Data
LRLAT<2:0>
Power Mode
FIGURE 21-5:
Power Mode A
Power Mode B
Mode A
32kHz_clk
cnt[4:0]
H00
H01
H02
H03
H04
H05
H06
H07
H1E
H1F
H00
H01
lcd_clk
H3
LRLAT[2:0]
Segment Data
LRLAT<2:0>
Power Mode
Power Mode A
Power Mode B
Preliminary
Mode A
DS41364B-page 251
PIC16F193X/LF193X
REGISTER 21-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
LRLAP1
LRLAP0
LRLBP1
LRLBP0
LRLAT2
LRLAT1
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
DS41364B-page 252
Preliminary
PIC16F193X/LF193X
21.4.4
CONTRAST CONTROL
FIGURE 21-6:
VDDIO
7 Stages
R
3.072V
Analog
MUX
From FVR
Buffer
7
To top of
Reference Ladder
0
LCDCST<2:0>
3
Internal Reference
21.4.5
Contrast control
21.4.6
INTERNAL REFERENCE
VLCD<3:1> PINS
.
Note:
Preliminary
DS41364B-page 253
PIC16F193X/LF193X
21.5
TABLE 21-5:
TABLE 21-4:
LMUX
Multiplex
<1:0>
COM3
COM2
Multiplex
Frame Frequency =
Static
1/2
1/3
1/4
FRAME FREQUENCY
FORMULAS
Note:
TABLE 21-6:
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR LFINTOSC
LP<3:0>
Static
1/2
1/3
1/4
COM1
85
85
114
85
64
64
85
64
Static
00
Unused
Unused
Unused
1/2
01
Unused
Unused
Active
51
51
68
51
43
43
57
43
1/3
10
Unused
Active
Active
1/4
11
Active
Active
Active
37
37
49
37
32
32
43
32
21.6
Segment Enables
21.7
Pixel Control
21.8
DS41364B-page 254
Preliminary
PIC16F193X/LF193X
TABLE 21-7:
LCD
Function
COM1
LCD
Segment
LCDDATAx
Address
COM2
LCD
Segment
LCDDATAx
Address
COM3
LCD
Segment
LCDDATAx
Address
SEG0
LCDDATA0, 0
LCDDATA3, 0
LCDDATA6, 0
LCDDATA9, 0
SEG1
LCDDATA0, 1
LCDDATA3, 1
LCDDATA6, 1
LCDDATA9, 1
SEG2
LCDDATA0, 2
LCDDATA3, 2
LCDDATA6, 2
LCDDATA9, 2
SEG3
LCDDATA0, 3
LCDDATA3, 3
LCDDATA6, 3
LCDDATA9, 3
SEG4
LCDDATA0, 4
LCDDATA3, 4
LCDDATA6, 4
LCDDATA9, 4
SEG5
LCDDATA0, 5
LCDDATA3, 5
LCDDATA6, 5
LCDDATA9, 5
SEG6
LCDDATA0, 6
LCDDATA3, 6
LCDDATA6, 6
LCDDATA9, 6
SEG7
LCDDATA0, 7
LCDDATA3, 7
LCDDATA6, 7
LCDDATA9, 7
SEG8
LCDDATA1, 0
LCDDATA4, 0
LCDDATA7, 0
LCDDATA10, 0
SEG9
LCDDATA1, 1
LCDDATA4, 1
LCDDATA7, 1
LCDDATA10, 1
SEG10
LCDDATA1, 2
LCDDATA4, 2
LCDDATA7, 2
LCDDATA10, 2
SEG11
LCDDATA1, 3
LCDDATA4, 3
LCDDATA7, 3
LCDDATA10, 3
SEG12
LCDDATA1, 4
LCDDATA4, 4
LCDDATA7, 4
LCDDATA10, 4
SEG13
LCDDATA1, 5
LCDDATA4, 5
LCDDATA7, 5
LCDDATA10, 5
SEG14
LCDDATA1, 6
LCDDATA4, 6
LCDDATA7, 6
LCDDATA10, 6
SEG15
LCDDATA1, 7
LCDDATA4, 7
LCDDATA7, 7
LCDDATA10, 7
SEG16
LCDDATA2, 0
LCDDATA5, 0
LCDDATA8, 0
LCDDATA11, 0
SEG17
LCDDATA2, 1
LCDDATA5, 1
LCDDATA8, 1
LCDDATA11, 1
SEG18
LCDDATA2, 2
LCDDATA5, 2
LCDDATA8, 2
LCDDATA11, 2
SEG19
LCDDATA2, 3
LCDDATA5, 3
LCDDATA8, 3
LCDDATA11, 3
SEG20
LCDDATA2, 4
LCDDATA5, 4
LCDDATA8, 4
LCDDATA11, 4
SEG21
LCDDATA2, 5
LCDDATA5, 5
LCDDATA8, 5
LCDDATA11, 5
SEG22
LCDDATA2, 6
LCDDATA5, 6
LCDDATA8, 6
LCDDATA11, 6
SEG23
LCDDATA2, 7
LCDDATA5, 7
LCDDATA8, 7
LCDDATA11, 7
Preliminary
LCD
Segment
DS41364B-page 255
PIC16F193X/LF193X
21.9
FIGURE 21-7:
V1
COM0
V0
COM0
V1
SEG0
V0
V1
SEG1
V0
V1
V0
COM0-SEG0
-V1
COM0-SEG1
V0
DS41364B-page 256
SEG1
SEG0
SEG2
SEG7
SEG6
SEG5
SEG4
SEG3
1 Frame
Preliminary
PIC16F193X/LF193X
FIGURE 21-8:
V1
V0
COM1
V2
COM1
COM0
V1
V0
V2
V1
SEG0
V0
V2
V1
SEG1
V2
SEG1
SEG0
SEG2
SEG3
V0
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
1 Frame
Preliminary
DS41364B-page 257
PIC16F193X/LF193X
FIGURE 21-9:
V2
V1
COM0
COM1
V0
COM0
V2
COM1
V1
V0
V2
SEG0
V1
SEG1
SEG0
SEG2
SEG3
V0
V2
SEG1
V1
V0
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
2 Frames
DS41364B-page 258
Preliminary
PIC16F193X/LF193X
FIGURE 21-10:
COM0
V1
COM1
V0
V3
COM0
V2
COM1
V1
V0
V3
V2
SEG0
V1
V0
SEG1
SEG0
SEG2
SEG3
V3
V2
SEG1
V1
V0
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
1 Frame
Preliminary
-V3
DS41364B-page 259
PIC16F193X/LF193X
FIGURE 21-11:
COM0
V1
COM1
V0
V3
COM0
V2
COM1
V1
V0
V3
V2
SEG0
V1
V0
SEG1
SEG0
SEG2
SEG3
V3
V2
SEG1
V1
V0
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
2 Frames
DS41364B-page 260
Preliminary
-V3
PIC16F193X/LF193X
FIGURE 21-12:
V1
V0
V2
COM2
COM1
V1
V0
COM1
V2
COM0
COM2
V1
V0
V2
SEG0
SEG2
V1
V0
V2
V1
SEG0
SEG1
SEG2
SEG1
V0
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
1 Frame
Preliminary
DS41364B-page 261
PIC16F193X/LF193X
FIGURE 21-13:
V2
COM0
V1
V0
COM2
V2
COM1
V1
COM1
V0
COM0
V2
COM2
V1
V0
V2
V1
V0
SEG0
SEG1
SEG2
SEG0
V2
SEG1
V1
V0
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
2 Frames
DS41364B-page 262
Preliminary
PIC16F193X/LF193X
FIGURE 21-14:
COM0
V1
V0
V3
COM2
V2
COM1
V1
COM1
V0
COM0
V3
V2
COM2
V1
V0
V3
V2
V1
V0
SEG0
SEG1
SEG2
SEG0
SEG2
V3
V2
SEG1
V1
V0
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
-V3
1 Frame
Preliminary
DS41364B-page 263
PIC16F193X/LF193X
FIGURE 21-15:
COM0
V1
V0
V3
COM2
V2
COM1
V1
COM1
V0
COM0
V3
V2
COM2
V1
V0
V3
V2
V1
V0
SEG0
SEG1
SEG2
SEG0
V3
V2
SEG1
V1
V0
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
-V3
2 Frames
DS41364B-page 264
Preliminary
PIC16F193X/LF193X
FIGURE 21-16:
COM3
COM2
COM1
COM0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
COM3
V3
V2
V1
V0
SEG0
V3
V2
V1
V0
SEG1
V3
V2
V1
V0
COM0-SEG0
V3
V2
V1
V0
-V1
-V2
-V3
COM0-SEG1
V3
V2
V1
V0
-V1
-V2
-V3
SEG0
SEG1
COM0
1 Frame
Preliminary
DS41364B-page 265
PIC16F193X/LF193X
FIGURE 21-17:
COM3
COM2
COM1
COM0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
COM3
V3
V2
V1
V0
SEG0
V3
V2
V1
V0
SEG1
V3
V2
V1
V0
COM0-SEG0
V3
V2
V1
V0
-V1
-V2
-V3
COM0-SEG1
V3
V2
V1
V0
-V1
-V2
-V3
SEG0
SEG1
COM0
2 Frames
DS41364B-page 266
Preliminary
PIC16F193X/LF193X
21.10 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD
frame timing.
21.10.1
An LCD interrupt is generated when the module completes shutting down (LCDA goes from 1 to 0).
21.10.2
Preliminary
DS41364B-page 267
PIC16F193X/LF193X
FIGURE 21-18:
Controller Accesses
Next Frame Data
COM0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
V3
V2
V1
V0
COM3
2 Frames
TFINT
Frame
Boundary
Frame
Boundary
TFWR
Frame
Boundary
DS41364B-page 268
Preliminary
PIC16F193X/LF193X
21.11 Operation During Sleep
The LCD module can operate during Sleep. The
selection is controlled by bit SLPEN of the LCDCON
register. Setting the SLPEN bit allows the LCD module
to go to Sleep. Clearing the SLPEN bit allows the
module to continue to operate during Sleep.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current Consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 21-19 shows this operation.
The LCD module can be configured to operate during
Sleep. The selection is controlled by bit SLPEN of the
LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and
correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will immediately cease all functions, drive
the outputs to Vss and go into a very low-current mode.
The SLEEP instruction should only be executed after
the LCD module has been disabled and the current
cycle completed, thus ensuring that there are no DC
voltages on the glass. To disable the LCD module,
clear the LCDEN bit. The LCD module will complete the
disabling process after the current frame, clear the
LCDA bit and optionally cause an interrupt.
The steps required to properly enter Sleep with the
LCD disabled are:
Clear LCDEN
Wait for LCDA = 0 either by polling or by interrupt
Execute SLEEP
If SLPEN = 0 and SLEEP is executed while the LCD
module clock source is FOSC/4, then the LCD module
will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent
LCD glass damage, either perform the proper LCD
module shutdown prior to Sleep, or change the LCD
module clock to allow the LCD module to continue
operation during Sleep.
If a SLEEP instruction is executed and SLPEN = 0 and
the LCD module clock is either T1OSC or LFINTOSC,
the module will continue to display the current contents
of the LCDDATA registers. While in Sleep, the LCD
data cannot be changed. If the LCDIE bit is set, the
device will wake from Sleep on the next LCD frame
boundary. The LCD module current consumption will
not decrease in this mode; however, the overall device
power consumption will be lower due to the shutdown
of the CPU and other peripherals.
TABLE 21-8:
Clock Source
T1OSC
LFINTOSC
FOSC/4
Note:
Operational
During Sleep
Yes
No
Yes
No
No
No
If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE = 1,
the device will awaken from Sleep on the next frame
boundary.
Preliminary
DS41364B-page 269
PIC16F193X/LF193X
FIGURE 21-19:
COM0
V0
V3
V2
V1
V0
COM1
V3
V2
V1
V0
COM2
V3
V2
V1
V0
SEG0
2 Frames
SLEEP Instruction Execution
DS41364B-page 270
Preliminary
Wake-up
PIC16F193X/LF193X
21.12 Configuring the LCD Module
1.
Oscillator Selection
LCD Bias Source
Capacitance of the LCD segments
2.
3.
4.
5.
6.
7.
21.14.1
OSCILLATOR SELECTION
21.14.2
The LCD bias source, internal or external, can contribute significantly to the current consumption. Use the
highest possible resistor values while maintaining
contrast to minimize current.
21.14.3
The LCD segments which can be modeled as capacitors which must be both charged and discharged every
frame. The size of the LCD segment and its technology
determines the segments capacitance.
Preliminary
DS41364B-page 271
PIC16F193X/LF193X
TABLE 21-9:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
LCDCON
LCDEN
SLPEN
WERR
CS1
CS0
LMUX1
LMUX0
243
LCDCST
LCDCST2
LCDCST1
LCDCST0
246
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
247
LCDDATA1
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
247
LCDDATA2
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
247
LCDDATA3
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
247
LCDDATA4
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
247
LCDDATA5
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
247
LCDDATA6
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
247
LCDDATA7
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
247
LCDDATA8
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
247
LCDDATA9
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
247
LCDDATA10
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
247
LCDDATA11
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
247
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0
244
LCDPS
LCDREF
LCDIRE
LCDIRS
LCDIRI
VLCD3PE
VLCD2PE
VLCD1PE
245
LCDRL
LRLAP1
LRLAP0
LRLBP1
LRLBP0
LRLAT2
LRLAT1
LRLAT0
252
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0
247
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
247
LCDSE2
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16
247
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
T1SYNC
TMR1ON
169
PIR2
T1CON
Legend:
T1CKPS0 T1OSCEN
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by the LCD module.
DS41364B-page 272
Preliminary
PIC16F193X/LF193X
22.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
22.1
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy chain connection of Slave devices
FIGURE 22-1:
Write
SSPBUF Reg
SDI
SSPSR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
SCK
Edge
Select
TRIS bit
Preliminary
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud rate
generator
(SSPADD)
DS41364B-page 273
PIC16F193X/LF193X
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
Figure 22-2 is a block diagram of the I2C interface module in Master mode. Figure 22-3 is a diagram of the I2C
interface module in Slave mode.
Internal
data bus
Read
[SSPM 3:0]
Write
SSPBUF
Baud rate
generator
(SSPADD)
SDA in
SCL
SCL in
Bus Collision
DS41364B-page 274
LSb
Preliminary
Clock Cntl
SSPSR
MSb
Shift
Clock
SDA
FIGURE 22-2:
PIC16F193X/LF193X
FIGURE 22-3:
Write
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
22.2
Set, Reset
S, P bits
(SSPSTAT Reg)
Preliminary
DS41364B-page 275
PIC16F193X/LF193X
REGISTER 22-1:
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
DS41364B-page 276
Preliminary
PIC16F193X/LF193X
REGISTER 22-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
1:
2:
3:
4:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSPADD values of 0, 1 or 2 are not supported for I2C Mode.
Preliminary
DS41364B-page 277
PIC16F193X/LF193X
REGISTER 22-3:
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
bit 5
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41364B-page 278
Preliminary
PIC16F193X/LF193X
REGISTER 22-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
bit 0
Note 1:
2:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
Preliminary
DS41364B-page 279
PIC16F193X/LF193X
REGISTER 22-5:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
bit 0
REGISTER 22-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
Not used: Unused for Most Significant Address byte. Bit state of this register is a dont care. Bit pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
bit 0
DS41364B-page 280
Preliminary
PIC16F193X/LF193X
22.3
SPI Mode
22.3.2
REGISTERS
OPERATIONS
Preliminary
DS41364B-page 281
PIC16F193X/LF193X
22.3.3
22.3.4
TYPICAL CONNECTION
FIGURE 22-4:
SDI
SDI
Shift Register
(SSPSR)
MSb
LSb
General I/O
DS41364B-page 282
Shift Register
(SSPSR)
MSb
SCK
Processor 1
SDO
Serial Clock
Slave Select
(optional)
Preliminary
LSb
SCK
SS
Processor 2
PIC16F193X/LF193X
22.3.5
MASTER MODE
FIGURE 22-5:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
Preliminary
DS41364B-page 283
PIC16F193X/LF193X
22.3.6
SLAVE MODE
22.3.7
FIGURE 22-6:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS41364B-page 284
Preliminary
PIC16F193X/LF193X
FIGURE 22-7:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 22-8:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
Preliminary
DS41364B-page 285
PIC16F193X/LF193X
22.3.8
OPERATION IN POWER-MANAGED
MODES
TABLE 22-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
CCP3SEL
T1GSEL
P2BSEL
SRNQSEL
C2OUTSEL
SSSEL
CCP2SEL
84
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIR1
TMR1GIf
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
SSPBUF
281*
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPCON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
279
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
276
277
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
94
Legend:
*
DS41364B-page 286
Preliminary
PIC16F193X/LF193X
22.4
I2C MODE
TABLE 22-2:
BYTE FORMAT
TERM
Transmitter
Preliminary
DS41364B-page 287
PIC16F193X/LF193X
22.4.4
22.4.6
START CONDITION
STOP CONDITION
FIGURE 22-9:
RESTART CONDITION
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
DS41364B-page 288
Stop
Condition
Preliminary
PIC16F193X/LF193X
FIGURE 22-10:
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
Preliminary
DS41364B-page 289
PIC16F193X/LF193X
22.4.8
22.5
ACKNOWLEDGE SEQUENCE
DS41364B-page 290
Preliminary
PIC16F193X/LF193X
22.5.2
22.5.2.2
SLAVE RECEPTION
Preliminary
DS41364B-page 291
DS41364B-page 292
Preliminary
SSPOV
BF
SSPIF
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D4
D3
D2
D1
SSPBUF is read
Cleared by software
D5
Receiving Data
D6
First byte
of data is
available
in SSPBUF
D0 ACK D7
D4
D3
D2
D1
Cleared by software
D5
Receiving Data
D0
ACK = 1
FIGURE 22-11:
SCL
SDA
Receiving Address
PIC16F193X/LF193X
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Preliminary
CKP
SSPOV
BF
SSPIF
SCL
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
SSPBUF is read
Cleared by software
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPBUF
D2
D1
Cleared by software
D6
D7
Receive Data
D0
ACK
FIGURE 22-12:
SDA
Receive Address
PIC16F193X/LF193X
DS41364B-page 293
DS41364B-page 294
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPIF is set
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPIF is set on
9th falling edge of
SCL, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 22-13:
SCL
SDA
PIC16F193X/LF193X
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Received
address is loaded into
SSPBUF
2 3
A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCL
Slave sends
not ACK
SSPBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 22-14:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16F193X/LF193X
DS41364B-page 295
PIC16F193X/LF193X
22.5.3
SLAVE TRANSMISSION
22.5.3.1
7-bit Transmission
1.
DS41364B-page 296
Preliminary
Preliminary
D/A
R/W
ACKSTAT
CKP
BF
SSPIF
Receiving Address
Indicates an address
has been received
R/W = 1 Automatic
ACK
Received address
is read from SSPBUF
A7 A6 A5 A4 A3 A2 A1
Transmitting Data
Automatic
Set by software
Data to transmit is
loaded into SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
FIGURE 22-15:
SCL
SDA
Master sends
Stop condition
PIC16F193X/LF193X
DS41364B-page 297
PIC16F193X/LF193X
22.5.3.2
DS41364B-page 298
Preliminary
Preliminary
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCL
Data to transmit is
loaded into SSPBUF
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
Masters ACK
response is copied
to SSPSTAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 22-16:
SCL
SDA
PIC16F193X/LF193X
DS41364B-page 299
PIC16F193X/LF193X
22.5.4
22.5.5
3.
4.
5.
6.
7.
8.
DS41364B-page 300
Preliminary
Preliminary
CKP
UA
BF
SSPIF
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCL is held low
If address matches
SSPADD it is loaded into
SSPBUF
ACK
A7 A6 A5 A4 A3 A2 A1 A0 ACK
9
1
Data is read
from SSPBUF
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
FIGURE 22-17:
SCL
SDA
Master sends
Stop condition
PIC16F193X/LF193X
DS41364B-page 301
DS41364B-page 302
Preliminary
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
R/W = 0
ACK
UA
A6
A5
A4
A3
A2
A1
Update to SSPADD is
not allowed until 9th
falling edge of SCL
SSPBUF can be
read anytime before
the next received byte
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
D1
Update of SSPADD,
clears UA and releases
SCL
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 22-18:
SSPIF
SCL
SDA
PIC16F193X/LF193X
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Preliminary
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPIF
Set by hardware
Indicates an address
has been received
UA indicates SSPADD
must be updated
SSPBUF loaded
with received address
SCL
1
3
7 8
After SSPADD is
updated, UA is cleared
and SCL is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
4
7 8
Set by hardware
2 3
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
Received address is
read from SSPBUF
Sr
1 1 1 1 0 A9 A8
ACK
Set by software
releases SCL
Data to transmit is
loaded into SSPBUF
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 22-19:
SDA
Master sends
Restart event
PIC16F193X/LF193X
DS41364B-page 303
PIC16F193X/LF193X
22.5.6
CLOCK STRETCHING
22.5.6.2
FIGURE 22-20:
Byte NACKing
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 22-19).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPCON1
DS41364B-page 304
Preliminary
PIC16F193X/LF193X
22.5.8
FIGURE 22-21:
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SCL
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
1
22.5.9
Preliminary
DS41364B-page 305
PIC16F193X/LF193X
22.6
22.6.1
2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and
the generation is complete.
DS41364B-page 306
Preliminary
PIC16F193X/LF193X
22.6.2
CLOCK ARBITRATION
FIGURE 22-22:
SDA
DX 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
03h
02h
22.6.3
Preliminary
DS41364B-page 307
PIC16F193X/LF193X
22.6.4
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 reg-
FIGURE 22-23:
SDA = 1,
SCL = 1
TBRG
TBRG
SDA
1st bit
2nd bit
TBRG
SCL
S
DS41364B-page 308
Preliminary
TBRG
PIC16F193X/LF193X
22.6.5
FIGURE 22-24:
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
TBRG
Repeated Start
Preliminary
DS41364B-page 309
PIC16F193X/LF193X
22.6.6
22.6.6.3
22.6.6.1
7.
8.
9.
10.
11.
12.
13.
BF Status Flag
22.6.6.2
DS41364B-page 310
Preliminary
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared by software
SSPBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
A7
D5
D4
D3
D2
D1
D0
D6
Cleared by software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 22-25:
SEN = 0
PIC16F193X/LF193X
DS41364B-page 311
PIC16F193X/LF193X
22.6.7
22.6.7.4
22.6.7.1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
BF Status Flag
11.
22.6.7.2
12.
22.6.7.3
13.
14.
15.
DS41364B-page 312
Preliminary
Preliminary
RCEN
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
A1
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Cleared in
software
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
RCEN = 1, start
next receive
Cleared by software
Cleared by software
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
R/W = 0
FIGURE 22-26:
SCL
SDA
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16F193X/LF193X
DS41364B-page 313
PIC16F193X/LF193X
22.6.8
ACKNOWLEDGE SEQUENCE
TIMING
22.6.9
22.6.8.1
22.6.9.1
FIGURE 22-27:
TBRG
SDA
ACK
D0
SCL
SSPIF
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Cleared in
software
FIGURE 22-28:
Write to SSPCON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
DS41364B-page 314
Preliminary
PIC16F193X/LF193X
22.6.10
SLEEP OPERATION
22.6.13
22.6.11
EFFECTS OF A RESET
22.6.12
MULTI-MASTER MODE
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin is 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 22-28).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 22-29:
SDA
SCL
BCLIF
Preliminary
DS41364B-page 315
PIC16F193X/LF193X
22.6.13.1
FIGURE 22-30:
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN
BCLIF
SSPIF
DS41364B-page 316
Preliminary
PIC16F193X/LF193X
FIGURE 22-31:
TBRG
SDA
SCL
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
SSPIF
FIGURE 22-32:
SDA
Set SSPIF
TBRG
SCL
S
SCL pulled low after BRG
time-out
SEN
BCLIF
SSPIF
SDA = 0, SCL = 1,
set SSPIF
Preliminary
Interrupts cleared
by software
DS41364B-page 317
PIC16F193X/LF193X
22.6.13.2
FIGURE 22-33:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
SDA
SCL
BCLIF
Cleared by software
S
SSPIF
FIGURE 22-34:
TBRG
SDA
SCL
BCLIF
RSEN
S
SSPIF
DS41364B-page 318
Preliminary
PIC16F193X/LF193X
22.6.13.3
b)
FIGURE 22-35:
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 22-36:
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
Preliminary
DS41364B-page 319
PIC16F193X/LF193X
22.7
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 22-6).
When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
EQUATION 22-1:
FOSC
FCLOCK = ---------------------------------------------( SSPADD + 1 ) ( 4 )
FIGURE 22-37:
SSPM<3:0>
Reload
SCL
Control
SSPADD<7:0>
Reload
SSPCLK
FOSC/2
TABLE 22-3:
Note 1:
2:
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz(1)
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz(1)
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
4 MHz
1 MHz
00h
250 kHz(2)
The I C interface does not conform to the 400 kHz I C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SPI mode only.
DS41364B-page 320
Preliminary
PIC16F193X/LF193X
23.0
23.1
EECON1
EECON2
EEDATL
EEDATH
EEADRL
EEADRH
23.1.1
Preliminary
DS41364B-page 321
PIC16F193X/LF193X
REGISTER 23-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDATL7
EEDATL6
EEDATL5
EEDATL4
EEDATL3
EEDATL2
EEDATL1
EEDATL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
EEDATL<7:0>: 8 Least Significant data bits of data EEPROM or Read from program memory
REGISTER 23-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
EEDATH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 23-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 23-4:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADRH6
EEADRH5
EEADRH4
EEADRH3
EEADRH2
EEADRH1
EEADRH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-0
EEADRH<6:0>: Specifies the 7 Most Significant Address bits or high bits for program memory reads
DS41364B-page 322
Preliminary
PIC16F193X/LF193X
REGISTER 23-5:
R/W-0/0
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W-x/q
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41364B-page 323
PIC16F193X/LF193X
REGISTER 23-6:
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
EEUNLK7
EEUNLK6
EEUNLK5
EEUNLK4
EEUNLK3
EEUNLK2
EEUNLK1
EEUNLK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS41364B-page 324
Preliminary
PIC16F193X/LF193X
23.1.2
23.1.3
EXAMPLE 23-1:
BANKSEL EEADRL
;
MOVLW
DATA_EE_ADDR ;
MOVWF
EEADRL
;Data Memory
;Address to read
BCF
EECON1, CFGS ;Deselect Config space
BCF
EECON1, EEPGD;Point to DATA memory
BSF
EECON1, RD
;EE Read
MOVF
EEDATL, W
;W = EEDATL
BCF
STATUS, RP1 ;Bank 0
Note:
Required
Sequence
EXAMPLE 23-2:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
EEADRL
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
;Point to DATA memory
;Enable writes
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
;Disable INTs.
;SEE AN576
BCF
BTFSC
GOTO
EECON1, WREN
EECON1, WR
$-2
;Disable writes
;Wait for write to complete
;Done
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
Preliminary
DS41364B-page 325
PIC16F193X/LF193X
23.1.4
2.
3.
4.
Required
Sequence
EXAMPLE 23-3:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BSF
BSF
EEADRL
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADRL
EECON1
EECON1, EEPGD
EECON1, RD
;
;
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
;
;Point to PROGRAM memory
;EE Read
;
BANKSEL EEDATL
MOVF
EEDATL, W
MOVWF
LOWPMBYTE
MOVF
EEDATH, W
MOVWF
HIGHPMBYTE
BCF STATUS, RP1
DS41364B-page 326
;
;W = LS Byte of Program Memory
;
;W = MS Byte of Program EEDATL
;
;Bank 0
Preliminary
PIC16F193X/LF193X
EXAMPLE 23-4:
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
FIGURE 23-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
Flash Data
PC
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
EEADRH,EEADRL
INSTR (PC + 1)
BSF EECON1,RD
executed here
PC
+3
PC+3
EEDATH,EEDATL
INSTR(PC + 1)
executed here
PC + 5
PC + 4
INSTR (PC + 3)
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
EERHLT
Preliminary
DS41364B-page 327
PIC16F193X/LF193X
23.2
23.3
DS41364B-page 328
Preliminary
PIC16F193X/LF193X
FIGURE 23-2:
0 7
EEDATH
EEDATA
14
14
14
EEADRL<2:0> = 000
EEADRL<2:0> = 010
EEADRL<2:0> = 001
Buffer Register
Buffer Register
Buffer Register
14
EEADRL<2:0> = 111
Buffer Register
Program Memory
Preliminary
DS41364B-page 329
PIC16F193X/LF193X
EXAMPLE 23-5:
;
;
;
;
;
Required
Sequence
LOOP
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
EEADRH
ADDRH,W
EEADRH
ADDRL,W
EEADRL
DATAADDRL,W
FSR0L
DATAADDRH,W
FSR0H
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
BSF
BCF
BSF
BSF
INDF0++
EEDATL
INDF0++
EEDATH
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
;
;
;
;
;
;
;
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
;
;
NOP
NOP
MOVF
EEADR,W
XORLW
0x08
ANDLW
0x08
BTFSC
STATUS,Z
GOTO
START_WRITE
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Write AAh
Set WR bit to begin write
EECON1,LWLO
55h
EECON2
AAh
EECON2
EECON1,WR
;
;
;
;
;
EECON1,WREN
;
;
;
;
;
NOP
DS41364B-page 330
EEADR,F
LOOP
NOP
BCF
Bank 3
Load initial address
Write AAh
Set WR bit to begin write
Preliminary
PIC16F193X/LF193X
23.4
TABLE 23-1:
Address
Function
Read Access
Write Access
8000h-8003h
8006h
8007h-8008h
User IDs
Device ID/Revision ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 23-3:
EEADRL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
; Select Bank 2
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
INTCON,GIE
;
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
EEDATL,W
PROG_DATA_LO
EEDATH,W
PROG_DATA_HI
;
;
;
;
Preliminary
DS41364B-page 331
PIC16F193X/LF193X
23.5
Write Verify
23.6
EXAMPLE 23-6:
WRITE VERIFY
XORWF
BTFSS
GOTO
:
23.5.1
;
;EEDATL not changed
;from previous write
EECON1, RD ;YES, Read the
;value written
EEDATL, W ;
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
Brown-out
Power Glitch
Software Malfunction
23.7
TABLE 23-2:
BANKSEL EEDATL
MOVF
EEDATL, W
BSF
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
EECON1
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
323
324*
322
322
322
322
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
PIR2
OSFIF
C2IF
C1IF
EEIF
BCLIF
LCDIF
CCP2IF
78
DS41364B-page 332
Preliminary
PIC16F193X/LF193X
24.0
24.1
The first two events will cause a device Reset. The last
three events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
Certain peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
Preliminary
DS41364B-page 333
PIC16F193X/LF193X
24.2
FIGURE 24-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON reg.)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC + 1
Inst(PC) = Sleep
Inst(PC - 1)
PC + 2
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
TABLE 24-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
104
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
104
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
104
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
73
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
74
PIE2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIE
C2IE
C1IE
EEIE
BCLIE
LCDIE
CCP2IE
78
Legend: x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used in Power-down
mode.
DS41364B-page 334
Preliminary
PIC16F193X/LF193X
25.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
Note:
25.2
1.
2.
FIGURE 25-1:
25.1
Device to be
Programmed
VDD
VDD
VDD
10k
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
Preliminary
DS41364B-page 335
PIC16F193X/LF193X
NOTES:
DS41364B-page 336
Preliminary
PIC16F193X/LF193X
26.0
26.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
The literal and control category contains the most varied instruction word format.
TABLE 26-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
mm
TABLE 26-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-out bit
C
DC
Z
PD
Description
PC
Preliminary
Carry bit
Digit carry bit
Zero bit
Power-down bit
DS41364B-page 337
PIC16F193X/LF193X
FIGURE 26-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
k (literal)
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS41364B-page 338
Preliminary
PIC16F193X/LF193X
TABLE 26-3:
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
01
01
2
2
1, 2
1, 2
f, b
f, b
1 (2)
1 (2)
01
01
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
Preliminary
DS41364B-page 339
PIC16F193X/LF193X
TABLE 26-3:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
mm n
n mm
k[n]
mm n
n mm
k[n]
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
01kk
0001
0000
0000
1111
0000
0000
1111
0nkk
0001
0001
0nkk
0001
0001
1nkk
kkkk
0mmn Z
0nmm Z
kkkk Z
1mmn
1nmm
kkkk
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
MOVWI
1
1
1
1
1
1
1
11
00
00
11
00
00
11
2
2
2
2
2
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
DS41364B-page 340
Preliminary
PIC16F193X/LF193X
26.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
[ label ] ADDFSR n, k
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
Operation:
FSR(n) + k FSR(n)
Status Affected:
Status Affected:
None
Description:
Description:
AND W with f
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ADDLW
ANDWF
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d [0,1]
Operation:
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
ADDWF
Add W and f
f,d
Status Affected:
Description:
ASRF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
f,d
Status Affected:
C, DC, Z
Description:
ADDWFC
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
f {,d}
Status Affected:
C, Z
Description:
f {,d}
Preliminary
DS41364B-page 341
PIC16F193X/LF193X
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
[ label ] BRA
Syntax:
Operands:
-256 k 255
Operands:
Operation:
(PC) + k PC
0 f 127
0b<7
Status Affected:
None
Operation:
skip if (f<b>) = 1
Description:
Status Affected:
None
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS41364B-page 342
f,b
Preliminary
PIC16F193X/LF193X
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
f,d
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
Preliminary
DS41364B-page 343
PIC16F193X/LF193X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
DS41364B-page 344
INCF f,d
Preliminary
IORWF
f,d
PIC16F193X/LF193X
LSLF
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
f {,d}
Status Affected:
C, Z
Description:
register f
Description:
Words:
Cycles:
Syntax:
[ label ] LSLF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
f {,d}
register f
MOVF f,d
Status Affected:
Example:
Move f
Preliminary
DS41364B-page 345
PIC16F193X/LF193X
MOVIW
Move INDFn to W
MOVLP
Syntax:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operands:
n [0,1]
mm [00, 01, 10, 11].
-32 k 31
If not present, k = 0.
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Operation:
k PCLATH
Status Affected:
None
Description:
MOVLW
Move literal to W
Syntax:
[ label ]
MOVLW k
Operands:
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
Words:
Cycles:
Status Affected:
mm
Mode
Syntax
00
Preincrement
++INDFn
01
Predecrement
--INDFn
10
Postincrement
INDFn++
MOVWF
Move W to f
11
Postdecrement
INDFn--
Syntax:
[ label ]
Description:
Example:
Syntax:
[ label ] MOVLB k
Operands:
0 k 15
Operation:
k BSR
Status Affected:
None
Description:
DS41364B-page 346
0x5A
0x5A
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVLB
MOVLW
After Instruction
W =
Preliminary
MOVWF
OPTION
Before Instruction
OPTION
W
After Instruction
OPTION
W
=
=
0xFF
0x4F
=
=
0x4F
0x4F
PIC16F193X/LF193X
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
Syntax:
[ label ]
Operands:
None
n [0,1]
mm [00, 01, 10, 11].
-32 k 31
If not present, k = 0.
Description:
No operation.
Words:
Cycles:
Operands:
Operation:
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
None
mm
Mode
00
Preincrement
++INDFn
01
Predecrement
--INDFn
10
Postincrement
INDFn++
11
Postdecrement
INDFn--
Description:
Syntax
NOP
Operation:
No operation
Status Affected:
None
Example:
NOP
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
Preliminary
DS41364B-page 347
PIC16F193X/LF193X
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RLF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
Operation:
k (W);
TOS PC
0 f 127
d [0,1]
Operation:
Status Affected:
None
Status Affected:
Description:
Description:
Words:
Cycles:
RETLW
Example:
TABLE
RETLW k
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
DS41364B-page 348
RLF
Words:
Cycles:
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
Preliminary
PIC16F193X/LF193X
SUBLW
Syntax:
[ label ]
RRF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
RRF f,d
SUBLW k
Operands:
0 k 255
Operation:
k - (W) (W)
Register f
C=0
W>k
C=1
Wk
DC = 0
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
Status Affected:
C, DC, Z
Description:
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
SUBWF f,d
C=0
W>f
C=1
Wf
DC = 0
DC = 1
W<3:0> f<3:0>
SUBWFB
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
f {,d}
Status Affected:
C, DC, Z
Description:
Preliminary
DS41364B-page 349
PIC16F193X/LF193X
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
Status Affected:
Description:
Operation:
SWAPF f,d
XORLW k
Status Affected:
None
Description:
TRIS
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
5f7
Operands:
Operation:
0 f 127
d [0,1]
Status Affected:
None
Operation:
Status Affected:
Description:
Description:
DS41364B-page 350
Preliminary
XORWF
f,d
PIC16F193X/LF193X
27.0
DEVELOPMENT SUPPORT
27.1
Preliminary
DS41364B-page 351
PIC16F193X/LF193X
27.2
MPASM Assembler
27.5
27.6
27.3
27.4
DS41364B-page 352
Preliminary
PIC16F193X/LF193X
27.7
27.9
27.8
Preliminary
DS41364B-page 353
PIC16F193X/LF193X
27.11 PICSTART Plus Development
Programmer
DS41364B-page 354
Preliminary
PIC16F193X/LF193X
28.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
Preliminary
DS41364B-page 355
PIC16F193X/LF193X
PIC16F193X VOLTAGE FREQUENCY GRAPH, -40C TA +125C
FIGURE 28-1:
VDD (V)
5.5
3.6
2.5
2.3
2.0
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 28-1 for each Oscillator modes supported frequencies.
VDD (V)
FIGURE 28-2:
3.6
2.5
2.3
2.0
1.8
0
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 28-1 for each Oscillator modes supported frequencies.
DS41364B-page 356
Preliminary
PIC16F193X/LF193X
FIGURE 28-3:
125
+ 5%
Temperature (C)
85
60
2%
25
0
-20
+ 5%
-40
1.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Preliminary
DS41364B-page 357
PIC16F193X/LF193X
28.1
PIC16LF193X
PIC16F193X
Param.
No.
D001
Sym.
VDD
D001
D002*
VDR
D002*
Characteristic
Min.
Typ
Max.
Units
PIC16LF193X
1.8
2.3
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 32 MHz (NOTE 2)
PIC16F193X
1.8
2.3
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 32 MHz (NOTE 2)
Supply Voltage
1.5
PIC16F193X
1.7
1.6
PIC16LF193X
0.8
PIC16F193X
1.7
0.984
0.974
1.968
1.938
3.966
3.936
1.024
1.064
1.064
2.158
2.148
4.226
4.226
0.984
0.974
1.968
1.938
3.966
3.936
1.024
1.064
1.064
2.158
2.148
4.226
4.226
0.984
0.974
1.024
1.064
1.064
0.05
V/ms
VPOR*
VPORR*
VADFVR
VCDAFVR
SVDD
Conditions
2.048
4.096
2.048
4.096
Note
DS41364B-page 358
Preliminary
PIC16F193X/LF193X
FIGURE 28-4:
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
Preliminary
DS41364B-page 359
PIC16F193X/LF193X
28.2
PIC16LF193X
PIC16F193X
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
LDO Regulator
D010
D010
D011*
D011*
350
TBD
50
TBD
30
TBD
TBD
7.0
TBD
1.8
9.0
TBD
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40C TA +85C
9.5
TBD
1.8
12.5
TBD
3.0
13.5
TBD
5.0
7.0
TBD
1.8
9.0
TBD
3.0
9.5
TBD
1.8
12.5
TBD
3.0
13.5
TBD
5.0
D011A*
150
TBD
1.8
270
TBD
3.0
D011A*
160
TBD
1.8
280
TBD
3.0
390
TBD
5.0
430
TBD
1.8
750
TBD
3.0
450
TBD
1.8
770
TBD
3.0
D012
D012
D013*
930
TBD
5.0
180
TBD
1.8
350
TBD
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40C TA +85C
FOSC = 32 kHz
LP Oscillator mode
FOSC = 32 kHz
LP Oscillator mode (Note 4)
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode (Note 5)
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
FOSC = 1 MHz
EC Oscillator mode
DS41364B-page 360
Preliminary
PIC16F193X/LF193X
28.2
PIC16LF193X
PIC16F193X
Param
No.
Conditions
Device
Characteristics
Min.
Typ
Max.
Units
VDD
200
TBD
1.8
370
TBD
3.0
450
TBD
5.0
D014
450
TBD
1.8
830
TBD
3.0
D014
475
TBD
1.8
850
TBD
3.0
D013*
Note
FOSC = 1 MHz
EC Oscillator mode (Note 5)
(1, 2)
D015
D015
D016*
D016*
980
TBD
5.0
130
TBD
1.8
190
TBD
3.0
150
TBD
1.8
210
TBD
3.0
270
TBD
5.0
980
TBD
1.8
1780
TBD
3.0
1.0
TBD
mA
1.8
1.8
TBD
mA
3.0
TBD
mA
5.0
TBD
mA
1.8
2.0
D017
1.5
2.8
TBD
mA
3.0
D017
1.7
TBD
mA
1.8
2.9
TBD
mA
3.0
3.1
TBD
mA
5.0
D018
410
TBD
1.8
710
TBD
3.0
D018
430
TBD
1.8
730
TBD
3.0
D019
860
TBD
5.0
5.3
TBD
mA
3.0
6.0
TBD
mA
3.6
FOSC = 4 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode (Note 5)
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode (Note 5)
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 32 MHz
HS Oscillator mode
Preliminary
DS41364B-page 361
PIC16F193X/LF193X
28.2
PIC16LF193X
PIC16F193X
Param
No.
Device
Characteristics
D019
Conditions
Min.
Typ
Max.
Units
VDD
5.3
TBD
mA
3.0
6.0
TBD
mA
5.0
Note
FOSC = 32 MHz
HS Oscillator mode (Note 5)
DS41364B-page 362
Preliminary
PIC16F193X/LF193X
28.3
PIC16LF193X
PIC16F193X
Param
No.
Device Characteristics
Power-down Base Current
Min.
Typ
Conditions
Max.
+85C
Max.
+125C
Units
VDD
D020
0.06
TBD
TBD
0.08
TBD
TBD
3.0
D020
3.1
TBD
TBD
1.8
3.6
TBD
TBD
3.0
4.5
TBD
TBD
5.0
0.5
TBD
TBD
1.8
0.8
TBD
TBD
3.0
3.8
TBD
TBD
1.8
4.3
TBD
TBD
3.0
D021
D021
D021A
D021A
1.8
5.3
TBD
TBD
5.0
8.5
TBD
TBD
1.8
8.5
TBD
TBD
3.0
32
TBD
TBD
1.8
39
TBD
TBD
3.0
70
TBD
TBD
mA
5.0
D022
TBD
TBD
1.8
7.5
TBD
TBD
3.0
D022
TBD
TBD
1.8
34
TBD
TBD
3.0
67
TBD
TBD
5.0
0.6
TBD
TBD
1.8
1.8
TBD
TBD
3.0
4.5
TBD
TBD
1.8
TBD
TBD
3.0
TBD
TBD
5.0
D026
D026
Legend:
Note 1:
2:
3:
4:
5:
Note
(IPD)(2)
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
Preliminary
DS41364B-page 363
PIC16F193X/LF193X
28.3
PIC16LF193X
PIC16F193X
Param
No.
Device Characteristics
Min.
Typ
Conditions
Max.
+85C
Max.
+125C
Units
VDD
Note
(2)
0.1
TBD
TBD
1.8
0.1
TBD
TBD
3.0
3.5
TBD
TBD
1.8
TBD
TBD
3.0
4.5
TBD
TBD
5.0
D027A
250
TBD
TBD
1.8
250
TBD
TBD
3.0
D027A
280
TBD
TBD
1.8
280
TBD
TBD
3.0
280
TBD
TBD
5.0
3.5
TBD
TBD
1.8
TBD
TBD
3.0
3.5
TBD
TBD
1.8
TBD
TBD
3.0
D028
D028
D029
D029
Legend:
Note 1:
2:
3:
4:
5:
Cap Sense
Cap Sense
32
TBD
TBD
5.0
TBD
TBD
3.6
10
TBD
TBD
3.6
100
TBD
TBD
3.6
TBD
TBD
5.0
10
TBD
TBD
5.0
100
TBD
TBD
5.0
DS41364B-page 364
Preliminary
PIC16F193X/LF193X
28.4
DC Characteristics: PIC16F193X/LF193X-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Typ
Max.
Units
Conditions
0.8
0.15 VDD
0.2 VDD
0.3 VDD
D030
D030A
D031
D032
D033A
VIH
0.8
0.2 VDD
0.3 VDD
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
D040
D040A
D041
2.1
D042
MCLR
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
(Note 1)
VSS VPIN VDD, Pin at highimpedance
125C
IIL
D060
I/O ports
100
nA
1000
nA
D061
MCLR(3)
50
200
nA
D063
OSC1
50
100
nA
25
25
100
140
200
300
0.6
IPUR
D070*
VOL
D080
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
Preliminary
DS41364B-page 365
PIC16F193X/LF193X
28.4
Param
No.
Sym.
VOH
D090
Characteristic
Typ
Max.
Units
VDD - 0.7
15
pF
50
pF
Conditions
D101A* CIO
Charging current
200
D102A
0.0
mA
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
DS41364B-page 366
Preliminary
PIC16F193X/LF193X
28.5
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
8.0
9.0
D111
IDDP
10
mA
2.7
VDD
max.
D112
D113
VPEW
VDD
min.
VDD
max.
D114
1.0
mA
D115
5.0
mA
D116
ED
Byte Endurance
D117
VDRW
D118
TDEW
(Note 3, Note 4)
100K
E/W
VDD
min.
VDD
max.
4.0
5.0
ms
D119
40
Year
Provided no other
specifications are violated
D120
TREF
1M
10M
E/W
-40C to +85C
D121
EP
Cell Endurance
10K
E/W
D122
VPR
VDD
min.
VDD
max.
D123
TIW
2.5
ms
D124
40
Year
-40C to +85C
Provided no other
specifications are violated
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Refer to Section 23.5.1 Using the Data EEPROM for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
Preliminary
DS41364B-page 367
PIC16F193X/LF193X
28.6
Thermal Considerations
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
JC
TJMAX
PD
Typ.
Units
Conditions
60
C/W
80
C/W
90
C/W
27.5
C/W
47.2
C/W
46
C/W
24.4
C/W
31.4
C/W
24
C/W
24
C/W
24
C/W
24.7
C/W
14.5
C/W
20
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS41364B-page 368
Preliminary
PIC16F193X/LF193X
28.7
FIGURE 28-5:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
Preliminary
DS41364B-page 369
PIC16F193X/LF193X
28.8
AC Characteristics: PIC16F193X/LF193X-I/E
FIGURE 28-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 28-1:
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
TCY
OS04*
TosH,
TosL
TosR,
TosF
OS05*
Min.
Typ
Max.
Units
Conditions
DC
MHz
DC
MHz
DC
32
MHz
32.768
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
MHz
20
MHz
DC
MHz
RC Oscillator mode
27
LP Oscillator mode
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
31.25
ns
EC Oscillator mode
30.5
LP Oscillator mode
250
10,000
ns
XT Oscillator mode
50
1,000
ns
HS Oscillator mode
250
ns
RC Oscillator mode
200
TCY
DC
ns
TCY = 4/FOSC
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
ns
LP oscillator
ns
XT oscillator
ns
HS oscillator
DS41364B-page 370
Preliminary
PIC16F193X/LF193X
TABLE 28-2:
OSCILLATOR PARAMETERS
Sym.
HFOSC
OS08A MFOSC
OS10*
Freq.
Tolerance
Characteristic
Min.
Typ
Max.
Units
Conditions
2%
16.0
MHz
0C TA +85C
5%
16.0
MHz
-40C TA +125C
2%
500
kHz
0C TA +85C
5%
500
kHz
-40C TA +125C
TABLE 28-3:
Param
No.
Sym.
Characteristic
Min.
F10
F11
FSYS
F12
TRC
F13*
CLK
Typ
Max.
Units
MHz
16
32
MHz
ms
-0.25%
+0.25%
Conditions
Preliminary
DS41364B-page 371
PIC16F193X/LF193X
FIGURE 28-7:
Cycle
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS41364B-page 372
Preliminary
PIC16F193X/LF193X
TABLE 28-4:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
70
ns
VDD = 3.3-5.0V
72
ns
VDD = 3.3-5.0V
OS11
TosH2ckL
OS12
(1)
(1)
OS13
TckL2ioV
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18
TioR
OS19
TioF
20
ns
TOSC + 200 ns
50
50
70*
ns
ns
ns
20
ns
25
25
40
15
28
15
72
32
55
30
ns
OS20* Tinp
OS21* Tioc
FIGURE 28-8:
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
ns
ns
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
Preliminary
DS41364B-page 373
PIC16F193X/LF193X
FIGURE 28-9:
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to 0.
2 ms delay if PWRTE = 0 and VREGEN = 1.
DS41364B-page 374
Preliminary
PIC16F193X/LF193X
TABLE 28-5:
Sym.
Characteristic
MCLR Pulse Width (low)
Min.
Typ
Max.
Units
Conditions
2
5
s
s
10
10
18
18
27
33
ms
ms
30
TMCL
31
32
TOST
1024
Tosc (Note 3)
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.40
1.80
2.5
1.9
2.60
2.00
36*
VHYST
25
50
75
100
mV
-40C to +85C
-40C to 125C
37*
5
10
Note 1:
2:
3:
4:
BORV=2.5V
BORV=1.9V
Preliminary
DS41364B-page 375
PIC16F193X/LF193X
FIGURE 28-10:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 28-6:
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
No Prescaler
TT0P
T0CKI Period
45*
TT1H
ns
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
Asynchronous
TT1L
46*
T1CKI Low
Time
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
47*
TT1P
48
FT1
49*
Asynchronous
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ
60
ns
32.4
32.768
33.1
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
DS41364B-page 376
Preliminary
PIC16F193X/LF193X
FIGURE 28-11:
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 28-7:
Characteristic
CC01* TccL
CC02* TccH
CC03* TccP
*
Min.
Typ
Max.
Units
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
No Prescaler
Conditions
TABLE 28-8:
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10
AD02
EIL
Integral Error
AD03
EDL
Differential Error
AD04
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
AD09* IREF
Note 1:
2:
3:
4:
Gain Error
bit
1.8
VDD
VSS
VREF
Recommended Impedance of
Analog Voltage Source
50
10
1000
10
V
V
Preliminary
DS41364B-page 377
PIC16F193X/LF193X
TABLE 28-9:
Sym.
Characteristic
AD130* TAD
AD131
TCNV
AD132* TACQ
Min.
Typ
Max.
Units
Conditions
1.0
9.0
TOSC-based
1.0
1.6
6.0
10.5
TAD
Acquisition Time
9.5
FIGURE 28-12:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS41364B-page 378
Preliminary
PIC16F193X/LF193X
FIGURE 28-13:
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Preliminary
DS41364B-page 379
PIC16F193X/LF193X
TABLE 28-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
CM01
VIOFF
7.5
15
mV
CM02
VICM
VDD
CM03
CMRR
55
dB
CM04
TRESP
Response Time
150
400
ns
CM05
TMC2OV
10
*
Note 1:
Comments
Note 1
Sym.
Characteristics
Min.
Typ.
Max.
Units
VDD/32
CLSB
Step Size(2)
DAC02*
CACC
Absolute Accuracy
1/2
LSb
DAC03*
CR
TBD
CST
Time(1)
10
DAC01*
DAC04*
Settling
Comments
*
These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from 0000 to 1111.
Sym.
VFVR
Characteristics
Fixed Voltage Reference
Voltage
(calibrated)
Typ.
Max.
Units
Comments
0.984
0.974
1.968
1.938
3.966
3.936
1.024
1.064
1.064
2.158
2.148
4.226
4.226
TBD
TBD
ppm/C
2.048
4.096
VR02
TCVOUT
VR03
TBD
V/V
VR04
TSTABLE
TBD
TBD
Settling Time
DS41364B-page 380
Preliminary
PIC16F193X/LF193X
FIGURE 28-14:
CK
US121
US121
DT
US122
US120
Note:
Symbol
Characteristic
Min.
Max.
Units
3.0-5.5V
80
ns
1.8-5.5V
100
ns
US121 TCKRF
3.0-5.5V
45
ns
1.8-5.5V
50
ns
3.0-5.5V
45
ns
1.8-5.5V
50
ns
US122 TDTRF
FIGURE 28-15:
Conditions
Symbol
Characteristic
Preliminary
Min.
Max.
Units
10
ns
15
ns
Conditions
DS41364B-page 381
PIC16F193X/LF193X
FIGURE 28-16:
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 28-5 for load conditions.
FIGURE 28-17:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SDO
MSb
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 28-5 for load conditions.
DS41364B-page 382
Preliminary
PIC16F193X/LF193X
FIGURE 28-18:
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 28-5 for load conditions.
FIGURE 28-19:
SS
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
MSb
SDO
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 28-5 for load conditions.
Preliminary
DS41364B-page 383
PIC16F193X/LF193X
TABLE 28-15: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ
TCY
ns
SP71* TSCH
TCY + 20
ns
SP72* TSCL
TCY + 20
ns
100
ns
SP74* TSCH2DIL,
TSCL2DIL
100
ns
SP75* TDOR
10
25
ns
SP76* TDOF
3.0-5.5V
1.8-5.5V
25
50
ns
10
25
ns
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
SP79* TSCF
10
25
ns
3.0-5.5V
50
ns
1.8-5.5V
145
ns
Tcy
ns
SP82* TSSL2DOV
50
ns
1.5TCY + 40
ns
FIGURE 28-20:
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 28-5 for load conditions.
DS41364B-page 384
Preliminary
PIC16F193X/LF193X
TABLE 28-16: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
Characteristic
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Start condition
Typ
4700
Max. Units
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
FIGURE 28-21:
SP100
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 28-5 for load conditions.
Preliminary
DS41364B-page 385
PIC16F193X/LF193X
TABLE 28-17: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
SP100* THIGH
Characteristic
Clock high time
Min.
Max.
Units
4.0
0.6
1.5TCY
4.7
1.3
SSP module
SP101* TLOW
SSP module
SP102* TR
SP103* TF
SP90*
SP91*
TSU:STA
THD:STA
SP106* THD:DAT
SP107* TSU:DAT
SP92*
TSU:STO
SP109* TAA
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Conditions
1.5TCY
1000
ns
0.1CB
300
ns
250
ns
20 + 0.1CB
250
ns
CB is specified to be from
10-400 pF
Only relevant for
Repeated Start condition
20 +
4.7
0.6
4.0
0.6
ns
0.9
250
ns
100
ns
Start condition
setup time
4.7
0.6
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
DS41364B-page 386
Preliminary
PIC16F193X/LF193X
TABLE 28-18: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
CS01
CS02
Symbol
ISRC
ISNK
Characteristic
Current Source
Current Sink
Min.
Typ
Max.
Units
High
-5.8
Medium
-1.1
Low
-0.2
High
6.6
Medium
1.3
Low
0.24
CS03
VCTH
Cap Threshold
High
0.8
CS04
VCTL
Cap Threshold
Low
0.4
Conditions
FIGURE 28-22:
VCTH
VCTL
ISRC
Enabled
ISNK
Enabled
Preliminary
DS41364B-page 387
PIC16F193X/LF193X
NOTES:
DS41364B-page 388
Preliminary
PIC16F193X/LF193X
29.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Preliminary
DS41364B-page 389
PIC16F193X/LF193X
NOTES:
DS41364B-page 390
Preliminary
PIC16F193X/LF193X
30.0
PACKAGING INFORMATION
30.1
28-Lead SPDIP
Example
PIC16F1936
-I/SP e3
0810017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F1937
-I/P e3
0810017
Example
28-Lead QFN
16F1936
-I/ML e3
0810017
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Preliminary
DS41364B-page 391
PIC16F193X/LF193X
Package Marking Information (Continued)
Example
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F1937
-I/ML e3
0810017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F1936
-I/SO e3
0810017
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16F1936
-I/SS e3
0810017
44-Lead TQFP
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
DS41364B-page 392
PIC16F1937
-I/PT e3
0810017
Preliminary
PIC16F193X/LF193X
30.2
Package Details
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DS41364B-page 393
PIC16F193X/LF193X
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Preliminary
PIC16F193X/LF193X
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DS41364B-page 397
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Preliminary
PIC16F193X/LF193X
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DS41364B-page 399
PIC16F193X/LF193X
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Preliminary
PIC16F193X/LF193X
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DS41364B-page 401
PIC16F193X/LF193X
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DS41364B-page 402
Preliminary
PIC16F193X/LF193X
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
Revision B (04/2009)
Revised data sheet title; Revised Features section.
B.1
PIC16F917 to PIC16F193X/LF193X
TABLE B-1:
FEATURE COMPARISON
Feature
PIC16F917
PIC16F1937
20 MHz
32 MHz
8K
8K
Max. Program
Memory (Words)
Max. SRAM (Bytes)
368
512
10-bit
10-bit
Timers (8/16-bit)
2/1
4/1
Oscillator Modes
A/D Resolution
Brown-out Reset
Internal Pull-ups
RB<7:0>
RB<7:0>
Interrupt-on-change
RB<7:4>
RB<7:0>
Comparator
AUSART/EUSART
1/0
0/1
Extended WDT
Software Control
Option of WDT/BOR
INTOSC Frequencies
30 kHz 8 MHz
Clock Switching
Capacitive Sensing
CCP/ECCP
Enhanced PIC16 CPU
MSSP/SSP
LCD
Preliminary
2/0
2/3
0/1
1/0
DS41364B-page 403
PIC16F193X/LF193X
NOTES:
DS41364B-page 404
Preliminary
PIC16F193X/LF193X
INDEX
A
A/D
Specifications.................................................... 377, 378
Absolute Maximum Ratings .............................................. 355
AC Characteristics
Industrial and Extended ............................................ 370
Load Conditions ........................................................ 369
ACKSTAT ......................................................................... 310
ACKSTAT Status Flag ...................................................... 310
ADC .................................................................................. 131
Acquisition Requirements ......................................... 140
Associated registers.................................................. 142
Block Diagram........................................................... 131
Calculating Acquisition Time..................................... 140
Channel Selection..................................................... 132
Configuration............................................................. 132
Configuring Interrupt ................................................. 136
Conversion Clock...................................................... 132
Conversion Procedure .............................................. 136
Internal Sampling Switch (RSS) Impedance.............. 140
Interrupts................................................................... 134
Operation .................................................................. 135
Operation During Sleep ............................................ 135
Port Configuration ..................................................... 132
Reference Voltage (VREF)......................................... 132
Source Impedance.................................................... 140
Special Event Trigger................................................ 135
Starting an A/D Conversion ...................................... 134
ADCON0 Register....................................................... 36, 137
ADCON1 Register....................................................... 36, 138
ADDFSR ........................................................................... 341
ADDWFC .......................................................................... 341
ADRESH Register............................................................... 36
ADRESH Register (ADFM = 0) ......................................... 138
ADRESH Register (ADFM = 1) ......................................... 139
ADRESL Register (ADFM = 0).......................................... 139
ADRESL Register (ADFM = 1).......................................... 139
Alternate Pin Function......................................................... 84
Analog-to-Digital Converter. See ADC
ANSELA Register ............................................................... 86
ANSELB Register ............................................................... 91
ANSELD Register ............................................................... 97
ANSELE Register ............................................................. 101
APFCON Register............................................................... 84
Assembler
MPASM Assembler................................................... 352
B
BAUDCON Register.......................................................... 224
BF ............................................................................. 310, 312
BF Status Flag .......................................................... 310, 312
Block Diagram
Capacitive Sensing ................................................... 177
Block Diagrams
(CCP) Capture Mode Operation ............................... 187
ADC .......................................................................... 131
ADC Transfer Function ............................................. 141
Analog Input Model ........................................... 141, 147
CCP PWM................................................................. 191
Clock Source............................................................. 107
Comparator ............................................................... 144
Compare ................................................................... 189
Crystal Operation ...................................................... 110
C
C Compilers
MPLAB C18.............................................................. 352
MPLAB C30.............................................................. 352
CALL................................................................................. 343
CALLW ............................................................................. 343
Capacitive Sensing ........................................................... 177
Associated registers w/ Capacitive Sensing............. 181
Specifications ........................................................... 387
Capture Module. See Enhanced Capture/Compare/
PWM(ECCP)
Capture/Compare/PWM ................................................... 183
Capture/Compare/PWM (CCP) ........................................ 185
Associated Registers w/ Capture ............................. 188
Associated Registers w/ Compare ........................... 190
Associated Registers w/ PWM ................................. 211
Capture Mode........................................................... 187
CCPx Pin Configuration............................................ 187
Clock Selection......................................................... 185
Compare Mode......................................................... 189
CCPx Pin Configuration.................................... 189
Software Interrupt Mode ........................... 187, 189
Special Event Trigger ....................................... 189
Timer1 Mode Selection............................. 187, 189
Prescaler .................................................................. 187
PWM Mode............................................................... 191
Duty Cycle ........................................................ 192
Effects of Reset ................................................ 194
Example PWM Frequencies and
Resolutions, 20 MHZ ................................ 193
Example PWM Frequencies and
Resolutions, 32 MHZ ................................ 193
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 193
Operation in Sleep Mode.................................. 194
Resolution ........................................................ 193
Preliminary
DS41364B-page 405
PIC16F193X/LF193X
Setup for Operation........................................... 194
System Clock Frequency Changes................... 194
PWM Period .............................................................. 192
Setup for PWM Operation ......................................... 194
CCP1CON Register ...................................................... 40, 41
CCPR1H Register ......................................................... 40, 41
CCPR1L Register.......................................................... 40, 41
CCPTMRS0 Register ........................................................ 185
CCPTMRS1 Register ........................................................ 186
CCPxAS Register.............................................................. 204
CCPxCON (ECCPx) Register ........................................... 184
Clock Accuracy with Asynchronous Operation ................. 222
Clock Sources
External Modes ......................................................... 109
EC ..................................................................... 109
HS ..................................................................... 110
LP...................................................................... 110
OST................................................................... 109
RC..................................................................... 111
XT ..................................................................... 110
Internal Modes .......................................................... 111
Frequency Selection ......................................... 115
HFINTOSC........................................................ 112
Internal Oscillator Clock Switch Timing............. 115
INTOSC ............................................................ 111
INTOSCIO......................................................... 111
LFINTOSC ........................................................ 112
MFINTOSC ....................................................... 112
Clock Switching................................................................. 117
CMOUT Register............................................................... 149
CMxCON0 Register .......................................................... 148
CMxCON1 Register .......................................................... 149
Code Examples
A/D Conversion ......................................................... 136
Changing Between Capture Prescalers .................... 187
Initializing PORTA ....................................................... 85
Initializing PORTB ....................................................... 89
Initializing PORTC....................................................... 93
Initializing PORTD....................................................... 96
Initializing PORTE ..................................................... 101
Write Verify ............................................................... 332
Writing to Flash Program Memory ............................ 330
Comparator
Associated Registers ................................................ 150
Operation .................................................................. 143
Comparator Module .......................................................... 143
Cx Output State Versus Input Conditions ................. 145
Comparator Specifications ................................................ 380
Comparator Voltage Reference (CVREF)
Associated Registers ................................................ 156
Comparators
C2OUT as T1 Gate ................................................... 163
Compare Module. See Enhanced Capture/
Compare/PWM (ECCP)
CONFIG1 Register............................................................ 126
CONFIG2 Register............................................................ 128
Core Registers .................................................................... 49
CPSCON0 Register .......................................................... 180
CPSCON1 Register .......................................................... 181
Customer Change Notification Service ............................. 413
Customer Notification Service........................................... 413
Customer Support ............................................................. 413
D
DACCON0 (Digital-to-Analog Converter Control 0) Register..
153
DS41364B-page 406
E
ECCP/CCP. See Enhanced Capture/Compare/PWM
EEADR Registers ............................................................. 321
EEADRH Registers........................................................... 321
EEADRL Register ............................................................. 322
EEADRL Registers ........................................................... 321
EECON1 Register..................................................... 321, 323
EECON2 Register..................................................... 321, 324
EEDATH Register............................................................. 322
EEDATL Register ............................................................. 322
EEPROM Data Memory
Avoiding Spurious Write ........................................... 332
Write Verify ............................................................... 332
Effects of Reset
PWM mode ............................................................... 194
Electrical Specifications .................................................... 355
Enhanced Capture/Compare/PWM
Timer Resources ...................................................... 184
Enhanced Capture/Compare/PWM (ECCP)..................... 184
Enhanced PWM Mode.............................................. 195
Auto-Restart ..................................................... 205
Auto-shutdown.................................................. 203
Direction Change in Full-Bridge Output Mode.. 201
Full-Bridge Application...................................... 199
Full-Bridge Mode .............................................. 199
Half-Bridge Application ..................................... 198
Half-Bridge Application Examples .................... 206
Half-Bridge Mode.............................................. 198
Output Relationships (Active-High and
Active-Low)............................................... 196
Output Relationships Diagram.......................... 197
Programmable Dead Band Delay..................... 206
Shoot-through Current ...................................... 206
Start-up Considerations .................................... 203
Specifications ........................................................... 377
Enhanced Mid-range CPU.................................................. 14
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) .............................. 213
Errata .................................................................................. 11
EUSART ........................................................................... 213
Associated Registers
Baud Rate Generator ....................................... 226
Preliminary
PIC16F193X/LF193X
Asynchronous Mode ................................................. 215
12-bit Break Transmit and Receive .................. 233
Associated Registers
Receive..................................................... 221
Transmit.................................................... 217
Auto-Wake-up on Break ................................... 231
Baud Rate Generator (BRG) ............................ 225
Clock Accuracy ................................................. 222
Receiver............................................................ 218
Setting up 9-bit Mode with Address Detect....... 220
Transmitter........................................................ 215
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 230
Baud Rate Error, Calculating ............................ 225
Baud Rates, Asynchronous Modes .................. 227
Formulas ........................................................... 226
High Baud Rate Select (BRGH Bit) .................. 225
Synchronous Master Mode ............................... 234, 238
Associated Registers
Receive..................................................... 237
Transmit.................................................... 235
Reception.......................................................... 236
Transmission .................................................... 234
Synchronous Slave Mode
Associated Registers
Receive..................................................... 239
Transmit.................................................... 238
Reception.......................................................... 239
Transmission .................................................... 238
Extended Instruction Set
ADDFSR ................................................................... 341
F
Fail-Safe Clock Monitor..................................................... 119
Fail-Safe Condition Clearing ..................................... 119
Fail-Safe Detection ................................................... 119
Fail-Safe Operation................................................... 119
Reset or Wake-up from Sleep................................... 119
Firmware Instructions........................................................ 337
Fixed Voltage Reference (FVR)
Specifications............................................................ 380
Flash Program Memory .................................................... 321
Erasing...................................................................... 328
Writing....................................................................... 328
FSR Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48
FVRCON (Fixed Voltage Reference Control) Register ..... 156
I
I2C Mode (MSSP)
Acknowledge Sequence Timing................................ 314
Bus Collision
During a Repeated Start Condition ................... 318
During a Stop Condition.................................... 319
Effects of a Reset...................................................... 315
I2C Clock Rate w/BRG.............................................. 320
Master Mode
Operation .......................................................... 306
Reception.......................................................... 312
Start Condition Timing .............................. 308, 309
Transmission .................................................... 310
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 315
Multi-Master Mode .................................................... 315
Read/Write Bit Information (R/W Bit) ........................ 291
Slave Mode
Transmission .................................................... 296
Preliminary
DS41364B-page 407
PIC16F193X/LF193X
TMR1 ........................................................................ 165
INTOSC Specifications ..................................................... 371
IOCBF Register................................................................. 104
IOCBN Register ................................................................ 104
IOCBP Register................................................................. 104
L
LATA Register............................................................... 85, 93
LATB Register..................................................................... 90
LATD Register..................................................................... 96
LATE Register..................................................................... 99
LCD
Associated Registers ................................................ 272
Bias Voltage Generation ................................... 249, 250
Clock Source Selection ............................................. 248
Configuring the Module ............................................. 271
Disabling the Module ................................................ 271
Frame Frequency...................................................... 254
Interrupts ................................................................... 267
LCDCON Register .................................................... 241
LCDPS Register........................................................ 241
Multiplex Types ......................................................... 254
Operation During Sleep ............................................ 269
Pixel Control.............................................................. 254
Prescaler ................................................................... 248
Segment Enables...................................................... 254
Waveform Generation ............................................... 256
LCDCON Register..................................................... 241, 243
LCDCST Register ............................................................. 246
LCDDATAx Registers ............................................... 247, 252
LCDPS Register........................................................ 241, 244
LP Bits....................................................................... 248
LCDREF Register ............................................................. 245
LCDRL Register ................................................................ 252
LCDSEn Registers ............................................................ 247
Liquid Crystal Display (LCD) Driver .................................. 241
Load Conditions ................................................................ 369
LSLF.................................................................................. 345
LSRF ................................................................................. 345
M
Master Synchronous Serial Port. See MSSP
MCLR .................................................................................. 59
Internal ........................................................................ 59
Memory Organization.......................................................... 21
Data ............................................................................ 24
Program ...................................................................... 21
Microchip Internet Web Site .............................................. 413
Migrating from other PIC Microcontroller Devices............. 403
MOVIW.............................................................................. 346
MOVLB.............................................................................. 346
MOVWI.............................................................................. 347
MPLAB ASM30 Assembler, Linker, Librarian ................... 352
MPLAB ICD 2 In-Circuit Debugger.................................... 353
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 353
MPLAB Integrated Development Environment Software .. 351
MPLAB PM3 Device Programmer..................................... 353
MPLAB REAL ICE In-Circuit Emulator System................. 353
MPLINK Object Linker/MPLIB Object Librarian ................ 352
MSSP ................................................................................ 273
SSPBUF Register ..................................................... 283
SSPSR Register ....................................................... 283
DS41364B-page 408
O
OPCODE Field Descriptions............................................. 337
OPTION ............................................................................ 347
OPTION Register........................................................ 51, 159
OSCCON Register............................................................ 108
Oscillator
Associated Registers ................................................ 120
Oscillator Module .............................................................. 107
EC............................................................................. 107
HFINTOSC ............................................................... 107
HS............................................................................. 107
INTOSC .................................................................... 107
LFINTOSC ................................................................ 107
LP ............................................................................. 107
MFINTOSC ............................................................... 107
RC ............................................................................ 107
XT ............................................................................. 107
Oscillator Parameters ....................................................... 371
Oscillator Specifications.................................................... 370
Oscillator Start-up Timer (OST)
Specifications ........................................................... 375
Oscillator Switching
Fail-Safe Clock Monitor ............................................ 119
Two-Speed Clock Start-up........................................ 117
OSCSTAT Register .......................................................... 113
OSCTUNE Register.......................................................... 114
P
P1A/P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM (ECCP)............................................ 195
Packaging ......................................................................... 391
Marking ............................................................. 391, 392
PDIP Details ............................................................. 393
PCL and PCLATH............................................................... 52
PCL Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48
PCLATH Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47,
48
PCON Register ............................................................. 36, 65
PICSTART Plus Development Programmer..................... 354
PIE1 Register................................................................ 36, 74
PIE2 Register................................................................ 36, 75
PIE3 Register...................................................................... 76
Pin Diagram
PIC16F1933/1936/1938, PICLF1933/1936/1938,
28-pin PDIP/SOIC/SSOP ..................................... 3
PIC16F1933/1936/1938, PICLF1933/1936/1938,
28-pin QFN ........................................................... 4
PICF1934/1937/1939, PICLF1934/1937/1939,
44-pin QFN ........................................................... 7
PICF1934/1937/1939, PICLF1934/1937/1939,
44-pin TQFP ......................................................... 8
PICF1934/1937/1939,PICLF1934/1937/1939,
40-pin PDIP .......................................................... 6
Pinout Descriptions
PIC16F193X/PIC16LF193X........................................ 15
PIR1 Register ............................................................... 35, 77
PIR2 Register ............................................................... 35, 78
PIR3 Register ..................................................................... 79
PORTA ............................................................................... 85
ANSELA Register ....................................................... 86
Associated Registers .................................................. 88
PORTA Register ................................................... 35, 37
Specifications ........................................................... 373
PORTA Register ................................................................. 85
PORTB ............................................................................... 89
Preliminary
PIC16F193X/LF193X
Additional Pin Functions
Weak Pull-up ...................................................... 89
ANSELB Register ....................................................... 91
Associated Registers .................................................. 92
Interrupt-on-Change.................................................... 89
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 89
Pin Descriptions and Diagrams................................... 92
PORTB Register ................................................... 35, 37
PORTB Register ................................................................. 90
PORTC ............................................................................... 93
Associated Registers .................................................. 95
P1A.See Enhanced Capture/Compare/
PWM+ (ECCP+) ................................................. 93
Pin Descriptions and Diagrams................................... 95
PORTC Register ................................................... 35, 37
Specifications............................................................ 373
PORTC Register ................................................................. 93
PORTD ............................................................................... 96
Additional Pin Functions
ANSELD Register ............................................... 97
Associated Registers .................................................. 98
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 96
Pin Descriptions and Diagrams................................... 98
PORTD Register ................................................... 35, 37
PORTD Register ................................................................. 96
PORTE................................................................................ 99
ANSELE Register ..................................................... 101
Associated Registers ................................................ 102
Pin Descriptions and Diagrams................................. 102
PORTE Register ................................................... 35, 37
PORTE Register ................................................................. 99
Power-Down Mode (Sleep) ............................................... 333
Associated Registers ................................................ 334
Power-on Reset .................................................................. 59
Power-up Time-out Sequence ............................................ 64
Power-up Timer (PWRT) .................................................... 59
Specifications............................................................ 375
PR2 Register................................................................. 35, 43
Precision Internal Oscillator Parameters........................... 371
Program Memory ................................................................ 21
Map and Stack (PIC16F1933/LF1933,
PIC16F1934/LF1934) ......................................... 22
Map and Stack (PIC16F1936/LF1936,
PIC16F1937/LF1937) ......................................... 22
Map and Stack (PIC16F1938/LF1938,
PIC16F1939/LF1939) ......................................... 23
Programming, Device Instructions .................................... 337
PSTRxCON Register ........................................................ 208
Pulse Steering................................................................... 208
PWM (ECCP Module)
Pulse Steering........................................................... 208
Steering Synchronization .......................................... 210
PWM Mode. See Enhanced Capture/Compare/PWM ...... 195
PWMxCON Register ......................................................... 207
R
RCREG ............................................................................. 220
RCREG Register................................................................. 38
RCSTA Register ......................................................... 38, 223
Reader Response ............................................................. 414
Read-Modify-Write Operations ......................................... 337
Register
RCREG Register....................................................... 230
Registers
Preliminary
DS41364B-page 409
PIC16F193X/LF193X
PSTRxCON (Pulse Steering Control) ....................... 208
PWMxCON (Enhanced PWM Control) ..................... 207
RCSTA (Receive Status and Control)....................... 223
Special Function, Summary ........................................ 35
SRCON0 (SR Latch Control 0) ................................. 122
SRCON1 (SR Latch Control 1) ................................. 123
SSPADD (MSSP Address and Baud Rate,
I2C Mode).......................................................... 280
SSPCON1 (MSSP Control 1).................................... 277
SSPCON2 (SSP Control 2)....................................... 278
SSPCON3 (SSP Control 3)....................................... 279
SSPMSK (SSP Mask) ............................................... 280
SSPSTAT (SSP Status) ............................................ 276
STATUS ...................................................................... 50
T1CON (Timer1 Control)........................................... 169
T1GCON (Timer1 Gate Control) ............................... 170
TRISA (Tri-State PORTA) ........................................... 86
TRISB (Tri-State PORTB) ........................................... 91
TRISC (Tri-State PORTC) .......................................... 94
TRISD (Tri-State PORTD) .......................................... 97
TRISE (Tri-State PORTE) ......................................... 101
TxCON ...................................................................... 175
TXSTA (Transmit Status and Control) ...................... 222
WDTCON (Watchdog Timer Control).......................... 61
WPUB (Weak Pull-up PORTB) ................................... 90
RESET .............................................................................. 347
Reset................................................................................... 57
Reset Instruction ................................................................. 64
Resets ................................................................................. 57
Associated Registers .................................................. 68
Revision History ................................................................ 403
S
SCK................................................................................... 281
SDI .................................................................................... 281
SDO .................................................................................. 281
Serial Clock, SCK.............................................................. 281
Serial Data In (SDI) ........................................................... 281
Serial Data Out (SDO) ...................................................... 281
Shoot-through Current ...................................................... 206
Slave Select (SS) .............................................................. 281
Software Simulator (MPLAB SIM)..................................... 352
SPBRG.............................................................................. 225
SPBRG Register ........................................................... 37, 38
SPBRGH ........................................................................... 225
Special Event Trigger........................................................ 135
Special Function Registers (SFRs) ..................................... 35
SPI Mode (MSSP)
Associated Registers ................................................ 286
Serial Clock ............................................................... 281
Serial Data In ............................................................ 281
Serial Data Out ......................................................... 281
Slave Select .............................................................. 281
SPI Clock .................................................................. 283
Typical Connection ................................................... 282
SR Latch ........................................................................... 121
SRCON0 Register............................................................. 122
SRCON1 Register............................................................. 123
SS ..................................................................................... 281
SSPADD Register ....................................................... 39, 280
SSPBUF Register ............................................................... 39
SSPCON 1 Register.......................................................... 277
SSPCON Register............................................................... 39
SSPCON2 Register........................................................... 278
SSPCON3 Register........................................................... 279
SSPMSK Register............................................................. 280
DS41364B-page 410
T
T1CON Register ......................................................... 35, 169
T1GCON Register ............................................................ 170
T2CON Register ........................................................... 35, 43
Thermal Considerations.................................................... 368
Timer0............................................................................... 157
Associated Registers ................................................ 159
Operation .................................................................. 157
Specifications ........................................................... 376
Timer1............................................................................... 161
Associated registers ................................................. 171
Asynchronous Counter Mode ................................... 163
Reading and Writing ......................................... 163
Clock Source Selection............................................. 162
Interrupt .................................................................... 165
Operation .................................................................. 162
Operation During Sleep ............................................ 165
Oscillator................................................................... 163
Prescaler .................................................................. 163
Specifications ........................................................... 376
Timer1 Gate
Selecting Source .............................................. 163
TMR1H Register ....................................................... 161
TMR1L Register........................................................ 161
Timer2
Associated registers ................................................. 176
Timer2/4/6......................................................................... 173
Associated registers ................................................. 176
Timers
Timer1
T1CON ............................................................. 169
T1GCON........................................................... 170
Timer2/4/6
TxCON.............................................................. 175
Timing Diagrams
A/D Conversion......................................................... 378
A/D Conversion (Sleep Mode) .................................. 379
Acknowledge Sequence ........................................... 314
Asynchronous Reception.......................................... 220
Asynchronous Transmission..................................... 216
Asynchronous Transmission (Back to Back) ............ 216
Auto Wake-up Bit (WUE) During Normal Operation . 232
Auto Wake-up Bit (WUE) During Sleep .................... 232
Automatic Baud Rate Calibration.............................. 230
Baud Rate Generator with Clock Arbitration............. 307
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 317
Brown-out Reset (BOR)............................................ 374
Brown-out Reset Situations ........................................ 62
Bus Collision During a Repeated Start Condition
(Case 1)........................................................... 318
Bus Collision During a Repeated Start Condition
(Case 2)........................................................... 318
Bus Collision During a Start Condition (SCL = 0) ..... 317
Bus Collision During a Stop Condition (Case 1) ....... 319
Preliminary
PIC16F193X/LF193X
Bus Collision During a Stop Condition (Case 2) ....... 319
Bus Collision During Start Condition (SDA only) ...... 316
Bus Collision for Transmit and Acknowledge............ 315
CLKOUT and I/O....................................................... 372
Clock Synchronization .............................................. 304
Clock Timing ............................................................. 370
Comparator Output ................................................... 143
Enhanced Capture/Compare/PWM (ECCP) ............. 377
Fail-Safe Clock Monitor (FSCM) ............................... 120
First Start Bit Timing ................................................. 308
Full-Bridge PWM Output ........................................... 200
Half-Bridge PWM Output .................................. 198, 206
I2C Bus Data ............................................................. 385
I2C Bus Start/Stop Bits.............................................. 384
I2C Master Mode (7 or 10-Bit Transmission) ............ 311
I2C Master Mode (7-Bit Reception)........................... 313
I2C Stop Condition Receive or Transmit Mode ......... 314
INT Pin Interrupt.......................................................... 71
Internal Oscillator Switch Timing............................... 116
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 268
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 270
PWM Auto-shutdown ................................................ 205
Firmware Restart .............................................. 205
PWM Direction Change ............................................ 201
PWM Direction Change at Near 100% Duty Cycle ... 202
PWM Output (Active-High)........................................ 196
PWM Output (Active-Low) ........................................ 197
Repeat Start Condition.............................................. 309
Reset, WDT, OST and Power-up Timer ................... 373
Send Break Character Sequence ............................. 233
SPI Master Mode (CKE = 1, SMP = 1) ..................... 382
SPI Mode (Master Mode).......................................... 283
SPI Slave Mode (CKE = 0) ....................................... 383
SPI Slave Mode (CKE = 1) ....................................... 383
Synchronous Reception (Master Mode, SREN) ....... 237
Synchronous Transmission....................................... 235
Synchronous Transmission (Through TXEN) ........... 235
Time-out Sequence
Case 1 ................................................................ 66
Case 2 ................................................................ 67
Case 3 ................................................................ 67
Timer0 and Timer1 External Clock ........................... 376
Timer1 Incrementing Edge........................................ 165
Two Speed Start-up .................................................. 118
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 257
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 259
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 261
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 263
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 265
Type-A/Type-B in Static Drive................................... 256
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 258
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 260
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 262
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 264
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 266
USART Synchronous Receive (Master/Slave) ......... 381
USART Synchronous Transmission (Master/Slave) . 381
Wake-up from Interrupt ............................................. 334
Timing Diagrams and Specifications
PLL Clock.................................................................. 371
Timing Parameter Symbology........................................... 369
Timing Requirements
I2C Bus Data ............................................................. 386
I2C Bus Start/Stop Bits ............................................. 385
SPI Mode .................................................................. 384
TMR0 Register.................................................................... 35
TMR1H Register ................................................................. 35
TMR1L Register.................................................................. 35
TMR2 Register.............................................................. 35, 43
TRIS ................................................................................. 350
TRISA Register............................................................. 36, 86
TRISB ................................................................................. 89
TRISB Register............................................................. 36, 91
TRISC ................................................................................. 93
TRISC Register............................................................. 36, 94
TRISD ................................................................................. 96
TRISD Register............................................................. 36, 97
TRISE ................................................................................. 99
TRISE Register........................................................... 36, 101
Two-Speed Clock Start-up Mode...................................... 117
TXCON (Timer2/4/6) Register .......................................... 175
TxCON Register ............................................................... 211
TXREG ............................................................................. 215
TXREG Register ................................................................. 38
TXSTA Register.......................................................... 38, 222
BRGH Bit .................................................................. 225
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 381
Requirements, Synchronous Transmission...... 381
Timing Diagram, Synchronous Receive ........... 381
Timing Diagram, Synchronous Transmission... 381
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 231
Wake-up Using Interrupts ................................................. 334
Watchdog Timer (WDT)...................................................... 59
Clock Source .............................................................. 59
Modes......................................................................... 60
Period ......................................................................... 59
Specifications ........................................................... 375
WCOL ....................................................... 307, 310, 312, 314
WCOL Status Flag.................................... 307, 310, 312, 314
WDTCON Register ............................................................. 61
WPUB Register................................................................... 90
WWW Address ................................................................. 413
WWW, On-Line Support ..................................................... 11
Preliminary
DS41364B-page 411
PIC16F193X/LF193X
NOTES:
DS41364B-page 412
Preliminary
PIC16F193X/LF193X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
Preliminary
DS41364B-page 413
PIC16F193X/LF193X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: PIC16F193X/LF193X
N
Literature Number: DS41364B
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS41364B-page 414
Preliminary
PIC16F193X/LF193X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
Temperature
Range:
I
E
=
=
-40C to +85C
-40C to +125C
Package:
ML
P
PT
SO
SP
SS
=
=
=
=
=
=
Pattern:
c)
Note 1:
2:
Preliminary
DS41364B-page 415
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
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Tel: 480-792-7200
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Tel: 82-2-554-7200
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Fax: 86-27-5980-5118
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Tel: 886-7-536-4818
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Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
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Tel: 86-756-3210040
Fax: 86-756-3210049
03/26/09
DS41364B-page 416
Preliminary