ITBP205

Digital Design and Computer

Organization
Unit 10
Top Level View of Computer Systems
Prof. Walid Ibrahim

Outline
Architecture vs. Organization
Computer Components
Instruction cycle
Interrupts
2

Architecture vs.
Organization
Architect
ure

Those attributes visible to the

programmer and have a direct impact on
the execution of a program
Instruction set, number of bits used for
data representation, I/O mechanisms,
addressing techniques.
e.g. Is there a multiply instruction?

Organiza
tion

How features are implemented

Control signals, interfaces, memory
technology.
e.g. Is there a hardware multiply unit or is
it done by repeated addition?
3

Architecture vs.
Organization
All Intel x86 family share the same basic
architecture
The IBM System/370 family share the same
basic architecture
Organization differs between different
versions
This gives code backward compatibility
A new member of the family can still run the software
designed for old versions
For example, programs designed for Pentium I, can still
run on Pentium II, III, and IV.

BRIEF HISTORY OF THE x86

FAMILY

BRIEF HISTORY OF THE x86

FAMILY

BRIEF HISTORY OF THE x86

FAMILY

Internal Organization of
Computers
Internal workings of every computer can be
broken down into three parts
CPU (central processing unit).
Main Memory.
I/O (input/output) devices.
Address Bus

CPU
CU
ALU
Regist
ers

RA
M

RO
M

Print
er

Disk

Data Bus
Control Bus

Monit
or

Keybo
ard

Computer Components
Central Processing Unit (CPU)
consists of:
Control Unit (CU)
Arithmetic and Logic Unit (ALU)
Registers

Data and instructions need to get

into the system and results out
Input/output

Temporary storage of code and

results is needed
Main memory

The CPU is connected to memory and

I/O through
a group of wires called a bus.

Address bus; Data bus; Control bus.

Main Memory
RAM

stands for Random Access

Memory.

Used for temporary storage of programs while running.

RAM is volatile
Data is lost when the computer is turned off.

ROM

stands for Read Only

Memory.

Contains programs and information essential to the

operation of the computer.
ROM is nonvolatile
Information in ROM is permanent, cannot be changed
by the user, and is not lost when the power is turned
off.

System Bus
For a device (memory or I/O) to be recognized by
the CPU, it must be assigned an address.
No two devices can have the same address.
The address assigned to a given device must be unique.

The CPU puts the address (in binary) on the

address bus & a decoding circuitry finds the
device.
The CPU then uses the data bus either to get
data from that device or to send data to it.
Control buses provide device read/write signals.
To indicate the action to be done, read, write, add,
reset, etc.

Data Bus
The Data Bus
is used to
carry
information
in/out of a
CPU.

Data buses
are
bidirection
al

More buses mean a

more powerful, but
expensive CPU &
computer.

control

Decode
Decode
rr

Address

Main Memory

Bus width

An 8-bit bus can send

out 1 byte a time.

Data
CPU

Data bus width affects the

system performance

A 16-bit bus can send

out 2 bytes at a time,
twice as fast.
Data bus width can
be either 8, 16, 32, or
64 bits.

Address Bus
The address bus is used to carry the address
bits from the CPU to the devices.

The more address bits available, the

larger the number
of devices
be addressed.
The
width ofthat
the can
address
bus
determines the number of memory
locations (or devices) the CPU can
access.
Number of locations Always equal to 2x, where x

is the number of address lines

address bus width = 8 bits: Memory size = 2 8 =
265 byte
address bus width = 32 bits: Memory size = 232 =
4G byte

The address bus is unidirectional.

The CPU uses the bus only to send addresses

out.

What is an instruction set?

The
complete
collection
of
instructions
that are
understood
by a CPU
Machine
Code

Binary

Usually
represente
d by
assembly
codes

Elements of an Instruction
Operation code (Op code)
Do this
Source Operand reference
To this
Result Operand reference
Put the answer here
Next Instruction Reference
When you have done that, do this...

Simple Instructions Format

8 bits
Op-Code
ADD

16 bits

16 bits

Operand Reference
A

Operand Reference
B

16

Instruction Cycle
Two steps:
Fetch
Execute

Fetch Cycle
Program Counter (PC) holds
address of next instruction to be
fetched
CU puts the address on the
address bus and send a read
signal to memory
Memory puts the content of the
address on the data bus
CU reads the data bus and store
the content into Instruction
Register (IR).
The CU decode the instruction

Execute Cycle
The CU generates the control signals
to perform the required actions:
Processor-memory

data transfer between CPU and main memory

Processor I/O

Data transfer between CPU and I/O module

Data processing

Arithmetic or logical operation on data

Control

Alteration of sequence of operations, e.g. jump, call

Combination of above

At the end, increment PC

Unless told otherwise

Instruction Cycle - State

Instructi
Diagram
on
Incremen
t PC

address
calculati
on

Instructi
on fetch
Instructi
on
decoding

Result
store

Result
address
calculati
on

Operand
address
calculati
on
Data
operatio
n

Operand
Fetch

20

Computer Components (again)

Example of Program
ExecutionEnd of Fetch
End of Execute
Cycle
PC

30
0
30
1

1 940
5 941
2 942

30
2

LDA,
940
ADD,
941
STR,
942

20

17

Cycle
PC

IR

IR

AC

AC

MAR
MBR
PC
IR
AC
MAR

94
0

MBR

94
1

PC

94

300

IR

1 940
301
20
5 941
302
3
7
2 942

300
301
1 94
940
0

MAR

20

MBR

301
302

PC
IR

5 94
941
31
7

AC
MAR

302

MBR

2 94
942
32

PC
IR

7
22

Exercise
Consider the following simple program
is stored in memory starting from
address 500. You are required to show
the content of the IR, PC, MAR, MBR,
and the accumulator (AC) at the end of
each fetch and execute cycle.
500 1 620

LDA,
620

501 7 621

MUL,
621

502 2 622

STR,
622

23

Interrupts
Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
Program
Timer
I/O
Hardware
failure

e.g. overflow, division by zero

Generated by internal processor
timer
Used in pre-emptive multitasking
from I/O controller

e.g. memory parity error

Program Flow Control

Program Timing

Interrupt Cycle
Added to instruction cycle
Processor checks for interrupt
Indicated by an interrupt signal

If no interrupt, fetch next instruction

If interrupt pending:
Suspend execution of current program
Save context
Set PC to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted

Continue with the interrupted instruction program

Fetch

Execut
e

Check
for
Interrup
t

Execute
ISR

Transfer of Control via

Interrupts

Exercise

After the current instruction is

executed, the CPU may:

halt
fetch next instruction
check for interrupts
none of the above