Ni Sbrio-9651: System On Module

NI sbRIO-9651
System on Module
Carrier Board Design Guide
NI sbRIO-9651 System on Module Carrier Board Design Guide
August 2015
376960B-01
Support
Worldwide Technical Support and Product Information
ni.com
Worldwide Offices
Visit ni.com/niglobal to access the branch office websites, which provide up-to-date
contact information, support phone numbers, email addresses, and current events.
National Instruments Corporate Headquarters
11500 North Mopac Expressway Austin, Texas 78759-3504 USA Tel: 512 683 0100
For further support information, refer to the NI Services appendix. To comment on National
Instruments documentation, refer to the National Instruments website at ni.com/info and
enter the Info Code feedback.
20142015 National Instruments. All rights reserved.
Legal Information
Limited Warranty
This document is provided as is and is subject to being changed, without notice, in future editions. For the latest version,
refer to ni.com/manuals. NI reviews this document carefully for technical accuracy; however, NI MAKES NO EXPRESS
OR IMPLIED WARRANTIES AS TO THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND
SHALL NOT BE LIABLE FOR ANY ERRORS.
NI warrants that its hardware products will be free of defects in materials and workmanship that cause the product to fail to
substantially conform to the applicable NI published specifications for one (1) year from the date of invoice.
For a period of ninety (90) days from the date of invoice, NI warrants that (i) its software products will perform substantially
in accordance with the applicable documentation provided with the software and (ii) the software media will be free from
defects in materials and workmanship.
If NI receives notice of a defect or non-conformance during the applicable warranty period, NI will, in its discretion: (i) repair
or replace the affected product, or (ii) refund the fees paid for the affected product. Repaired or replaced Hardware will be
warranted for the remainder of the original warranty period or ninety (90) days, whichever is longer. If NI elects to repair or
replace the product, NI may use new or refurbished parts or products that are equivalent to new in performance and reliability
and are at least functionally equivalent to the original part or product.
You must obtain an RMA number from NI before returning any product to NI. NI reserves the right to charge a fee for
examining and testing Hardware not covered by the Limited Warranty.
This Limited Warranty does not apply if the defect of the product resulted from improper or inadequate maintenance,
installation, repair, or calibration (performed by a party other than NI); unauthorized modification; improper environment;
use of an improper hardware or software key; improper use or operation outside of the specification for the product; improper
voltages; accident, abuse, or neglect; or a hazard such as lightning, flood, or other act of nature.
THE REMEDIES SET FORTH ABOVE ARE EXCLUSIVE AND THE CUSTOMERS SOLE REMEDIES, AND SHALL
APPLY EVEN IF SUCH REMEDIES FAIL OF THEIR ESSENTIAL PURPOSE.
EXCEPT AS EXPRESSLY SET FORTH HEREIN, PRODUCTS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND AND NI DISCLAIMS ALL WARRANTIES, EXPRESSED OR IMPLIED, WITH RESPECT TO THE
PRODUCTS, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE OR NON-INFRINGEMENT, AND ANY WARRANTIES THAT MAY ARISE FROM
USAGE OF TRADE OR COURSE OF DEALING. NI DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
REPRESENTATIONS REGARDING THE USE OF OR THE RESULTS OF THE USE OF THE PRODUCTS IN TERMS
OF CORRECTNESS, ACCURACY, RELIABILITY, OR OTHERWISE. NI DOES NOT WARRANT THAT THE
OPERATION OF THE PRODUCTS WILL BE UNINTERRUPTED OR ERROR FREE.
In the event that you and NI have a separate signed written agreement with warranty terms covering the products, then the
warranty terms in the separate agreement shall control.
Copyright
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical,
including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the
prior written consent of National Instruments Corporation.
National Instruments respects the intellectual property of others, and we ask our users to do the same. NI software is protected
by copyright and other intellectual property laws. Where NI software may be used to reproduce software or other materials
belonging to others, you may use NI software only to reproduce materials that you may reproduce in accordance with the
terms of any applicable license or other legal restriction.
End-User License Agreements and Third-Party Legal Notices

You can find end-user license agreements (EULAs) and third-party legal notices in the following locations:
Notices are located in the <National Instruments>\_Legal Information and <National Instruments>
directories.
EULAs are located in the <National Instruments>\Shared\MDF\Legal\license directory.
Review <National Instruments>\_Legal Information.txt for information on including legal information in
installers built with NI products.
U.S. Government Restricted Rights

If you are an agency, department, or other entity of the United States Government (Government), the use, duplication,
reproduction, release, modification, disclosure or transfer of the technical data included in this manual is governed by the
Restricted Rights provisions under Federal Acquisition Regulation 52.227-14 for civilian agencies and Defense Federal
Acquisition Regulation Supplement Section 252.227-7014 and 252.227-7015 for military agencies.
Trademarks
Refer to the NI Trademarks and Logo Guidelines at ni.com/trademarks for more information on National Instruments
trademarks.
ARM, Keil, and Vision are trademarks or registered trademarks of ARM Ltd or its subsidiaries.
LEGO, the LEGO logo, WEDO, and MINDSTORMS are trademarks of the LEGO Group.
TETRIX by Pitsco is a trademark of Pitsco, Inc.
FIELDBUS FOUNDATION and FOUNDATION are trademarks of the Fieldbus Foundation.
EtherCAT is a registered trademark of and licensed by Beckhoff Automation GmbH.

CANopen is a registered Community Trademark of CAN in Automation e.V.
DeviceNet and EtherNet/IP are trademarks of ODVA.
Go!, SensorDAQ, and Vernier are registered trademarks of Vernier Software & Technology. Vernier Software & Technology
and vernier.com are trademarks or trade dress.
Xilinx is the registered trademark of Xilinx, Inc.
Taptite and Trilobular are registered trademarks of Research Engineering & Manufacturing Inc.
FireWire is the registered trademark of Apple Inc.
Linux is the registered trademark of Linus Torvalds in the U.S. and other countries.
Handle Graphics, MATLAB, Real-Time Workshop, Simulink, Stateflow, and xPC TargetBox are registered
trademarks, and TargetBox and Target Language Compiler are trademarks of The MathWorks, Inc.
Tektronix, Tek, and Tektronix, Enabling Technology are registered trademarks of Tektronix, Inc.
The Bluetooth word mark is a registered trademark owned by the Bluetooth SIG, Inc.
The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is under
license.
The mark LabWindows is used under a license from Microsoft Corporation. Windows is a registered trademark of Microsoft
Corporation in the United States and other countries.
Other product and company names mentioned herein are trademarks or trade names of their respective companies.
Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments
and have no agency, partnership, or joint-venture relationship with National Instruments.
Patents
For patents covering National Instruments products/technology, refer to the appropriate location: HelpPatents in your
software, the patents.txt file on your media, or the National Instruments Patent Notice at ni.com/patents.
Export Compliance Information

Refer to the Export Compliance Information at ni.com/legal/export-compliance for the National Instruments global
trade compliance policy and how to obtain relevant HTS codes, ECCNs, and other import/export data.
WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

YOU ARE ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY AND
RELIABILITY OF THE PRODUCTS WHENEVER THE PRODUCTS ARE INCORPORATED IN YOUR SYSTEM OR
APPLICATION, INCLUDING THE APPROPRIATE DESIGN, PROCESS, AND SAFETY LEVEL OF SUCH SYSTEM
OR APPLICATION.
PRODUCTS ARE NOT DESIGNED, MANUFACTURED, OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL
SYSTEMS, HAZARDOUS ENVIRONMENTS OR ANY OTHER ENVIRONMENTS REQUIRING FAIL-SAFE
PERFORMANCE, INCLUDING IN THE OPERATION OF NUCLEAR FACILITIES; AIRCRAFT NAVIGATION; AIR
TRAFFIC CONTROL SYSTEMS; LIFE SAVING OR LIFE SUSTAINING SYSTEMS OR SUCH OTHER MEDICAL
DEVICES; OR ANY OTHER APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD
LEAD TO DEATH, PERSONAL INJURY, SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM
(COLLECTIVELY, HIGH-RISK USES). FURTHER, PRUDENT STEPS MUST BE TAKEN TO PROTECT AGAINST
FAILURES, INCLUDING PROVIDING BACK-UP AND SHUT-DOWN MECHANISMS. NI EXPRESSLY DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH-RISK
USES.
Contents
About This Document
Terminology ..................................................................................................................... ix
Schematic Conventions .................................................................................................... xi
Additional Documentation Resources .............................................................................. xii
Chapter 1
Fixed Behavior Signals
Primary Ethernet (GBE0) ................................................................................................. 1-1
GBE0 Signal Definitions .......................................................................................... 1-2
GBE0 Implementation on the Reference Carrier Board........................................... 1-2
Gigabit Ethernet Magnetic Requirements ................................................................ 1-3
GBE0 Routing Considerations ................................................................................. 1-4
USB (USB0, USB1) ......................................................................................................... 1-4
USB0 Host/Device Signal Definitions ..................................................................... 1-5
USB0 Device Implementation on the Reference Carrier Board............................... 1-6
USB1 Host Signal Definitions.................................................................................. 1-8
USB1 Host Implementation on the Reference Carrier Board .................................. 1-8
Supporting Onboard USB Devices........................................................................... 1-10
USB Routing Considerations.................................................................................... 1-10
UART/Console Out (Serial1) ........................................................................................... 1-10
Serial1 Signal Definitions......................................................................................... 1-10
Serial1 Implementation on the Reference Carrier Board ......................................... 1-11
Adding Flow Control and Modem Control Signals.................................................. 1-12
SD Card ............................................................................................................................ 1-13
SD Signal Definitions............................................................................................... 1-13
SD Implementation on the Reference Carrier Board................................................ 1-14
SD Routing Considerations ...................................................................................... 1-16
RTC Battery (VBAT) ....................................................................................................... 1-16
VBAT Signal Definitions ......................................................................................... 1-17
VBAT Implementation on the Reference Carrier Board.......................................... 1-17
Eliminating the Effects of Contact Bounce .............................................................. 1-17
Resets................................................................................................................................ 1-18
Reset Signal Definitions ........................................................................................... 1-18
Reset Implementation on the Reference Carrier Board............................................ 1-19
Status LED........................................................................................................................ 1-19
Status LED Signal Definitions ................................................................................. 1-19
Status LED Implementation on the Reference Carrier Board .................................. 1-20
FPGA Config.................................................................................................................... 1-21
FPGA Config Signal Definitions.............................................................................. 1-21
FPGA Config Implementation on the Reference Carrier Board .............................. 1-21
Temp Alert........................................................................................................................ 1-21
Temp Alert Signal Definitions ................................................................................. 1-22
Temp Alert Implementation on the Reference Carrier Board .................................. 1-22
National Instruments
Contents
Chapter 2
User-Defined FPGA Signals
Secondary Ethernet (GBE1) ............................................................................................. 2-1
GBE1 Signal Definitions on the Reference Carrier Board ....................................... 2-2
GBE1 Reference Schematic...................................................................................... 2-4
GBE1 Routing Considerations.................................................................................. 2-8
Additional RS-232 (Serial2, Serial3, Serial4) .................................................................. 2-8
Serial2 Signal Definitions on the Reference Carrier Board...................................... 2-8
Serial2 Reference Schematic .................................................................................... 2-10
RS-485 (Serial5, Serial6) .................................................................................................. 2-11
Serial5 Definitions on the Reference Carrier Board ................................................. 2-11
Serial5 Reference Schematic .................................................................................... 2-12
RS-485 Layout Considerations ................................................................................. 2-13
CAN (CAN0, CAN1) ....................................................................................................... 2-13
CAN0 Signal Definitions on the Reference Carrier Board....................................... 2-14
CAN0 Reference Schematic ..................................................................................... 2-15
Termination Resistors for CAN Cables .................................................................... 2-17
Chapter 3
Carrier Board PCB Layout Guidelines
Impedance-Controlled Signaling ...................................................................................... 3-1
Single-Ended Signal Best Practices .................................................................................. 3-2
Differential Signal Best Practices ..................................................................................... 3-2
Ground and Power Plane Recommendations.................................................................... 3-3
Fanout and Layout Options............................................................................................... 3-3
Chapter 4
Mechanical Considerations
Mounting........................................................................................................................... 4-1
Selecting an Appropriate Mating Connector ............................................................ 4-1
Selecting Appropriate Standoffs ............................................................................... 4-2
Mounting Direction Options..................................................................................... 4-4
Managing Thermal Conditions ......................................................................................... 4-6
Designing a Suitable Enclosure ................................................................................ 4-7
Understanding Thermal Specifications..................................................................... 4-7
Validating the System ....................................................................................................... 4-9
Validating Temperature Measurements.................................................................... 4-9
Managing Power and Feature Utilization ................................................................. 4-10
Mounting Recommendations for Maximizing Thermal Performance......................4-11
Additional Resources for Managing Thermal Conditions ........................................ 4-12
Shock and Vibration ......................................................................................................... 4-12
vi
ni.com
Appendix A
Reference Carrier Board Specifications and User Guide
Parts Locator Diagram and Block Diagram ..................................................................... A-1
Specifications.................................................................................................................... A-1
Ethernet..................................................................................................................... A-2
Serial......................................................................................................................... A-2
CAN.......................................................................................................................... A-2
SD Card .................................................................................................................... A-2
USB .......................................................................................................................... A-2
Pmod......................................................................................................................... A-2
RTC Battery.............................................................................................................. A-4
Support Signals......................................................................................................... A-4
Connector Pinouts............................................................................................................. A-4
RS-232, RS-485, and CAN Connector Pinouts........................................................ A-4
Pmod 12-Pin Connector Pinout ................................................................................ A-5
Pmod I2C Connector Pinout ..................................................................................... A-6
Environmental Management............................................................................................. A-6
Appendix B
Revision History
Appendix C
NI Services
vii
About This Document

The NI sbRIO-9651 System on Module (SOM) provides an embedded real-time processor and
reconfigurable FPGA. The sbRIO-9651 SOM requires a user-designed carrier board to provide
power and I/O interfaces. You can optimize the carrier board to implement the exact functions
your application requires. You can design the carrier board size and connector locations to fit the
packaging or enclosure of your specific system.
This document provides detailed information about carrier board design techniques, guidelines,
and requirements.
Refer to the documents listed in the Additional Documentation Resources
section of this chapter for more information as you design, prototype, and implement
your sbRIO-9651 SOM application. In particular, refer to the NI sbRIO-9651 System
on Module OEM Device Specifications for dimensions, pinout information,
functional specifications, and electrical specifications for the sbRIO-9651 SOM.
Note
Terminology
Table 1 defines terms used in this document to describe sbRIO-9651 SOM concepts and
technology.
Table 1. sbRIO-9651 SOM Terminology in This Document
Term
Definition
System Components
J1
Molex 45971-4185 320-pin, 8 40 position, SEARAY

open-pin-field-array connector on the sbRIO-9651 SOM.
SEARAY
Connector family used for the J1 connector on the sbRIO-9651 SOM.

Manufactured by Samtec and Molex.
SOM
System on Module.
SoC
System on Chip.
USB Device
Physical, electrical, addressable, and logical entity that is attached to

USB and performs a function.
USB Device port
Port on a carrier board that provides a USB Device interface to the SOM.
USB Host
USB interface that controls the bus and communicates with connected
USB devices.
USB Host port
Port on a carrier board that provides a USB Host interface from the SOM.
ix
About This Document
Table 1. sbRIO-9651 SOM Terminology in This Document (Continued)

Term
Definition
Reference Schematic and Signal Naming
LVTTL
In compliance with the Low-Voltage Transistor-Transistor Logic

(LVTTL) specification.
LVCMOS
In compliance with the Low-Voltage Complementary Metal Oxide

Semiconductor (LVCMOS) specification.
PUDC
Pull-up During Configuration

Mechanical
CPU/FPGA
temperature
The temperature reported digitally by a sensor that measures the die

junction temperature of the Xilinx Zynq SoC.
Primary System
temperature
The temperature reported digitally by a sensor on the Xilinx Zynq SoC

side of the circuit card assembly underneath the integrated heat
spreader. This value is an approximation of the local ambient
temperature inside the heat spreader.
Secondary System
temperature
The temperature reported digitally by a sensor on the SEARAY side

of the circuit card assembly. This value is a conservative
approximation of the local ambient temperature on that side of the
circuit card assembly.
ni.com
Schematic Conventions
Table 2 describes symbol conventions used in the I/O interface schematic diagrams in this
document.
Table 2. Schematic Conventions in This Document
Symbol
Description
Off-page symbol that represents communication to and from the mating

connector.
Off-page symbol that represents communication from the mating
connector.
Off-page symbol that represents communication to the mating connector.
On-page symbol that represents the signal being driven.
On-page symbol that represents the signal being received.
Power supply rail.
Analog ground.
I
Digital ground.
Chassis ground.
SPARE
Refers to an unpopulated reference designator.
xi
About This Document
Additional Documentation Resources

Refer to the following additional resources as you design, prototype, and implement your
sbRIO-9651 SOM application.
What Would You Like to

Learn More About?
Resources
NI sbRIO-9651
System on Module OEM Device
NI sbRIO-9651 System on Module

OEM Device Specifications
NI sbRIO-9651
System on Module Development Kit

Development Kit Quick Start Guide
Designing a carrier board

for your application

Carrier Board Design Guide
Adding an sbRIO-9651
System on Module target in LabVIEW
LabVIEW Help (NI-RIO)
Creating a socketed CLIP that defines the

I/O configuration to use in your application
NI Single-Board RIO CLIP

Generator Help
NI Training and Support
ni.com/singleboard/setup
ni.com/training
ni.com/support
PDF available online at ni.com/manuals
xii
ni.com
Help file available locally
Included in the shipping kit
Availability
Available online at ni.com
A subset of pins on the J1 connector on the sbRIO-9651 SOM are dedicated to implementing the
following specific I/O functionality:
Primary Ethernet (GBE0)
USB Host/Device (USB0)
USB Host (USB1)
UART/Console Out (Serial1)
SD Card
Other pins on the J1 connector are dedicated to implementing the following support signals:
RTC Battery (VBAT)
Resets
Status LED
FPGA Config
Temp Alert
Refer to the NI sbRIO-9651 System on Module OEM Device Specifications
for a complete list of all pins and signals on the J1 connector.
Note
The reference carrier board included with the sbRIO-9651 SOM development kit demonstrates
how to implement each of these signals. Refer to the specific sections in this chapter for more
information about how the reference carrier board implements each signal.
Primary Ethernet (GBE0)

The sbRIO-9651 SOM provides a primary Gigabit Ethernet port (GBE0) for use on a carrier
board. Refer to the Secondary Ethernet (GBE1) section of Chapter 2, User-Defined FPGA
Signals, for information about implementing a secondary Gigabit Ethernet port.
1-1
Chapter 1
GBE0 Signal Definitions

Table 1-1 describes the GBE0 port pins and signals on the J1 connector on the
sbRIO-9651 SOM.
Table 1-1. GBE0 Signal Definitions
Dedicated
SOM Pin #
Signal Name
Direction*
I/O Standard
Description
Defined by
Ethernet PHY
specification.
Pre-magnetic
Gigabit Ethernet
data pairs.
GBE0_MDI0_P
GBE0_MDI0_N
GBE0_MDI1_P
GBE0_MDI1_N
GBE0_MDI2_P
GBE0_MDI2_N
GBE0_MDI3_P
GBE0_MDI3_N
1
9
18
26
3
11
20
28
I/O
GBE0_SPEED_LEDg
GBE0_SPEED_LEDy
5
13
LVTTL
Speed LED signals.
GBE0_ACT_LEDg
LVTTL
Activity/link LED
signal.
I/O direction is with respect to the sbRIO-9651 SOM.
GBE0 Implementation on the Reference Carrier Board

Figure 1-1 shows a schematic design for the GBE0 implementation on the reference carrier
board.
Figure 1-1. GBE0 Reference Schematic
J3
GBE0_MDIO_P
GBE0_MDIO_N
GBE0_MDI1_P
GBE0_MDI1_N
GBE0_MDI2_P
GBE0_MDI2_N
GBE0_MDI3_P
GBE0_MDI3_N
2
2
2
2
2
2
2
2
11
10
4
5
3
2
8
9
12
6
1
7
1
2
C7
1
0.1UF
10%
16V 2
C8
1
0.1UF
10%
16V 2
C2
1
0.1UF
10%
16V 2
13
14
15
16
C4
0.1UF
10%
16V
MDIA_P
MDIA_N~
MDIB_P
MDIB_N~
MDIC_P
MDIC_N~
MDID_P
MDID_N~
MCTA
MCTB
MCTC
MCTD
17
SHIELD1
18
SHIELD2
LED1(GRN-CATH)
LED1(GRN-AN)
LED2(GRN-CATH/YEL-AN)
LED2(GRN-AN/YEL-CATH)
08261K1T-43-F
GBE0_ACT_LEDg
R5
475 1%
1/16 W
GBE0_SPEED_LEDy
GBE0_SPEED_LEDg
R6
475 1%
1/16 W
1-2
ni.com
Reference Schematic Design Considerations

Table 1-2 lists design considerations for the schematic shown in Figure 1-1.
Table 1-2. GBE0 Reference Schematic Design Considerations
Consideration
Notes
MDI data pairs
The MDI data pairs are routed differentially and connected directly to
the Ethernet connector.
The Ethernet connector has the required Ethernet magnetics built into
it. You may use discrete magnetics instead.
LED signals
The LED signals can be used to directly drive connector LEDs.

The current-limiting resistors must be sized so that the drive current of
the LED signals is not exceeded.
Refer to the Ethernet Speed LED Behavior section of the
NI sbRIO-9651 System on Module OEM Device Specifications for
information about Ethernet LED signal behavior and rated drive
current.
Gigabit Ethernet Magnetic Requirements

The Ethernet PHY on the sbRIO-9651 SOM uses voltage-mode drivers for the MDI pairs, which
greatly reduces the power that the magnetics consume and eliminates the need for a sensitive
center tap power supply.
You must consider the following requirements for connecting center taps:
Do not connect the center taps of the isolation transformer on the MDI pair side to any
power source. Keep the center taps separate from each other.
Connect each center tap through separate 0.1 F capacitors to ground. The separation is
required because the common-mode voltage on each MDI pair might be different.
Table 1-3 lists recommended magnetic characteristics.

Table 1-3. Recommended Magnetic Characteristics
Parameter
Turns ratio
Value
Test Condition
1 CT : 1 CT
Open-circuit inductance
(min)
350 H
100 mV, 100kHz, 8 mA
Insertion loss (max)
1.0 dB
0 MHz to 100 MHz
HIPOT (min)
1500 Vrms
1-3
Chapter 1
The sbRIO-9651 SOM development kit uses the Gigabit Ethernet connector parts described in
Table 1-4.
Table 1-4. Gigabit Ethernet Connector Parts
Part
Manufacturer
Part Number
sbRIO-9651 SOM PHY
Micrel
KSZ9031MNXIA
Reference carrier board

Gigabit Ethernet connector
Bel Stewart Magjack
0826-1K1T-43-F
Refer to the datasheet for the Micrel Ethernet PHY for more information about magnetic
requirements.
GBE0 Routing Considerations

NI recommends the following design practices for properly routing GBE0 signals on your carrier
board:
Route MDI pairs differentially with 100 differential trace impedance.
Length-match the positive and negative signal for each MDI data pair to within 10 mils.
Limit the MDI trace lengths on the carrier board to 6.0 in. or less, which is the length at
which Ethernet compliance was tested.
USB (USB0, USB1)

The sbRIO-9651 SOM provides two USB 2.0-compliant ports for use on a carrier board:
USB Host/Device port (USB0) and USB Host port (USB1).
Note Your carrier board design must provide the 5 V USB_VBUS power to USB
Host ports and must limit the current supplied to each host port according to USB
specifications.
1-4
ni.com
USB0 Host/Device Signal Definitions

Table 1-5 describes the USB0 Host/Device port pins and signals on the sbRIO-9651 SOM
connector.
Table 1-5. USB0 Host/Device Signal Definitions
Dedicated
SOM Pin #
Direction*
I/O Standard
USB0_DP
33
I/O
USB0 data pair.
USB0_DN
41
Defined by
USB
specification.
USB0_MODE
65
LVTTL
Controls whether the

USB0 port provides a
Host or Device
connection. Refer to the
Configuring the USB0
Mode section of this
chapter for more
information.
USB0_CPEN
73
LVTTL
USB0 over-current
protection enable.
USB0_VBUS
81
5 V tolerant
voltage sense
USB0 VBUS input.

Allows USB PHY to
sense if VBUS is
present on the
connector.
Signal Name
Description
1-5
Chapter 1
Configuring the USB0 Mode

You can configure the USB0 interface to be a USB Host port or a USB Device port, as shown
in Table 1-6. This mode is set when the system boots and does not change dynamically. The
reference carrier board uses the USB0 interface for a USB Device port.
Note
USB On-The-Go (OTG) is not supported.
Table 1-6. Configuring the USB0 Mode
Mode
How to Enable
USB Host
Connect the USB0_MODE signal to digital ground on your carrier

board. You can implement USB0 Host functionality in the same way that
the USB1 Host signal is implemented on the reference carrier board, as
described in the USB1 Host Implementation on the Reference Carrier
Board section of this chapter.
USB Device
Connect the USB0_MODE signal to the VCC_3V3 rail on your carrier

board. Refer to the USB0 Device Implementation on the Reference
Carrier Board section of this chapter for more information about the
USB0 Device implementation on the reference carrier board.
USB0 Device Implementation on the Reference Carrier

Board
Figure 1-2 shows a schematic design for the USB0 Device implementation on the reference
carrier board.
Figure 1-2. USB0 Device Reference Schematic
1
R78
0 5%
1/16W
USB0_DN
USB0_DP
These lines can swap

if layout is easier
+3.3V
Population Options
For EMC/EMI
L2
2
2
1 D+
2 D
DLW21S_900
Not Populated
U17
TPD2EUSB30
1 R76 2
0, 5%
1/16 W
USB0_VBUS
2 1
R66
1K
0.5%
3 GND
2
1
2
C32
1
1.0 UF
10% 2
16 V
1
2
3
4
C33
0.1 UF
10%
16 V
1
R61
Spare
R0603
1-6
| ni.com
J8
VBUS
D
D+
GND
5 SHLD1
6 SHLD2
CONN-USB,B,HIGH_RETENTION
USB0_MODE
Pulled Up To Select Usb Device Port
C204
1
0.1 UF 10%
50 V

Table 1-7. USB0 Device Reference Schematic Design Considerations
Consideration
USB data pair
Notes
The USB0_DP and USB0_DN data pair is routed differentially to the

USB connector.
On the reference carrier board, the L2 common-mode choke is not
populated, but you can populate it in your design to help with
conducted immunity or emissions.
If you choose to populate L2, remove R76 and R78 from your design.
If your design does not include a common-mode choke, you can route
the USB pair directly from the USB connector to the sbRIO-9651
SOM connector.
U17 provides ESD protection to the USB data pair and should be
placed close to the USB connector.
USB0_MODE
The USB0_MODE signal is pulled up to 3.3 V to select USB Device

functionality.
USB0_CPEN
Leave the USB0_CPEN signal disconnected for a USB Device port.
USB0_VBUS
For the USB Device port to function properly, the USB0_VBUS signal
must be connected to the VBUS pin on the USB connector.
This is a low-current, voltage-sense connection.
In layout, you can treat this connection as a data signal.
R66 helps provide some overvoltage protection on USB0_VBUS and
should be placed close to the USB connector. NI recommends that you
use a 1 k resistor.
1-7
Chapter 1
USB1 Host Signal Definitions

Table 1-8 describes the USB1 Host port pins and signals on the sbRIO-9651 SOM connector.
Table 1-8. USB1 Host Signal Definitions
Dedicated
SOM Pin #
Direction*
USB1_DP
35
I/O
USB1_DN
43
USB1_CPEN
50
USB1_VBUS
58
Signal Name
I/O
Standard
Description
Defined by
USB
specification.
USB1 data pair.
LVTTL
USB1 over-current
protection enable.
5 V tolerant
voltage sense
USB1 VBUS input.

Allows USB PHY to
sense if VBUS is present
on the connector.
USB1 Host Implementation on the Reference Carrier

Board
Figure 1-3 shows a schematic design for the USB1 Host implementation on the reference carrier
board.
Figure 1-3. USB1 Host Reference Schematic
R82
0 5%
1/16 W
These lines can swap

if layout is easier
POPULATION OPTIONS
FOR EMC/EMI
USB1_DN
USB1_DP
USB1_VBUS
L3
U18
TPD2EUSB30
2
3
DLW21S_900
NOT POPULATED
+5 V
+5 V
1
2
R92
1k
0.5%
C57
0.1 UF
10%
16 V
R79
1
1
2
2
1
2
D+
D
0 5%
1/16 W
R86
4.7 K
0.5%
1/16 W
3 GND
U20
6
USB1_CPEN
2
1
R85
4.7 K
0.5%
1/16 W
IN
J10
OUT
EN
ILIM
FAULT~
GND
PAD
1
2
3
4
3
5
7
TPS2553
R89
23.2 K
0.5%
1/16 W
1
C67
100 UF
6.3 V
20% 2
C62
22 UF
25 V
10%
1
C61
0.01 UF
100 V
10%
2
C203
0.1 UF 10%
50 V
1-8
| ni.com
R93
1K
.5%
5
6
VCC
DAT1
+DAT1
GND
SHLD1
SHLD2
USB_A

Table 1-9. USB1 Host Reference Schematic Design Considerations
Consideration
USB data pair
Notes
The USB1_DP and USB1_DN data pair is routed differentially to

the USB connector.
On the reference carrier board, the L3 common-mode choke is not
populated, but you can populate it in your design to help with
conducted immunity or emissions.
If you choose to populate L3, remove R79 and R82 from your
design.
If your design does not include a common-mode choke, you can
route the USB pair directly from the USB connector to the
sbRIO-9651 SOM connector.
U18 provides ESD protection to the USB data pair and should be
placed close to the USB connector.
USB1_CPEN
The USB1_CPEN signal must be connected to the enable of the

VBUS current limit switch (U20). This allows the sbRIO-9651 SOM
to power-cycle USB devices when the processor is reset.
USB1_VBUS
For the USB Host port to function properly, the USB1_VBUS

signal must be connected to VBUS on the USB connector.
This is a low-current, voltage-sense connection.
In layout, you can treat the trace after R92 going to the sbRIO-9651
SOM connector as a data signal.
R92 helps provide some overvoltage protection on USB1_VBUS
and should be placed close to the USB connector. NI recommends
that you use a 1 k resistor.
The carrier board must provide 5 V VBUS power for the USB Host
port.
A current limit switch is required between the 5 V rail and the USB
connector.
U20 is the current limiter.
NI recommends that you provide 100 F of capacitance on the
VBUS rail.
1-9
Chapter 1
Supporting Onboard USB Devices

When you implement a USB device directly on your carrier board, you can connect the device
to a USB Host port from the sbRIO-9651 SOM. For this case, use the following design
guidelines:
You can connect the USB data pair directly to a USB device on your carrier board.
A current limiter is not required.
Use the CARRIER_RST# signal to reset the USB device when the sbRIO-9651 SOM is in
reset.
Tie the USBx_VBUS signal to 3.3 V or 5 V.
USB Routing Considerations

NI recommends the following design practices for properly routing USB signals on your carrier
board:
Route the USBx_DP and USBx_DN signals as differential pairs with 90 differential
impedance.
Length-match the positive and negative signal for each USB data pair to within 10 mils.
Limit the USBx_DP and USBx_DN trace lengths on the carrier board to 8.0 in. or less,
which is the length at which USB compliance was tested.
UART/Console Out (Serial1)

The sbRIO-9651 SOM provides a dedicated UART (Serial1) interface for use on a carrier board.
This interface also functions as an operating system console when Console Out is enabled. Refer
to the Additional RS-232 (Serial2, Serial3, Serial4) and RS-485 (Serial5, Serial6) sections of
Chapter 2, User-Defined FPGA Signals, for information about implementing additional serial
ports.
Serial1 Signal Definitions

Table 1-10 describes the Serial1 port pins and signals on the sbRIO-9651 SOM connector.
Note The NI-Serial driver has been developed for and tested with the Texas
Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be
compatible.
1-10
ni.com
Table 1-10. Serial1 Signal Definitions

Dedicated
SOM Pin #
Direction*
SERIAL1_TX
52
SERIAL1_RX
60
Signal Name
I/O
Standard
Description
LVTTL
Two-wire serial and

console out signals for
the sbRIO-9651 SOM.
Serial1 Implementation on the Reference Carrier Board

Figure 1-4 shows a schematic design for the Serial1 implementation on the reference carrier
board.
Figure 1-4. Serial1 Reference Schematic
+3.3 V
SERIAL1_RX
+3.3 V
R122
SPARE
R0402
R124
4.7 K
0.5%
1/16 W
C189
0.1 UF
10%
16 V
1
2
C190
0.1 UF
10%
16 V
U24
4 DIN1
DOUT1
5 DIN2
DOUT2
7 DIN3
DOUT3
14 ROUT1
RIN1
13 ROUT2
RIN2
12 ROUT3
RIN3
11 ROUT4
RIN4
10 ROUT5
RIN5
9
VCC
FORCEON
28
FORCEOFF~
GND
6 INVALID~
THERMALPAD
8
NC1
NC3
16 NC
NC4
30
J15
DSUB9-761918-A
25
23
22
21
20
19
18
17
SERIAL1_TX_F#
R116
SERIAL1_TX_CONN#
0 5%
1/16 W
1 R115 2
SERIAL1_RX_F#
+3.3 V
27
26
33
24
32
5
9
4
8
3
7
2
6
1
0 5%
1/16 W
C188
0.1 UF
10%
16 V
SERIAL1_RX_CONN#
1
C94
V+
15 VL
29
C1+
31
C11 C2+
2 C2-
0.1 UF 10%
50 V
1 R123 2
39 0.5%
1/16 W
+3.3 V
FPGA_CFG
C111
SERIAL1_TX
C187
10%
0.1 UF
16 V
0.1 UF 10%
50 V
1
R125
1K
0.5%
+3.3 V
C107
10
11
C1206, SPARE
1
C99
C1206, SPARE
TRS3253EIRSMR
2, 4
1
R121
4.7 K
0.5%
1/16 W
C106
0.1 UF 10%
50 V
1-11
Chapter 1

Table 1-11. Serial1 Reference Schematic Design Considerations
Consideration
Notes
Interface
The reference carrier board demonstrates how to use the Serial1 interface
to implement a two-wire RS-232 serial port.
Serial
transceiver
U24 is the RS-232 serial transceiver that converts between RS-232 and
LVTTL signal levels. To minimize the impact of higher voltage signals
on your carrier board, place the serial transceiver near the RS-232
connector.
Series
termination
R123 is the series termination for SERIAL1_RX. Use series termination

at the serial transceiver on all signals being driven to the sbRIO-9651
SOM. The sbRIO-9651 SOM provides onboard series termination for
SERIAL1_TX near the Xilinx Zynq SoC.
FPGA
All serial port signals pass through the FPGA on the sbRIO-9651 SOM.
The FPGA_CFG signal is used to disable the serial transceiver when the
FPGA is not configured. Disabling the transceiver in this way prevents
any unwanted glitches on the RS-232 port.
Adding Flow Control and Modem Control Signals

You can use the sbRIO CLIP Generator application included with the NI-RIO Device Drivers
software to add optional flow control and modem control signals to the Serial1 interface.
Refer to the Additional RS-232 (Serial2, Serial3, Serial4) section of Chapter 2, User-Defined
FPGA Signals, for an example of how to implement a full-modem RS-232 port. Refer to the
NI Single-Board RIO CLIP Generator Help, described in the Additional Documentation
Resources section of the About This Document preface, for more information about using the
sbRIO CLIP Generator application.
1-12
ni.com
SD Card
The sbRIO-9651 SOM provides a Secure Digital (SD) Card interface for use on a carrier board.
This interface supports SD and SDHC cards. You can implement this interface with standard SD
or microSD card connectors. The maximum supported SDHC card capacity is 32 GB.
SD Signal Definitions
Table 1-12 describes the SD pins and signals on the sbRIO-9651 SOM connector.
Table 1-12. SD Signal Definitions
Dedicated
SOM Pin #
Direction*
SD_CLK
15
LVTTL
SD clock.
SD_CMD
31
I/O
LVTTL
SD command.
SD_D0
SD_D1
SD_D2
SD_D3
8
22
24
30
I/O
LVTTL
SD data bus.
SD_CD#
32
LVTTL
SD card detect. Assert

low when card is present.
Can connect to a
mechanical switch in the
SD card socket.
SD_WP
40
LVTTL
SD write protect. Assert

high to enable protection.
Can connect to a
mechanical switch in the
SD card socket.
SD_PWR_EN
38
LVTTL
Power enable for SD card

socket.
Signal Name
I/O
Standard
Description
1-13
Chapter 1
SD Implementation on the Reference Carrier Board

Figure 1-5 shows a schematic design for the SD implementation on the reference carrier board.
Figure 1-5. SD Reference Schematic
+3.3V
0 5%
1/16 W
U9
+3.3 V
4
3
2
1
2
C144
10%
0.1 UF
16 V
EN
OC#
INS1
INS2
GND
OUTD1
OUTD2
OUTD3
SD_OC#
VOUT_SD
6
7
8
TPS2030D
SD_D3
SD_D2
R14
4.7 K
0.5%
1/16 W
R211
C12 1
10 UF
10%
10 V 2
24.9 0.5%
1/16 W
R212
1
2
C13
0.1 UF
10%
16 V
1
R21
1K
0.5%
2
J2
4
1
9
8
7
24.9 0.5%
1/16 W
SD_D1
R213
SD_CLK
24.9 0.5%
1/16 W
SD_D0
R214
R215
+3.3V
1
2
R198
1K
0.5%
24.9 0.5%
1/16 W
SD_CD#
R216
5
2
CD/D3
D2
D1
D0
CLK
CMD
SD SOCKET
10
24.9 0.5%
1/16 W
SD_CMD
Vdd
CardDetect
Common
12
WP
11
3
6
Shield1
SD_PWR_EN
R38
Vss1
Vss2
CONN9-764432-01-RA 13
2
2
68.1 0.5%
1/16 W
+3.3V
C205
1
1
R199
1K
0.5%
SD_WP
R217
68.1 .5%
1/16 W
1-14
ni.com
2
2
0.1UF 10%
50 V

Table 1-13. SD Reference Schematic Design Considerations
Consideration
Notes
SD_CLK,
SD_CMD, and
SD_D0 through
SD_D3
You can route these signals directly from the sbRIO-9651 SOM to the
SD connector.
Each of these signals requires series termination near its driver. The
sbRIO-9651 SOM provides series termination near the Xilinx Zynq
SoC to prevent overshoot on the SD card when the sbRIO-9651 SOM
drives these signals. The bi-directional signals also require series
termination at the SD converter.
Use series termination at the SD connector for the SD_CMD and
SD_D0 through SD_D3 signals to prevent overshoot on the
sbRIO-9651 SOM when the SD card drives these signals.
SD_CD#
The SD_CD# signal is connected to the mechanical card-detect switch

in the SD connector.
When a card is inserted, the card-detect pin on the SD connector is
shorted to ground.
Because this is a mechanical switch with low output impedance, you
must place a series termination resistor (R216) at the SD connector.
You must have a card-detect switch to properly support hot-swapping
cards. If you do not need to support hot-swapping cards, you can use
an SD connector without a card-detect switch. In this case, tie the
SD_CD# signal to ground so that the sbRIO-9651 SOM attempts to
initialize a card on boot.
1-15
Chapter 1
Table 1-13. SD Reference Schematic Design Considerations (Continued)

Consideration
SD_WP
Notes
When the SD_WP signal is asserted high, the sbRIO-9651 will not
write to the SD card.
Standard-size SD card connectors provide a mechanical write-protect
switch that you can connect to the SD_WP signal. The switch detects
the position of the lock slide on the SD card.
Because this is a mechanical switch with low output impedance, you
must place a series termination resistor (R217) at the SD connector.
If you are using a microSD connector or do not have a write-protect
switch, you can tie the SD_WP signal to ground in order to disable
write protection and allow changes to the SD card.
SD_PWR_EN
Use the SD_PWR_EN signal to gate power to the SD connector.

U9 acts as a power switch and current limiter for the SD interface.
SDHC cards must not draw more than 200 mA.
The SD_PWR_EN signal controls when power is going to the SD card.
The SD_PWR_EN signal asserts high when a card is detected using
the SD_CD# signal. The SD_PWR_EN signal deasserts when a card is
not present.
SD Routing Considerations
NI recommends the following design practices for properly routing SD signals on your carrier
board:
Length-match the SD_CMD and SD_D0 through SD_D3 signals to within 250 mils of
SD_CLK.
Limit the trace length of the SD_CLK, SD_CMD, and SD_D0 through SD_D3 signals on
the carrier board to 8.0 in. or less.
RTC Battery (VBAT)

The reference carrier board contains a lithium cell battery that maintains the real-time
clock (RTC) on the sbRIO-9651 SOM when the sbRIO-9651 SOM is powered off. A slight drain
on the battery occurs when power is not applied to the sbRIO-9651 SOM. For information about
the VBAT current drain, refer to the VBAT Requirements section of the NI sbRIO-9651 System
on Module OEM Device Specifications.
If the battery is dead, or if no voltage has been applied to the VBAT pins, the system still starts
but the system clock resets to the UNIX epoch date and time.
1-16
ni.com
VBAT Signal Definitions

Table 1-14 describes the VBAT pins and signals on the sbRIO-9651 SOM connector.
Table 1-14. VBAT Signal Definitions
Signal Name
VBAT
Dedicated
SOM Pin #
Direction*
I/O Standard
64
Power rail
Description
RTC battery input that

provides backup power to
the RTC to keep track of
absolute time.
VBAT Implementation on the Reference Carrier Board

Figure 1-6 shows a schematic design for the VBAT implementation on the reference carrier
board.
Figure 1-6. VBAT Reference Schematic
2
BTH1
BATHLDR-747921-01
VBAT
Use Br1225
Battery In
This Holder

You can directly connect the battery to VBAT. The sbRIO-9651 SOM already provides a
current-limiting resistor and reverse-voltage protection.
Eliminating the Effects of Contact Bounce

If you are using the A revision of the sbRIO-9651 SOM, it is important to eliminate the effects
of contact bounce when you initially attach the battery.
To determine the revision, check the bottom side of the sbRIO-9651 SOM for
a sticker with the part number 157660x-01L, where x is the revision letter.
Note
Contact bounce can cause a momentary power interruption to the RTC, which might result in
drift greater than the RTC accuracy listed in the NI sbRIO-9651 System on Module OEM Device
Specifications.
1-17
Chapter 1
To eliminate the effects of contact bounce, try one of the following methods:
(Preferred) Use power sequencing by applying Vcc to the RTC before attaching the battery.
Filter the signal using a small capacitor between VBAT and ground. The manufacturer
recommends capacitor values between 0.1 nf and 1.0 nf.
Resets
The sbRIO-9651 SOM provides signals for implementing a reset button on a carrier board and
indicating that the sbRIO-9651 SOM is in reset.
Reset Signal Definitions

Table 1-15 describes the Reset pins and signals on the sbRIO-9651 SOM connector.
Table 1-15. Reset Signal Definitions
Signal Name
Dedicated
SOM Pin #
Direction*
I/O
Standard
CARRIER_RST#
37
LVTTL
Reset that indicates that

main power is not
adequate or that the
sbRIO-9651 SOM is in
reset. Asserted low.
SYS_RST#
47
LVTTL
System reset that puts

the sbRIO-9651 SOM
in reset. Asserted low.
Description
Asserting this signal

causes the
CARRIER_RST#
signal to also assert.
You can also assert this
signal to put the
sbRIO-9651 SOM into
safe mode or reset
IP address settings.
*
1-18
ni.com
Reset Implementation on the Reference Carrier Board

Figure 1-7 shows a schematic design for the Reset implementation on the reference carrier
board.
Figure 1-7. Reset Reference Schematic
+3.3 V
1
R4
1K
0.5%
2
2
SYS_RST#
1
1
R2
RESET_SW#
68.1 0.5%
1/16 W
C3
C0402
SPARE
3
SW3
720176-01
Refer to the SYS_RST# and CARRIER_RST# sections of the NI sbRIO-9651 System on Module
OEM Device Specifications for more information about the behavior of the Reset signals.

Table 1-16. Reset Reference Schematic Design Considerations
Consideration
Series
termination
Notes
When SYS_RST# is driven, you must place a series termination resistor

at the driver. When the driver is a mechanical switch, placing series
termination is especially important due to the low output impedance of
the switch.
Status LED
The sbRIO-9651 SOM provides a Status LED signal for use on a carrier board. The Status LED
indicates the status of the SOM boot process or Safe Mode and can be used to report software
errors.
Status LED Signal Definitions

Table 1-17 describes the Status LED pins and signals on the sbRIO-9651 SOM connector.
1-19
Chapter 1
Table 1-17. Status LED Signal Definitions
Signal Name
STATUS_LED
*
Dedicated
SOM Pin #
Direction*
14
I/O
Standard
Description
LVTTL
Status LED indicator.
Status LED Implementation on the Reference Carrier

Board
Figure 1-8 shows a schematic design for the Status LED implementation on the reference carrier
board.
Figure 1-8. Status LED Reference Schematic
STATUS_LED
R127
DS7
YEL
2
357 0.5%
1/16 W
Refer to the STATUS_LED section of the NI sbRIO-9651 System on Module OEM Device
Specifications for more information about the behavior of the Status LED signal.
1-20
ni.com
FPGA Config
The sbRIO-9651 SOM provides an FPGA Config signal to indicate when the FPGA is
configured.
FPGA Config Signal Definitions

Table 1-18 describes the FPGA Config pins and signals on the sbRIO-9651 SOM connector.
Table 1-18. FPGA Config Signal Definitions
Signal
Name
Dedicated
SOM Pin #
Direction*
FPGA_CFG
53
I/O Standard
Description
Refer to the
NI sbRIO-9651
System on Module
OEM Device
Specifications for
more information
about the behavior
of this signal.
FPGA Config Asserts

when the FPGA is
configured. Asserted
high when the FPGA
has been
programmed.
FPGA Config Implementation on the

Reference Carrier Board
Figure 1-9 shows a schematic design for the FPGA Config implementation on the reference
carrier board.
Figure 1-9. FPGA Config Reference Schematic
DS3
FPGA_CFG
2, 3, 4
R128
357 0.5%
1/16 W
GRN
2
LED_GRN_735278-01
Refer to the FPGA_CFG section of the NI sbRIO-9651 System on Module OEM Device
Specifications for more information about the behavior of the FPGA Config signal.
Temp Alert
The sbRIO-9651 SOM provides a Temp Alert signal to indicate that the onboard CPU/FPGA or
Primary System temperature has exceeded the minimum or maximum temperature
specifications of the sbRIO-9651 SOM. Refer to the Environmental section of the
NI sbRIO-9651 System on Module OEM Device Specifications for the minimum and maximum
temperature specifications.
1-21
Chapter 1
Temp Alert Signal Definitions

Table 1-19 describes the Temp Alert pins and signals on the sbRIO-9651 SOM connector.
Table 1-19. Temp Alert Signal Definitions
Signal Name
TEMP_ALERT
*
Dedicated
SOM Pin #
Direction*
46
I/O
Standard
LVTTL
Description
Temp Alert indicator.

Asserted high.
Temp Alert Implementation on the Reference Carrier

Board
Figure 1-10 shows a schematic design for the Temp Alert implementation on the reference
carrier board.
Figure 1-10. Temp Alert Reference Schematic
LED-QTLP630
TEMP_ALERT
R129
RED
2
357 0.5%
1/16 W
DS4
Refer to the TEMP_ALERT section of the NI sbRIO-9651 System on Module OEM Device
Specifications for more information about the behavior of the Temp Alert signal.
Refer to the Validating Temperature Measurements section of Chapter 4, Mechanical
Considerations, for information about validating the system temperatures of your sbRIO-9651
SOM application.
1-22
ni.com
The sbRIO-9651 SOM connector provides several banks of FPGA pins that you can configure
for purposes specific to your application. In addition to FPGA Digital I/O (DIO), you can use
these pins to implement the following run-time peripheral interfaces:
Secondary Ethernet (GBE1)
Additional RS-232 (Serial2, Serial3, Serial4)
RS-485 (Serial5, Serial6)
CAN (CAN0, CAN1)
The reference carrier board included with the sbRIO-9651 SOM development kit shows an
example of how to implement these signals. Refer to the specific sections in this chapter for more
information about how the reference carrier board implements each signal.
To read or write to this I/O from a LabVIEW project, you must use the
sbRIO CLIP Generator application to create a socketed component-level IP (CLIP)
that defines the I/O configuration of the sbRIO-9651 SOM to use in your application.
Refer to the Getting Started with the NI sbRIO-9651 in LabVIEW topic in the
LabVIEW Help for more information about creating a CLIP.
Note
Tip When you create your own CLIP, you must compile your FPGA VI and
download it to the flash of the sbRIO-9651 SOM. This ensures that the driver for each
enabled peripheral can load properly at boot time. Refer to the Downloading an
FPGA VI to the Flash Memory of an FPGA Target topic in the LabVIEW Help
(FPGA Module) for more information.
Secondary Ethernet (GBE1)

You must use specific FPGA pins to implement a secondary Ethernet port due to the strict timing
requirements across semiconductor process and temperature variations.
The reference carrier board implements one secondary Ethernet port (GBE1) in addition to the
primary Ethernet port. Refer to the Primary Ethernet (GBE0) section of Chapter 1, Fixed
Behavior Signals, for more information about implementing a primary Ethernet port.
Note The sbRIO CLIP Generator enforces the selection of specific FPGA pins
when you implement a secondary Ethernet port.
2-1
Chapter 2
GBE1 Signal Definitions on the Reference Carrier

Board
Table 2-1 describes the GBE1 pins and signals on the sbRIO-9651 SOM connector used to
implement a secondary Ethernet port on the reference carrier board.
Table 2-1. GBE1 Signal Definitions
Signal Name
Pin #*
DIO Signal on
Reference
Carrier Board
Direction
Description
TX Signals
GBE1_GMII_GTX_CLK
192
DIO_62_N
Gigabit transmit
clock.
GBE1_MII_TX_CLK
207
DIO_60_SRCC
10/100 transmit
clock.
GBE1_GMII_TX_EN
215
DIO_60_N
Transmit
enable.
GBE1_GMII_TX_ER
183
DIO_59
Transmit error.
GBE1_GMII_TX_D0
GBE1_GMII_TX_D1
GBE1_GMII_TX_D2
GBE1_GMII_TX_D3
GBE1_GMII_TX_D4
GBE1_GMII_TX_D5
GBE1_GMII_TX_D6
GBE1_GMII_TX_D7
235
227
211
203
187
179
234
242
DIO_49_N
DIO_49
DIO_48_N
DIO_48
DIO_47_N
DIO_47
DIO_46_N
DIO_46
Transmit data
bus.
RX Signals
GBE1_GMII_RX_CLK
231
DIO_61_MRCC
Receive clock.
GBE1_GMII_RX_DV
200
DIO_62_MRCC
Receive data
valid.
GBE1_GMII_RX_ER
239
DIO_61_N
Receive error.
GBE1_GMII_RX_D0
GBE1_GMII_RX_D1
GBE1_GMII_RX_D2
GBE1_GMII_RX_D3
GBE1_GMII_RX_D4
GBE1_GMII_RX_D5
GBE1_GMII_RX_D6
GBE1_GMII_RX_D7
210
218
194
186
170
162
225
233
DIO_45_N
DIO_45
DIO_44
DIO_44_N
DIO_43
DIO_43_N
DIO_42
DIO_42_N
Receive data
bus.
2-2
ni.com
Table 2-1. GBE1 Signal Definitions (Continued)
Signal Name
Pin #*
DIO Signal on
Reference
Carrier Board
Direction
Description
Support Signals
GBE1_GMII_COL
201
DIO_41
Collision
detect.
GBE1_GMII_CRS
209
DIO_41_N
Carrier sense.
GBE1_MDC
177
DIO_40
MDIO clock,
which needs to
be pulled up on
carrier board.
GBE1_MDIO
185
DIO_40_N
I/O
MDIO data,
which needs to
be pulled up on
carrier board.
GBE1_IRQ#
191
DIO_59_N
PHY interrupt
request, which
should be pulled
high on
reference
carrier board.
GBE1_SPEED_LEDg
GBE1_SPEED_LEDy
126
118
DIO_33
DIO_33_N
Speed LED
signals:
Yellow = 1000
Green = 100
Off = 10
* When you use the sbRIO CLIP Generator to enable secondary Ethernet, you must use the pins listed in
this table. If you do not enable secondary Ethernet, you can use these pins for other FPGA DIO.
I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the
sbRIO CLIP Generator.
You can use any available FPGA DIO lines to implement these signals. In NI-RIO Device Drivers
February 2015 or later, you can use the sbRIO CLIP Generator to assign FPGA DIO to these signals.
2-3
Chapter 2
Figure 2-1 shows a schematic design for the GBE1 implementation on the reference carrier board.
Figure 2-1. GBE1 Reference Schematic
+1.8V
1
R19
1K
0.5%
J6
+3.3 V
+1.8 V
+1.8V
GBE1_GMII_RX_ER
GBE1_GMII_RX_DV
GBE1_GMII_RX_D[7]
GBE1_GMII_RX_D[6]
GBE1_GMII_RX_D[5]
GBE1_GMII_RX_D[4]
GBE1_GMII_RX_D[3]
GBE1_GMII_RX_D[2]
GBE1_GMII_RX_D[1]
GBE1_GMII_RX_D[0]
GBE1_GMII_COL
GBE1_GMII_CRS
GBE1_MDC
GBE1_MDIO
+1.8V
R137 1
4.7 K
0.5%
1/16 W
2
GBE1_MII_TX_CLK
R36
24.9 0.5%
1/16 W
R16
R15
R17
1
R18
R25
R24
R28
R47
52
49
24.9 0.5%
1/16 W
50
51
R29
1
AVDDH[0]
AVDDH[1] 16
4
AVDDL[0]
5
AVDDL[1]
12
AVDDL[2]
AVDDL[3] 13
DVDDH[0]
DVDDH[1]
DVDDH[2]
DVDDH[3]
DVDDL[0]
DVDDL[1]
DVDDL[2]
DVDDL[3]
DVDDL[4]
TXRXP_A
TXRXM_A
TXRXP_B
TXRXM_B
R50
24.9 0.5%
1/16 W
C18 1
0.1 UF
10%
16 V 2
1
2
7
8
GBE1_MDI1_P
GBE1_MDI1_N
R49
GBE1_MDI2_P
GBE1_MDI2_N
1
R133
1K
0.5%
GBE1_MDI3_P
GBE1_MDI3_N
2
RXD1/MODE1
RXD0/MODE0
R134
4.7 K
0.5%
1/16 W
R27
10 K
0.5%
1/16 W
R22
10 K
0.5%
1/16 W
NC
VCC
R35
10 K
0.5%
1/16 W
C122 1
0.1 UF
10%
16 V
2
R222
39
0.5%
1/16 W
+1.8 V
C123
12
U7
5
A
B
0.1 UF 10%
16 V
Y
4
1
2
2
R223
39
0.5%
1/16 W
2 Y1
GND1
4
GND2
PERIPHERAL_RESET_1V8#
A
B
0.1 UF 10%
16 V
C14
+1.8 V
+3.3 V
74LVCE1G08
1
2
C115
1
5
+1.8 V
U5
33 pF
50 V
GBE1_XTAL_IN
0.1 UF 10%
50 V
74LVCE1G08
R23
10 K
0.5%
1/16 W
C206
1
C147
0.1 UF
10%
16 V
GBE1_IRQ#
C17
R53
475
1%
1/16 W
Y2 4
A2
NC7WZ16
1
2
R45
SPARE
R0402
GND
GDN VCC
U8
1
NC_GBE1_6
NC_GBE1_62
0 5%
1/16 W
08261K1T-43-F
1
Y1
A1
+1.8 V
GBE1_SPEED_LEDg
24.9 0.5%
1/16 W
1
R39
10 K
0.5%
1/16 W
R20
1K
0.5%
GBE1_XTAL_OUT
16
SN74LVC1G04DBVR
R44
LED1(GRN-CATH)
LED1(GRN-AN)
LED2(GRN-CATH/YEL-AN)
LED2(GRN-AN/YEL-CATH)
+3.3V
MDC
MDIO
12
475 1% GBE1_ACT_LED
1/16W
C9
0.1 UF
10%
16 V
17
18
SHIELD1
SHIELD2
MCTA
MCTB
MCTC
MCTD
13
14
15
16
U11
KSZ9031MNXIA
+1.8 V
24.9 0.5%
1/16 W
C10 1
0.1 UF
10%
16 V 2
GBE1_SPEED_LEDy
+1.8 V
COL
CRS
NC[0] 6
NC[1] 62
C19 1
0.1 UF
10%
16 V 2
R30
AVDDL_PLL_1V2
GBE1_MDIO_P
GBE1_MDIO_N
19 GBE1_LED[1]_1P8
LED1/PHYAD0/~P~M~E~_~1
17 GBE1_LED[2]_1P8
LED[2]/PHYAD1
55 GBE1_LED_MODE
RX_CLK/PHYAD2 CLK125_ND0/LED_MODE
53
RX_ER
~I~N~T/~P~M~E~_~2
RX_DV/CLK125_EN
63 GBE1_ISET
RXD7
ISET
65
1
RXD6
P_GND
1 R41
9
AGNDH[0]
RXD5
12.1 K
64
RXD4
AGNDH[1]
0.1%
1/16 W
RXD3/MODE3
2
2
RXD2/MODE2
RESET~
61
XI
60
XO
2
3
TXRXP_C 10
TXRXM_C 11
14
TXRXP_D
15
TXRXM_D
MDIA_P
MDIA_N~
MDIB_P
MDIB_N~
MDIC_P
MDIC_N~
MDID_P
MDID_N~
12
6
1
7
+1.2 V
58
59
LDO_O
AVDDL_PLL
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
56
24.9 0.5%
1/16 W
32
57
33
31
29
28
27
26
24
23
22
21
48
47
45
34
35
37
38
39
41
43
44
24.9 0.5%
1/16 W
24.9 0.5%
1/16 W
2
2
2
2
2
2
2
2
2
2
GBE1_GMII_TX_EN
GBE1_GMII_TX_ER
GBE1_GMII_TX_D[7]
GBE1_GMII_TX_D[6]
GBE1_GMII_TX_D[5]
GBE1_GMII_TX_D[4]
GBE1_GMII_TX_D[3]
GBE1_GMII_TX_D[2]
GBE1_GMII_TX_D[1]
GBE1_GMII_TX_D[0]
24.9 0.5%
1/16 W
20
25
36
42
54
24.9 0.5%
1/16 W
24.9 0.5%
1/16 W
24.9 0.5%
1/16 W
+1.2 V
2
24.9 0.5%
1/16 W
R37 2
R51
24.9 0.5%
1/16 W
U10
18
30
40
46
2
2
24.9 0.5%
1/16 W
R40
GBE1_GMII_GTX_CLK
R26
10 K
0.5%
1/16 W
25MHZ
GBE1_GMII_RX_CLK
+1.8V
1
R136
4.7 K
0.5%
1/16 W
2
11
10
4
5
3
2
8
9
1
33 pF
50 V
2
2
R224
39
0.5%
1/16 W
C208
0.1 UF
10%
16 V
1
2
C207
0.1 UF
10%
16 V
U26
+1.8V
+3.3V
2
1
C20
0.1 UF
10%
16 V
U13
CARRIER_RST#
6
4
2
2
1
6
1
4 VCCB VCCA 3
5
2 BA
DIR
GND
1
VCCB VCCA
BA
DIR
GND
1
3
5
C151
0.1 UF
10%
16 V
R55
74LVC1T45
PERIPHERAL_RESET_1V8#
74LVC1T45
R54
1K
0.5%
R52
1K
0.5%
2
+1.2 V
AVDDL_PLL Decoupling
L1
1
2
F
BLM15AG121
1
2
C118 1
10 UF
10%
10 V 2
+1.8 V
DVDDL Decoupling
+1.2V
C141 1
0.1 UF
10%
16 V 2
C142 1
0.1UF
10%
2
16 V
C138 1
0.1 UF
10%
16 V 2
C127 1
0.1 UF
10%
16 V 2
C126
0.1 UF
10%
16 V
C134 1
0.1 UF
10%
2
16 V
C136 1
0.1 UF
10%
2
16 V
C133 1
0.1 UF
10%
16 V 2
C132 1
0.1 UF
10%
2
16 V
C139
0.1 UF
10%
16 V
1
C16
10 UF
10%
2
10 V
C15
0.1 UF
10%
16 V
1
2
C148 1
10 UF
10%
10 V 2
C137 1
0.1 UF
10%
2
16 V
DVDDH Decoupling
C143 1
0.1 UF
10%
2
16 V
C125 1
0.1 UF
10%
16 V 2
C124 1
0.1 UF
10%
16 V 2
C140
0.1 UF
10%
16 V
+3.3 V
+1.2V
AVDDL_PLL_1V2
1
1
2
C131 1
10 UF
10%
10 V 2
C128
0.1 UF
16 V
10%
AVDDH Decoupling
GBE1_ACT_LED
ni.com
2-4
GBE1 Reference Schematic
Figure 2-2 shows additional schematic details for the GBE1 TX signal series termination
resistors at the SEARAY.
Figure 2-2. GBE1 TX Series Termination Reference Schematic
+1.8V
GBE1_MDC
R227
49.9 0.5%
1/16 W
GBE1_MDIO
R226
GBE1_GMII_TX_D[7]
R203
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[6]
R204
GBE1_GMII_RX_D[4]
GBE1_GMII_RX_D[5]
2
GBE1_GMII_RX_D[2]
GBE1_GMII_RX_D[3]
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[5]
R205
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[4]
R206
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[3]
R207
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[2]
R208
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[1]
R209
49.9 0.5%
1/16 W
GBE1_GMII_TX_D[0]
R210
GBE1_GMII_RX_D[6]
GBE1_GMII_RX_D[7]
GBE1_GMII_RX_D[1]
GBE1_GMII_RX_D[0]
C145
0.1 UF
10%
16 V
J5
GBE1_GMII_COL
GBE1_GMII_CRS
1
C146
0.1 UF
16 V
10%
168
49.9 0.5%
1/16 W
+1.8V
7
7
7
7
7
7
7
7
7
7
VIO_BANK2_1
177
DIO_40
185
DIO_40_N
201
DIO_41
209
DIO_41_N
225
DIO_42
233
DIO_42_N
170
DIO_43
162
DIO_43_N
194
DIO_44
186
DIO_44_N
218
DIO_45
210
DIO_45_N
242
DIO_46
234
DIO_46_N
179
DIO_47
187
DIO_47_N
203
DIO_48
211
DIO_48_N
227
DIO_49
235
DIO_49_N
196
DIO_50
188
DIO_50_N
220
DIO_51
212
DIO_51_N
VIO_BANK2_2
176
244
DIO_52
236
DIO_52_N
181
DIO_53
189
DIO_53_N
205
DIO_54
213
DIO_54_N
229
DIO_55
237
DIO_55_N
198
DIO_56
190
DIO_56_N
222
DIO_57
214
DIO_57_N
246
DIO_58
238
DIO_58_N
183
DIO_59
191
DIO_59_N
207
DIO_60_SRCC
215
DIO_60_N
231
DIO_61_MRCC
239
DIO_61_N
200
DIO_62_MRCC
192
DIO_62_N
224
DIO_63_SRCC
216
DIO_63_N
1
7
7
7
7
7
GBE1_MII_TX_CLK
R201
GBE1_GMII_TX_ER
GBE1_GMII_TX_EN
49.9 0.5%
1/16W
GBE1_GMII_RX_CLK
GBE1_GMII_RX_ER
GBE1_GMII_RX_DV
R200
49.9 0.5%
1/16W
GBE1_IRQ#
R202
GBE1_GMII_GTX_CLK
49.9 0.5%
1/16W
SBRIO-9651 Mating Connector

Bank 2 - 4 of 6 Symbols
49.9 0.5%
1/16 W
2-5
Chapter 2

Table 2-2 lists design considerations for the schematics shown in Figures 2-1 and 2-2.
Table 2-2. GBE1 Reference Schematic Design Considerations
Consideration
Ethernet PHY
selection
Notes
The only PHY supported for secondary Ethernet is the Micrel

Ethernet PHY, part number KSZ9031MNXIA. Refer to Table 1-4,
Gigabit Ethernet Connector Parts, of Chapter 1, Fixed Behavior
Signals, for information about the Gigabit Ethernet connector parts
used in the sbRIO-9651 SOM development kit.
To meet GMII timing to the sbRIO-9651 SOM, the DIO bank for the
PHY (DVDDH) and VIO_BANK2 on the sbRIO-9651 SOM must be
powered at 1.8 V.
All pull-up and pull-down resistors connected to the PHY must be
implemented in your carrier board design as shown in Figure 2-1.
These connections ensure that the PHY is set up properly for
sbRIO-9651 SOM software support.
Refer to the datasheet for the Micrel Ethernet PHY for more
information about secondary Ethernet PHY requirements.
GMII TX signals
Route the GMII TX signals directly to the Ethernet PHY.

To meet timing requirements, the TX signals must be 1.8 V logic.
You must place series termination resistors at the sbRIO-9651 SOM
connector on the TX signals driving to the Ethernet PHY, as shown in
Figure 2-2.
GMII RX signals
Connect the GMII RX signals directly to the Ethernet PHY.

The pull resistors on the RX signals set options in the PHY when
coming out of reset.
The pull resistors must be implemented in your carrier board design
as shown in Figure 2-1 to ensure that secondary Ethernet works
properly. The resistors must be the same values shown in Figure 2-1.
You must place series termination resistors near the Ethernet PHY on
all RX signals, as shown in Figure 2-1.
PHY crystal
selection
NI recommends that you use a crystal with the Ethernet PHY.

The crystal must be 25 MHz with 50 ppm or better accuracy.
Ensure that you use suitable load capacitors for your crystal.
2-6
| ni.com
Table 2-2. GBE1 Reference Schematic Design Considerations (Continued)

Consideration
MDI data pairs
Notes
The MDI data pairs are connected directly to the Ethernet connector.
Route the MDI data pairs differentially from the PHY to the
connector.
The Ethernet connector has magnetics built into it. You may use
discrete magnetics instead.
Magnetic
selection
Refer to the Gigabit Ethernet Magnetic Requirements section of

Chapter 1, Fixed Behavior Signals, for information about magnetic
requirements.
Ethernet speed
LEDs
Refer to the Ethernet Speed LED Behavior section of the

NI sbRIO-9651 System on Module OEM Device Specifications for
information about Ethernet LED signal behavior and rated drive
current.
Ethernet link
activity LEDs
Figure 2-1 shows the logic required to create the same link activity
LED behavior that the primary Ethernet signal uses.
GBE1 support
signals listed in
Table 2-1
Connect these signals as shown in Figure 2-1.
CARRIER_RST#
The CARRIER_RST# signal should control the Ethernet PHY reset.

Because the PHY has 1.8 V I/O, including the reset input, and the
CARRIER_RST# signal is a 3.3 V signal, level translation is required
to connect the CARRIER_RST# signal to the PHY. U13 provides this
translation in Figure 2-1.
2-7
Chapter 2
GBE1 Routing Considerations

NI recommends the following design practices for properly routing GBE1 signals on your carrier
board:
Length-match GMII TX signals to within 250 mils of the GBE1_GMII_GTX_CLK

signal.
Length-match GMII RX signals to within 250 mils of the GBE1_GMII_RX_CLK signal.
Limit the overall length of GMII TX and RX signals to 5.0 in. or less.
Route MDI pairs differentially with 100 differential trace impedance.
Length-match the positive and negative signal for each MDI data pair to within 10 mils.
Limit the MDI trace lengths to 6.0 in. or less, which is the length at which Ethernet
compliance was tested.
Additional RS-232 (Serial2, Serial3, Serial4)

You can use any FPGA pins to implement additional RS-232 ports.
The reference carrier board implements one secondary RS-232 port (Serial2) in addition to the
primary UART/Console Out port. You can implement additional RS-232 ports (Serial3 and
Serial4) in the same way that the Serial1 signal is implemented on the reference carrier board.
Refer to the UART/Console Out (Serial1) section of Chapter 1, Fixed Behavior Signals for more
information about implementing the primary UART/Console Out port.
Serial2 Signal Definitions on the Reference Carrier

Board
Table 2-3 describes the Serial2 pins and signals on the sbRIO-9651 SOM connector used to
implement an additional RS-232 port on the reference carrier board.
Note The NI-Serial driver has been developed for and tested with the
Texas Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be
compatible.
2-8
| ni.com
Pin #*
DIO Signal on
Reference
Carrier Board
Direction
SERIAL2_TX
66
DIO_0
SERIAL2_RX
69
DIO_7
SERIAL2_RTS#
74
DIO_1
SERIAL2_CTS#
76
DIO_6
SERIAL2_DTR#
59
DIO_2
SERIAL2_DSR#
83
DIO_4
SERIAL2_DCD#
75
DIO_3
SERIAL2_RI#
68
DIO_5
Signal Name
Description
Full-modem RS-232
serial port signals.
* The pin numbers listed in this table are the pins used on the reference carrier board. For your carrier
board design, you can use the sbRIO CLIP Generator to configure these pins for any FPGA DIO.
2-9
Figure 2-3 shows a schematic design for the Serial2 implementation on the reference carrier board.
ni.com
Chapter 2
2-10
Serial2 Reference Schematic

C83
1
C0603, SPARE
C82
1
C0603, SPARE
C81
1
C0603, SPARE
+3.3V
C80
1
+3.3V
2
1
SERIAL2_DCD#
R90
SERIAL2_RX
R87
SERIAL2_RI#
39 0.5%
1/16W
R83
R84
4
5
7
2
8
16
39 0.5%
1/16W
2
C1+
C1C2+
V-
SERIAL2_DTR_F
DOUT1
DOUT2
DOUT3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
RIN1
RIN2
RIN3
RIN4
RIN5
VCC
FORCEON
FORCEOFF~
GND
INVALID~
THERMALPAD
NC1
NC2
NC3
NC4
25
23
22
21
20
19
18
17
R161
+3.3V
SERIAL2_CTS_F
SERIAL2_TX_F#
SERIAL2_RTS_F
SERIAL2_DTR_F
SERIAL2_TX_F#
SERIAL2_CD_F
SERIAL2_DSR_F
SERIAL2_RX_F# +3.3V
SERIAL2_CTS_F
SERIAL2_RI_F
R159
33
1
24
32
SERIAL2_CTS_CONN
SERIAL2_RTS_CONN
5
9
4
8
3
7
2
6
1
SERIAL2_RX_CONN#
10
11
SERIAL2_TX_CONN#
0 5%
1/16W
1
SERIAL2_RTS_F
R152
0 5%
1/16W
27
26
R160
0 5%
1/16W
C175
0.1 UF
10%
16 V
SERIAL2_RX_F#
R153
0 5%
1/16W
1
SERIAL2_DSR_F
R154
SERIAL2_DSR_CONN
0 5%
1/16W
SERIAL2_CD_F
+3.3V
J11
DSUB9-761918-A
1
TRS3253EIRSMR
39 0.5%
1/16W
SERIAL2_DTR_CONN
0 5%
1/16W
C2DIN1
DIN2
DIN3
SERIAL2_RI_CONN
0 5%
1/16W
30
R155
SERIAL2_CD_CONN
0 5%
1/16W
C63
1
R145
SPARE
R0402
2
R80
4.7 K
0.5%
1/16 W
C0603, SPARE
C64
1
C0603, SPARE
FPGA_CFG
2,3
R147
4.7 K
0.5%
1/16 W
9
28
6
39 0.5%
1/16W
SERIAL2_CTS#
R88
31
1
14
13
12
11
10
39 0.5%
1/16W
SERIAL2_DSR#
V+
2
2
2
2
C46
SERIAL2_RI_F
VL
R162
0.1 UF 10%
50 V
29
R81
1K
0.5%
2
15
SERIAL2_SIGNAL_GND_232
0 5%
1/16W
U19
R163
C168
0.1 UF
10%
16 V
SERIAL2_TX
SERIAL2_RTS#
SERIAL2_DTR#
C48
1
2
0.1 UF 10%
50 V
C171
0.1 UF
10%
16 V
+3.3V
1
2
C176
0.1 UF
10%
16 V
C0603, SPARE
C76
1800 PF
50 V
5%
Caps are placed

to reduce emissions.
Standard practice.
120pF, 220pF, 470pF, etc
can be used
C65
1
C0603, SPARE
C66
1
C0603, SPARE
C84
1
C0603, SPARE
C58
0.1 UF 10%
50V
1
R108
R0805, SPARE

Consideration
Notes
Interface
to implement a null-modem RS-232 serial port.
Serial
transceiver
LVTTL signal levels. To minimize the impact of higher voltage signals
on your carrier board, place the serial transceiver near the RS-232
connector.
Series
termination
R83, R84, R87, R88, and R90 are the series termination for Serial2.
Use series termination at the serial transceiver on all signals being
driven to the sbRIO-9651 SOM.
FPGA DIO signals from DIO Bank 0 include series termination on the
sbRIO-9651 SOM. Use series termination at the SEARAY connector
on all signals outside of Bank 0 being driven from the sbRIO-9651
SOM to the serial transceiver.
FPGA
All serial port signals pass through the FPGA on the sbRIO-9651 SOM.
The FPGA_CFG signal is used to disable the serial transceiver when the
FPGA is not configured. Disabling the transceiver in this way prevents
any unwanted glitches on the RS-232 port.
RS-485 (Serial5, Serial6)

You can use any FPGA pins to implement an RS-485 port.
The reference carrier board implements one RS-485 port (Serial5). You can implement an
additional RS-485 port (Serial6) in the same way that the Serial5 signal is implemented on the
reference carrier board.
Serial5 Definitions on the Reference Carrier Board

Table 2-5 describes the Serial5 pins and signals on the sbRIO-9651 SOM connector used to
implement an RS-485 port on the reference carrier board.
Note The NI-Serial driver has been developed for and tested with the Analog
Devices ADM2587EBRWZ Isolated RS-485 transceiver. Other isolated and
non-isolated transceivers may be compatible.
2-11
Chapter 2
Pin #*
Signal Name
DIO Signal on
Reference
Carrier Board
Direction
SERIAL5_TX
70
DIO_11
SERIAL5_TX_EN
78
DIO_12
SERIAL5_RX
79
DIO_14
SERIAL5_RX_EN
87
DIO_15_MRCC
Description
Isolated RS-485
interface signals.
Serial5 Reference Schematic

Figure 2-4 shows a schematic design for the Serial5 implementation on the reference carrier
board.
0.1 uF and 0.01 uF

Across pin 2 and 1
10 uF and 0.1 uF
Across pin 8 and 9
0.1 uF and 0.01 uF
Across pin 19 and 20
10 uF and 0.1 uF
Across pin 12 and 11
+3.3V
Vcc_RS485_1
Vcc_RS485_1
1
2
I
IGND0
+3.3V
10
2
GND1-3
GND1-4 Digital
Isolation iCoupler
6 DE
SERIAL5_TX_EN
SERIAL5_RX
R140
4 RxD
39 0.5%
1/16W
ni.com
IGND0
Y
Z
SERIAL5_RXN
SERIAL5_TXN
SERIAL5_RXP
SERIAL5_TXP
13
15
18
17
SERIAL5_TXP
SERIAL5_TXN
I
SERIAL5_RXP
SERIAL5_RXN
11
GND2-1
I
IGND0
IGND0
5
9
4
8
3
J7
DSUB9-761918-A
I
IGND0
5 RE~
ADM2587E
IGND0
20
19
16
12
14
Tranceiver
SERIAL5_RX_EN
2-12
VDD1-2
SERIAL5_TX
GND2-4
VISOIN
GND2-3
VISOOUT
GND2-2
GND1-2
7 TxD
C155
0.1 UF
10%
16 V
DC-DC Converter
VDD1-1
1
C156
0.01 UF
10%
2
100 V
9
+3.3V
isoPower
C162
10 UF
10%
10 V
3
8
GND1-1
ISOLATION BARRIER
Vcc_RS485_1
U25
1
R141
10 K
1/16 W
0.5%
C161
0.1 UF
10%
16 V
C160
0.1 UF
10%
16 V
C159 2
10 UF
10%
10 V
1
C153
0.01 UF
10%
100 V
7
2
C154 1
0.1 UF
10%
16 V 2
6
1
10
11
+3.3V

Table 2-6 lists design considerations for the schematic shown in Figure 2-4
Consideration
Notes
Interface
to implement an isolated RS-485 serial port.
Serial
transceiver
LVTTL signal levels. This transceiver provides functional isolation of
the RS-485 signals to prevent ground loops from affecting the RS-485
signals.
Series
termination
R140 is the series termination for Serial5. Use series termination at the
serial transceiver on all signals being driven to the sbRIO-9651 SOM.
SOM to the serial transceiver.
RS-485 Layout Considerations

Pay close attention to how the ground planes are arranged under the isolated RS-485 transceiver.
Isolated and non-isolated ground planes overlap across layers to provide some capacitance
between the grounds and help with EMC. Refer to the datasheet for the RS-485 transceiver for
more information.
CAN (CAN0, CAN1)

You can use any FPGA pins to implement a CAN interface port.
The reference carrier board implements one CAN port (CAN0). You can implement an
additional CAN port (CAN1) in the same way that the CAN0 signal is implemented on the
2-13
Chapter 2
CAN0 Signal Definitions on the Reference Carrier Board

Table 2-7 describes the CAN0 pins and signals on the sbRIO-9651 SOM connector used to
implement a CAN interface port on the reference carrier board.
The NI-Embedded CAN driver has been developed for and tested with the
NXP PCA82C251T/YM CAN transceiver. Other transceivers may be compatible.
Note
Table 2-7. CAN0 Signal Definitions
Signal Name
Pin #*
DIO Signal on
Reference
Carrier Board
Direction
Description
CAN0_TX
85
DIO_8
Transmit line.
CAN0_RX
54
DIO_9
Receive line.
CAN0_RS
62
DIO_10
Slope control and

standby.
2-14
ni.com
CAN0 Reference Schematic

Figure 2-5 shows a schematic design for the CAN0 implementation1 on the reference carrier
board.
Figure 2-5. CAN0 Reference Schematic
+3.3V
+5V
C113
0.1 UF
10%
16 V
C6
0.1 UF
10%
16 V
1
2
U2
CAN0_RX
R8
49.9 0.5%
1/16 W
6
4
VCCB
B
GND
VCCA
A
DIR
1
3
5
CAN0_RX_5V
74LVC1T45
+5V
+3.3V
+3.3V
+5V
VCCA
A
DIR
R11
CAN0_TX_5V
39 0.5%
1/16 W
+5V
+5V
+3.3V
+5V
1
2
R130
1K
0.5%
C130
0.1 UF
10%
16 V
1
2
2
CAN0_RS
C121
0.1 UF
10%
16 V
VCCB
B
GND
VCCA
A
DIR
1
3
5
R9
C114
0.1 UF
10%
16 V
CAN0_RX_5V_R
J4
DSUB9-761918-A
U3
2
8
RXD
TXD
VCC
VREF
GND CANH
RS
CANL
PCA82C251T
5
5
9
4
NC_RESERVED1
NC_RESERVED2
7
6
8
3
CAN0_CANH
CAN0_CANL
7
2
6
1
NC_RESERVED3
R10
1K
0.5%
U6
6
4
2
4
1
3
74LVC1T45
+3.3V
R7
39 0.5%
1/16 W
VCCB
B
GND
1
3
5
6
4
2
R12
1K
0.5%
U4
2
CAN0_TX
C117
0.1 UF
10%
16 V
C120
0.1 UF
10%
16 V
2
R132
1K
0.5%
10
11
2
2
CAN0_RS_5V
39 0.5%
1/16 W
74LVC1T45
C11
1
0.1 UF 10%
50 V
The NXP PCA82C25IT CAN transceiver requires 5 V logic levels. The reference carrier board uses
external discrete buffers to translate 3.3 V FPGA lines to 5 V logic levels.
2-15
Chapter 2

Table 2-8 lists design considerations for the schematic shown in Figure 2-5
Table 2-8. CAN0 Reference Schematic Design Considerations
Consideration
CANx_RX,
CANx_TX, and
CANx_RS
Notes
The recommended CAN transceiver requires 5 V I/O.

U2, U4, and U6 provide level translation between the 3.3 V I/O on the
sbRIO-9651 SOM and the 5 V I/O on the transceiver. Use caution
when implementing this level translation.
The TXD and RS inputs of the CAN transceiver must remain high
during power-down and power-up of the sbRIO-9651 SOM and carrier
board. This prevents glitches on the CAN bus that might disrupt
communication between other devices on the bus. The level translator
IC in this schematic prevents these glitches.
The level translator output remains at high impedance until both of its
power supply rails are powered to allow the 5 V power supply to
power-up before the 3.3 V power supply.
All signals have series termination at the outputs to prevent over- or
under-shoot at the receivers.
SOM to the CAN transceiver.
CANx_CANH
and
CANx_CANL
Route these signals differentially with a 120 differential trace

impedance.
Minimize the overall length of the traces so that you can place
termination resistors in the CAN cabling as close as possible to the
CAN transceiver.
Depending on your design requirements, you can also place the CAN
termination resistor on the carrier board.
2-16
ni.com
Termination Resistors for CAN Cables

The termination resistors should match the nominal impedance of the CAN cable and therefore
comply with the values in Table 2-9.
Table 2-9. Termination Resistor Specification
Characteristic
Termination resistor
Value
100 minimum
120 nominal
130 maximum
Condition
Minimum power
dissipation: 220 mW
2-17
Carrier Board PCB Layout

Guidelines
Use the guidelines in this chapter to help you arrange the I/O signals you implement in your
carrier board design.
Impedance-Controlled Signaling
Use the following guidelines for implementing impedance for all I/O signals:
All signals connected to the sbRIO-9651 SOM must use impedance-controlled traces.
Refer to the sections of this document listed in Table 3-1 for information about impedance
requirements.
Table 3-1. Impedance Requirements Resources
Impedance Requirement
Resource
General requirements for single-ended

signals
Single-Ended Signal Best Practices section

of this chapter
General requirements for differential signals
Differential Signal Best Practices section of

this chapter
Signal-specific requirements
Signal-specific sections in Chapter 1, Fixed

Behavior Signals, or Chapter 2,
Trace geometry to meet impedance requirements vary depending on your specific carrier
board PCB stack-up. Collaborate with your vendor to match impedance requirements,
stack-up, and trace geometry appropriate for your application.
To properly maintain trace impedance and avoid discontinuities, you cannot route traces
over gaps in the reference plane. Use stitching vias and capacitors when appropriate near
layer changes to provide a transient return path between reference planes.
3-1
Chapter 3
Carrier Board PCB Layout Guidelines
Single-Ended Signal Best Practices

Use the following guidelines for implementing single-ended I/O signals:
Route all single-ended signals that are implemented on your carrier board and connected to
the sbRIO-9651 SOM with 50 characteristic trace impedance.
Maintain at minimum a 2 H line spacing between single-ended traces, where H is the

distance in the board stack-up from the trace to its reference plane.
When you configure FPGA DIO signals from DIO Bank 1, 2, or 3 as single-ended traces,
observe the following guidelines:
Use the DIO_x positive signals first because those signals have slightly lower
crosstalk in the J1 connector on the sbRIO-9651 SOM than the DIO_x negative
(DIO_x_N) signals.
To minimize crosstalk when using the DIO_x_N signals, ensure that you implement
corresponding positive and negative signals in the same direction. For example, if you
are using DIO_16 and DIO_16_N, implement both signals as inputs or both as outputs.
Avoid implementing one as an input and the other as an output.
To improve signal integrity on the carrier board, place series termination resistors on
outputs from the sbRIO-9651 SOM as close to the mating connector as possible.
Note FPGA DIO signals from DIO Bank 0 include series termination resistors near
the Xilinx Zynq SoC on the sbRIO-9651 SOM. Refer to the FPGA DIO section of
the NI sbRIO-9651 System on Module OEM Device Specifications for more
information.
Differential Signal Best Practices

Use the following guidelines for implementing differential I/O signals:
Route all differential signals that are implemented on your carrier board and connected to
the sbRIO-9651 SOMother than USB data pair signalswith 100 differential trace
impedance. Route USB data pair signals with 90 differential trace impedance.
Maintain at minimum a 3 H spacing between differential pairs and any other copper
features on the same layer, where H is the distance in the board stack-up from the trace to
its reference plane.
3-2
| ni.com
Ground and Power Plane Recommendations

Use the following guidelines for implementing ground and power planes:
You must include ground planes on your carrier board. All GND pins on the J1 connector
of the sbRIO-9651 SOM must connect to the carrier board ground planes.
If possible, use planes to connect power to the sbRIO-9651 SOM. All power pins on the J1
connector of the sbRIO-9651 SOM must be connected and powered, even if a bank of DIO
is unused.
Fanout and Layout Options

Refer to Samtec SEARAY documentation for information about possible fanout and layout
options with various layer count carrier boards.
3-3
Proper mechanical design is critical for rugged environments in which the sbRIO-9651 SOM
may be subjected to extreme temperatures, shock, vibration, and other factors. In particular,
pay special attention to thermal performance to ensure that your application meets the
sbRIO-9651 SOM operating requirements.
Mounting
You can mount the sbRIO-9651 SOM and carrier board in a variety of ways in order to maximize
system performance. Some mounting methods might require custom fasteners or unique
assembly techniques to maintain required connector stack heights and enable improved thermal
and structural design for rugged environments.
Selecting an Appropriate Mating Connector

The J1 connector on the sbRIO-9651 SOM is a Molex 45971-4185 320-pin, 8 40 position,
SEARAY open-pin-field-array connector. To interface with the J1 connector, your carrier board
design must implement a mating connector that is compatible with the Molex 45971 series or
Samtec SEAF series. Table 4-1 lists compatible mating connectors, such as the Molex 45970
series or Samtec SEAM series.
Table 4-1. sbRIO-9651 SOM Connector and Compatible Mating Connectors
Connector
Manufacturer, Part Number
sbRIO-9651 SOM J1 connector
Molex, 45971-4185 (equivalent to

Samtec SEAF-40-05.0-S-08-2-A-K-TR)
Recommended mating connector*
Molex, 45970-4130
Alternative 7-mm stack height mating

connectors
Molex, 45970-4185
Samtec, SEAM-40-02.0-S-08-2-A-K-TR
Compatible connectors are available in multiple stack height and termination options. NI has secured
a special Molex connector part number, 45970-4130, with a 7-mm mated pair stack height. Refer to the
Ordering the Recommended Mating Connector section of this chapter for information about ordering
connectors. Consult Molex or Samtec for alternative stack heights and terminations.
4-1
Chapter 4
Ordering the Recommended Mating Connector

The recommended mating connector is distributed through TTI, Inc. at NI-negotiated pricing
and with shortened lead times. Complete the following steps to order individual bulk or reel
quantities of the mating connector.
1.
Visit www.ttiinc.com.
2.
Search for the 45970-4130 part number. Table 4-2 describes the available parts.
3.
Contact TTI, Inc. directly and request NI pricing when obtaining a quote. You may also be
able to place an order directly from the TTI, Inc. website.
Table 4-2. Orderable Mating Connector Parts from TTI, Inc.
Part Number
Description
45970-4130
A packaged reel of 300 connectors.
45970-4130 BULK
One or more individual connectors.
These recommended connectors are available only from TTI, Inc. distribution
centers located in the United States but can be shipped internationally. Customers
outside the U.S. should contact a U.S.-based distribution center and request
international shipping.
Note
Note
Online pricing might not reflect negotiated pricing.
Selecting Appropriate Standoffs

The Molex 45970 series and Samtec SEAM series connectors are available in multiple heights.
The height of the mating connector you select determines the height of the standoffs you need.
To prevent over-insertion, the SEARAY connector design requires that standoffs never be less
than the stack height. Because standard nominal tolerances might result in a standoff being
shorter than the stack height, NI requires that you use standoffs that are 0.15 mm (0.006 in.)
taller than the combined height of the J1 connector on the sbRIO-9651 SOM and the mating
SEARAY connector. Therefore, to determine the required standoff height, you must add the
heights of the mated connectors plus an additional 0.15 mm (0.006 in.). Refer to Samtec
documentation for more information about SEARAY standoff requirements.
4-2
ni.com
Table 4-3 provides an example standoff height calculation using a Molex 45970-4130 mating
connector.
Table 4-3. Example Connector Configuration and Calculated Standoff Height
Component
Manufacturer,
Part Number
Height
J1 connector on the sbRIO-9651 SOM
Molex, 45971-4185
5.00 mm (0.197 in.)
Mating connector
Molex, 45970-4130
2.00 mm (0.079 in.)
Required additional standoff height
0.15 mm (0.006 in.)
Total calculated standoff height
7.15 mm (0.281 in.)
NI Custom Standoffs
NI offers a custom standoff that is an exact fit with the recommended or other compatible 7-mm
stack height mating connectors listed in Table 4-1. This custom M3 7.15 mm (0.281 in.) is
made from 4.5 mm (0.177 in.) stainless steel hex stock and includes a nylon threadlock patch.
The external threads extend 4.78 mm (0.188 in.) and the internal threads are 5 mm (0.197 in.)
deep. Table 4-4 lists orderable quantities of this custom standoff.
Table 4-4. Custom M3 7.15 mm (0.281 in.) Standoff Kits
Quantity
Manufacturer, Part Number
20
NI, 157543-020
500
NI, 157543-500
NI recommends that you use stainless steel fasteners for good corrosion resistance and strength.
Tighten M3 fasteners to a torque of 0.76 N m (6.70 lb in), unless otherwise noted or required
by your specific design constraints.
4-3
Chapter 4
Mounting Direction Options

Figures 4-1 through 4-3 show possible mounting configurations and associated fastener types.
Mounting on a Panel or Plate (Recommended)

If possible, NI recommends that you mount the sbRIO-9651 SOM on a panel or plate, as shown
in Figure 4-1.
Figure 4-1. Mounting on a Panel or Plate
1
1
2
3
4
Exploded view of all mounting

components
Complete assembled and mounted view
Standoff, 15.00 mm (0.591 in.)
Carrier board
5
6
7
8
Mounting surface
Mounting screw, panel thickness + 12.00 mm (0.472 in.)
sbRIO-9651 SOM
The sbRIO-9651 SOM was designed so that you can use the 15.00 mm (0.591 in.) standoffs
between the carrier board and the base panel when the 7.15 mm (0.281 in.) standoffs are used
between the carrier board and the sbRIO-9651 SOM, as shown in Figure 4-1.
This method accommodates a layer of thermal grease that is 0.08 mm (0.003 in.) thick between
the aluminum heat spreader of the sbRIO-9651 SOM and the metal base panel. However, thicker
4-4
ni.com
thermal interface materials may require different lengths of standoffs or mounting bosses. The
direction of fastening may also require custom lengths or types of fasteners and might impact
ease of assembly.
Mounting on a Panel or Plate with Flathead Screws

Alternatively, use flathead screws when mounting on a panel or plate, as shown in Figure 4-2.
Figure 4-2. Mounting on a Panel or Plate with Flathead Screws
1
1
2
3
4
Exploded view of all mounting components

Mounting surface
Carrier board
5
6
7
Mounting screw, 12.00 mm (0.472 in.)

sbRIO-9651 SOM
4-5
Chapter 4
Mounting on a Panel or Plate with an Attached Heat Sink

Your system design might require you to attach a heat sink or other thermal solution described
in the Mounting Recommendations for Maximizing Thermal Performance section of this
chapter. Figure 4-3 shows standoffs and fasteners that are compatible with the AlphaNovatech
S01LZZ0E-A heat sink that is included in the sbRIO-9651 SOM development kit.
Figure 4-3. Mounting on a Panel or Plate with an Attached Heat Sink
1
1
2
3
4
Exploded view of all mounting components

Mounting surface
Carrier board
5
6
7

sbRIO-9651 SOM
Mounting screw, 16.00 mm (0.630 in.)
Managing Thermal Conditions

Due to the compact size of the sbRIO-9651 SOM, it is very important to appropriately dissipate
the heat generated during operation. You must plan for the thermal conditions of your
application throughout development and validation. This section provides design
recommendations and validation tools and methods for maximizing the thermal performance
of the system.
4-6
ni.com
Designing a Suitable Enclosure

NI sbRIO devices operate as components in a higher-level system and may require an enclosure
to protect the internal circuit card assembles and dissipate heat. For the sbRIO-9651 SOM, the
system integrator is responsible for designing an enclosure that meets the thermal requirements
of your specific application.
NI sbRIO devices integrated into an enclosure or system with proper thermal dissipation can
be deployed in high- and low-temperature environments. However, the 85 C local ambient
operating temperature rating of the sbRIO-9651 SOM does not mean that the external
temperature of the natural convection environment such as a room or larger enclosure can be
85 C. In this way, properly designed NI sbRIO devices may still require an external ambient
temperature of 70 C or less and may still require specific mounting requirements to ensure that
the local ambient and thermally-relevant component maximum operating temperatures are
within specification.
Understanding Thermal Specifications

A deployed system has several temperature measurement locations that indicate the thermal
performance of the system and the devices the system contains. For example, in a natural
convection system, the temperature of a critical component will be higher than the temperature
of the air in the immediate vicinity of the component. This local air temperature will also be
higher inside an enclosure than in the room ambient that surrounds the enclosure.
4-7
Chapter 4
Figure 4-4 identifies these types of ambient temperatures.

Figure 4-4. Ambient Temperatures
1
2
3
External ambient temperature

Internal/enclosure ambient temperature
Carrier board
4
5
6
sbRIO-9651 SOM
Local ambient temperature
Enclosure
External ambientThe maximum air temperature of the room or installation location that
surrounds the system.
Internal/enclosure ambientThe maximum air temperature inside the enclosure. This
can be measured at various locations within the enclosure and is highly influenced by the
proximity and dissipation of devices inside the enclosure.
Local ambientThe maximum air temperature as specified directly adjacent to the
NI sbRIO device. This is measured on all sides of a device that has exposed circuitry.
Because the sbRIO-9651 SOM has an integrated heat spreader on the primary side, only
the secondary side needs to be measured.
Because the system integrator may use any number of enclosure sizes, materials, thermal
solutions, and room conditions when designing an enclosure for a specific application, NI sbRIO
devices are specified in a manner that removes most of these external variables. Therefore, the
sbRIO-9651 SOM thermal performance is not determined by measuring the external ambient or
internal/enclosure ambient temperatures, but by measuring the local ambient and specific
component temperatures. NI provides digitally reported temperatures to help you accurately
measure these critical temperatures.
4-8
| ni.com
Validating the System

NI recommends that you use a validation system for an extended period of time in a test
environment with the same thermal, environmental, and functional utilization characteristics as
the target deployment environment. You are responsible for final validation of your application.
Validating Temperature Measurements

The sbRIO-9651 SOM includes three onboard temperature-monitoring sensors to simplify
validation of a thermal solution, as shown in Figure 4-5. The sensors provide an indication of
thermal performance and are used to validate the system along with the local ambient operating
temperature.
Figure 4-5. Onboard Temperature-Monitoring Sensors
1
2
3
1
CPU/FPGA sensor
Primary System sensor
Secondary System sensor
CPU/FPGA sensorDigitally reports the die junction temperature of the Xilinx

Zynq SoC.
Primary System sensorDigitally reports the temperature on the Xilinx Zynq SoC side
of the circuit card assembly underneath the integrated heat spreader. This value is an
approximation of the local ambient temperature inside the heat spreader.
Secondary System sensorDigitally reports the temperature on the SEARAY side of the
circuit card assembly. This value is a conservative approximation of the local ambient
temperature on that side of the circuit card assembly.
4-9
Chapter 4
To meet the thermal specifications described in the NI sbRIO-9651 System on Module OEM
Device Specifications, you must record the following measurements:
The CPU/FPGA reported temperature, which must not exceed 98 C
The Primary System reported temperature, which must not exceed 85 C
The local ambient operating temperature near the device, which must not exceed 85 C
Measure the local ambient temperature by placing a thermocouple near the center of the printed
circuit board 5 mm (0.2 in.) from the board surface. Alternatively, you can rely on the reported
Secondary System temperature to provide a conservative estimate of the local ambient
temperature. This alternative method provides a completely digital validation scheme that does
not require using a thermocouple and allows you to validate the sbRIO-9651 SOM as part of
every deployment.
In addition to being useful for system validation, digitally reported temperatures also provide
feedback about system health and can be used as triggers or set points. The TEMP_ALERT
signal from the J1 connector on the sbRIO-9651 SOM asserts when the CPU/FPGA or Primary
System reported temperatures exceed specification. However, you should not use the
TEMP_ALERT signal in place of proper system validation because the TEMP_ALERT signal
does not monitor the Secondary System or local ambient temperatures. Refer to the Temp Alert
section of Chapter 1, Fixed Behavior Signals, for more information about the TEMP_ALERT
signal.
NI recommends that you monitor the digitally reported temperatures on deployed systems,
especially if the temperatures approach the maximum thermal specifications during system
validation testing. Monitoring allows individual systems to identify adverse thermal changes
caused by differences in environmental, operating, or process conditions.
For more information about how to access and use the digitally reported temperature sensor
measurements, visit ni.com/info and enter the Info Code sbriosensors.
Managing Power and Feature Utilization

An sbRIO-9651 SOM that heavily utilizes all of its performance and features consumes and
dissipates substantially more power than when the device is idle. Certain features, such as LVDS
outputs, can greatly increase the power that the Xilinx Zynq SoC dissipates and therefore also
quickly raise the die junction temperature.
Consider the following options for reducing the die junction temperature:
Design for additional thermal cooling that can appropriately dissipate power
Reduce device feature utilization

Your final validation must consider software and hardware utilization that is
representative of the final deployment conditions.
Note
4-10
ni.com
Note Refer to the Input Power Requirements section of the NI sbRIO-9651 System
on Module OEM Device Specifications for specifications that approximate the
maximum power requirement for each input rail on an sbRIO-9651 SOM with
worst-case silicon manufacturing process and maximum junction temperatures. For
a more accurate estimate of the power consumption for a specific application,
NI recommends that you directly measure the power the sbRIO-9651 SOM
consumes when running your application in an environment that is representative of
the intended use case. You can use the Xilinx Power Estimator to calculate the
VIO_BANK input rail power for a given configuration.
Mounting Recommendations for Maximizing Thermal

Performance
The sbRIO-9651 SOM includes an integrated heat spreader that uses a thermal gap filler material
to effectively conduct into the spreader the heat that the circuit card assembly components
generate. NI recommends the following mounting procedures for maximizing the thermal
performance of your application:
Directly mount the flat and smooth exterior surface of the integrated heat spreader to
a thermally-conductive surface, such as a metal enclosure wall or plate, as shown in
Figure 4-1. An interface material such as thermal grease should be used to maximize the
heat transfer from the integrated heat spreader to the enclosure or plate. The enclosure or
plate conducts and convects the heat to the external ambient environment.
If design limitations prevent this solution, you can alternatively attach a heat sink or other
thermal solution to the integrated heat spreader, as shown in Figure 4-3. This solution takes
advantage of natural convection or forced convection cooling provided by a fan.
Mount the sbRIO-9651 SOM vertically with respect gravity to take advantage of natural
convection cooling.
Mount the sbRIO-9651 SOM below and away from other heat-dissipating components.
Note Placing the sbRIO-9651 SOM within a system or enclosure will also
influence thermal performance.
4-11
Chapter 4
Figure 4-6 shows good, better, and best thermal mounting solutions for the sbRIO-9651 SOM.
Figure 4-6. Thermal Mounting Solutions Comparison
1
1
2
3
GoodHorizontal mounting with no additional thermal provisions

BetterVertical mounting with an attached heat sink, as described in Figure 4-3
BestVertical mounting directly to a thermally-conductive wall or plate, as described in Figure 4-1
Additional Resources for Managing Thermal Conditions

Visit ni.com/info and enter the Info Code sbriocooling for the following additional
information to help you manage thermal conditions:
Examples regarding the effect of the design factors discussed in this chapter
Case study examples to help you estimate the achievable external ambient temperature for
a representative system
Shock and Vibration

The mounting method you use, components you select, and assembly techniques you use
influence the ability of the system to resist fretting corrosion and other damage caused by
exposure to shock and vibration. Consider the following factors when designing your
sbRIO-9651 SOM system to account for shock and vibration:
In general, shorter SEARAY stack heights perform better than taller stack heights.
Directly mounting the sbRIO-9651 SOM heat spreader to a rigid surface provides the best
performance. If this method is not feasible for your design, minimize the amount of extra
mass that only the sbRIO-9651 SOM supports, such as a heat sink or other thermal solution,
that is fastened to the four standoffs. If you require substantial thermal solutions, provide
additional structural support.
4-12
ni.com
NI recommends that you use connectors that provide the following benefits:
Positive locking
Provisions for strain relief
Substantial gold plating on pins
The connectors on the reference carrier board are representative of connectors that NI has
used and validated for high shock and vibration environments. The connectors and the
sbRIO-9651 SOM have been tested to industry specifications and are recommended, where
possible, for rugged environments.
Exceptions to this recommendation are the barrel jack and Peripheral Module (Pmod)
headers, which have designs that are not positive-locking or do not provide strain relief.
NI offers a variety of cable assemblies and other connectivity accessories to complete your
system design. Typically, these accessories include the best available designs, materials,
and plating to maximize performance and longevity in rugged environments.
4-13
Reference Carrier Board

Specifications and User
Guide
This appendix provides pinouts, connectivity information, and specifications for the reference
carrier board included with the sbRIO-9651 SOM development kit.
The reference carrier board provides the following:
A hardware environment for developing and evaluating designs that target the
sbRIO-9651 SOM.
Access to most of the onboard peripherals available on the sbRIO-9651 SOM, including
Ethernet, serial RS-232 and RS-485, USB Device, USB Host, SD card, and FPGA I/O.
Additional supported capability through five Pmod connectors on the breadboard circuit
prototyping area.
Visit ni.com and search for 9651 for the reference carrier board schematic
and PCB gerber files.
Note
Parts Locator Diagram and Block Diagram

Refer to the NI sbRIO-9651 System on Module Development Kit Quick Start Guide for the
reference carrier board parts locator diagram and hardware block diagram.
Specifications
The following specifications are typical and not guaranteed.
Refer to the NI sbRIO-9651 System on Module OEM Device Specifications
for complete specifications for each interface the sbRIO-9651 SOM supports. The
specifications listed in this section pertain only to the interfaces implemented on the
Note
A-1
Appendix A
Ethernet
The reference carrier board includes the following tri-mode Ethernet ports:
Ethernet0Utilizes the primary Ethernet (GBE0) fixed behavior interface from the
sbRIO-9651 SOM.
Ethernet1Implemented from the secondary Ethernet user-defined FPGA interface.
Serial
Number of ports
TX/RX-only RS-232.................................1 (Serial1)
Full-modem RS-232 .................................1 (Serial2)
RS-485 ......................................................1 (Serial5)
CAN
Number of CAN ports.......................................1 (CAN0)
SD Card
Number of full-size SD card sockets ................1 (J2)
Refer to SanDisk Corporation or SD Association websites for information about SD I/O card
specifications.
USB
Number of ports
USB Device ..............................................1 (USB0)
USB Host ..................................................1 (USB1)
USB Host maximum current.............................900 mA (supports USB3 Vision cameras)
Pmod
The Pmod standard is defined by Digilent, Inc. and is used for small I/O interface boards that
extend the capabilities of FPGA control boards. Pmods communicate with system boards via
6- or 12-pin connectors. The reference carrier board provides Pmod-compatible connectors to
support quick connectivity to the Pmod ecosystem for prototyping and evaluating sensors,
converters, connectors, and other devices.
Note Refer to the Digilent website at www.digilentinc.com for more
information about Pmods.
A-2
ni.com
Number of ports
Pmod 12-pin ............................................. 4 (Pmod1, Pmod2, Pmod3, Pmod4)
Pmod I2C .................................................. 1 (Pmod5)
Pmod Vcc
Voltage ...................................................... 3.3 V
Current ...................................................... 100 mA
Pmod Signal Definitions on the Reference Carrier Board

Table A-1 describes the pins and signals on the sbRIO-9651 SOM connector used to implement
four Pmod 12-pin connectors.
Refer to the Pmod 12-Pin Connector Pinout section of this chapter for more
information about the Pmod 12-pin connector pins and signals on the reference
carrier board.
Note
Table A-1. Pmod 12-pin Connector Signal Definitions

Signal Name*
Pin #
PMOD1_PIN1
PMOD1_PIN2
PMOD1_PIN3
PMOD1_PIN4
PMOD1_PIN7
PMOD1_PIN8
PMOD1_PIN9
PMOD1_PIN10
114
90
122
98
138
146
153
161
PMOD3_PIN1
PMOD3_PIN2
PMOD3_PIN3
PMOD3_PIN4
PMOD3_PIN7
PMOD3_PIN8
PMOD3_PIN9
PMOD3_PIN10
148
116
140
124
92
109
100
117
Signal Name*
Pin #
DIO_20_N
DIO_19_N
DIO_20
DIO_19
DIO_21_N
DIO_21
DIO_18
DIO_18_N
PMOD2_PIN1
PMOD2_PIN2
PMOD2_PIN3
PMOD2_PIN4
PMOD2_PIN7
PMOD2_PIN8
PMOD2_PIN9
PMOD2_PIN10
164
131
172
139
107
155
115
163
DIO_28_N
DIO_23
DIO_28
DIO_23_N
DIO_22
DIO_24
DIO_22_N
DIO_24_N
DIO_27
DIO_26_N
DIO_27_N
DIO_26
DIO_25_N
DIO_29
DIO_25
DIO_29_N
PMOD4_PIN1
PMOD4_PIN2
PMOD4_PIN3
PMOD4_PIN4
PMOD4_PIN7
PMOD4_PIN8
PMOD4_PIN9
PMOD4_PIN10
135
111
143
119
159
167
142
150
DIO_37_MRCC
DIO_36_SRCC
DIO_37_N
DIO_36_N
DIO_38_MRCC
DIO_38_N
DIO_34_N
DIO_34
DIO Signal
DIO Signal
All signals have both I/O directions and comply with the LVTTL I/O standard.
A-3
Appendix A
Table A-2 describes the specific pins and signals on the sbRIO-9651 SOM connector used to
implement a Pmod I2C connector.
Refer to the Pmod I2C Connector Pinout section of this chapter for more
information about the Pmod I2C connector pins and signals on the reference carrier
board.
Note
Table A-2. Pmod I2C Connector Signal Definitions

Signal Name*
Pin #
DIO Signal
PMOD_I2C_SCL1
PMOD_I2C_SCL2
105
129
DIO_16
DIO_17
PMOD_I2C_SDA1
PMOD_I2C_SDA2
113
137
DIO_16_N
DIO_17_N
All signals have both I/O directions and comply with the LVTTL I/O standard.
RTC Battery
The reference carrier board provides a battery backup for the RTC on the sbRIO-9651 SOM.
Support Signals
The reference carrier board implements support signals in the following ways:
STATUS_LED and TEMP_ALERT signals are routed to user-visible LEDs.
SYS_RST# is connected to a Reset push button.
Connector Pinouts
RS-232, RS-485, and CAN Connector Pinouts
The RS-232, RS-485, and CAN connectors on the reference carrier board use the port shown in
Figure A-1. Table A-3 describes the pins and signals on each port.
Figure A-1. RS-232, RS-485, and CAN Port Pin Locations
Pin 6
Pin 9
A-4
ni.com
Pin 1
Pin 5
Table A-3. RS-232, RS-485, and CAN Port Pins and Signals
TX/RX-only
RS-232
Pin
Signal
Full-modem
RS-232
Pin
RS-485
Signal
Pin
CAN
Signal
Pin
Signal
NC
DCD
GND
NC
RXD
RXD
NC
CANL
TXD
TXD
NC
GND
NC
DTR
RXP
NC
GND
GND
RXN
SHIELD
NC
DSR
NC
GND
NC
RTS
NC
CANH
NC
CTS
TXP
NC
NC
RI
TXN
NC
Pmod 12-Pin Connector Pinout

The Pmod 12-pin connectors on the reference carrier board use the port shown in Figure A-2.
Table A-4 describes the pins and signals on the port.
Figure A-2. Pmod 12-Pin Port Pin Locations
4
12 11 10
Table A-4. Pmod 12-Pin Port Pins and Signals

Pin
Signal
Pin
Signal
PMODx_PIN1
PMODx_PIN7
PMODx_PIN2
PMODx_PIN8
PMODx_PIN3
PMODx_PIN9
PMODx_PIN4
10
PMODx_PIN10
GND
11
GND
3.3 V power
12
3.3 V power
A-5
Appendix A
Pmod I2C Connector Pinout

The Pmod I2C connector on the reference carrier board uses the port shown in Figure A-3.
Table A-5 describes the pins and signals on the port.
Figure A-3. Pmod I2C Port Pin Locations
2
Table A-5. Pmod I2C Port Pins and Signals

Pin
Signal
Pin
Signal
PMOD5_SCL1
GND
PMOD5_SCL2
GND
PMOD5_SDA1
3.3 V power
PMOD5_SDA2
3.3 V power
Environmental Management
NI is committed to designing and manufacturing products in an environmentally responsible
manner. NI recognizes that eliminating certain hazardous substances from our products is
beneficial to the environment and to NI customers.
For additional environmental information, refer to the Minimize Our Environmental Impact web
page at ni.com/environment. This page contains the environmental regulations and
directives with which NI complies, as well as other environmental information not included in
this document.
Waste Electrical and Electronic Equipment (WEEE)

At the end of the product life cycle, all products must be sent to
a WEEE recycling center. For more information about WEEE recycling centers,
National Instruments WEEE initiatives, and compliance with WEEE Directive
2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/
weee.
EU Customers
A-6
ni.com
Battery Replacement and Disposal

This device contains a long-life coin cell battery. If you need
to replace it, use the Return Material Authorization (RMA) process or contact an
authorized National Instruments service representative. For more information
about compliance with the EU Battery Directives 2006/66/EC about Batteries
and Accumulators and Waste Batteries and Accumulators, visit ni.com/
environment/batterydirective.
Battery Directive
Cd/Hg/Pb
RoHS
(RoHS) National Instruments RoHS ni.com/
environment/rohs_china (For information about China RoHS compliance,
go to ni.com/environment/rohs_china.)
A-7
Revision History
Table B-1 lists changes to this document since its first iteration.
Table B-1.
Revision
Edition Date
August 2015
December 2014
Changes
Added information about eliminating the effects of

contact bounce to the Eliminating the Effects of
Contact Bounce section of Chapter 1, Fixed
Behavior Signals.
Added more information about ordering the

recommended mating connector
(Molex, 45970-4130) from TTI, Inc. to the Ordering
the Recommended Mating Connector section of
Chapter 4, Mechanical Considerations.
B-1
NI Services
National Instruments provides global services and support as part of our commitment to your
success. Take advantage of product services in addition to training and certification programs
that meet your needs during each phase of the application life cycle; from planning and
development through deployment and ongoing maintenance.
To get started, register your product at ni.com/myproducts.
As a registered NI product user, you are entitled to the following benefits:
Access to applicable product services.
Easier product management with an online account.
Receive critical part notifications, software updates, and service expirations.
Log in to your National Instruments ni.com User Profile to get personalized access to your
services.
Services and Resources
Maintenance and Hardware ServicesNI helps you identify your systems accuracy and
reliability requirements and provides warranty, sparing, and calibration services to help you
maintain accuracy and minimize downtime over the life of your system. Visit ni.com/
services for more information.
Warranty and RepairAll NI hardware features a one-year standard warranty that

is extendable up to five years. NI offers repair services performed in a timely manner
by highly trained factory technicians using only original parts at a National
Instruments service center.
CalibrationThrough regular calibration, you can quantify and improve the

measurement performance of an instrument. NI provides state-of-the-art calibration
services. If your product supports calibration, you can obtain the calibration certificate
for your product at ni.com/calibration.
System IntegrationIf you have time constraints, limited in-house technical resources, or
other project challenges, National Instruments Alliance Partner members can help. To learn
more, call your local NI office or visit ni.com/alliance.
C-3
Appendix C
NI Services
Training and CertificationThe NI training and certification program is the most

effective way to increase application development proficiency and productivity. Visit
ni.com/training for more information.
The Skills Guide assists you in identifying the proficiency requirements of your
current application and gives you options for obtaining those skills consistent with
your time and budget constraints and personal learning preferences. Visit ni.com/
skills-guide to see these custom paths.
NI offers courses in several languages and formats including instructor-led classes at

facilities worldwide, courses on-site at your facility, and online courses to serve your
individual needs.
Technical SupportSupport at ni.com/support includes the following resources:
Self-Help Technical ResourcesVisit ni.com/support for software drivers and

updates, a searchable KnowledgeBase, product manuals, step-by-step troubleshooting
wizards, thousands of example programs, tutorials, application notes, instrument
drivers, and so on. Registered users also receive access to the NI Discussion Forums
at ni.com/forums. NI Applications Engineers make sure every question submitted
online receives an answer.
Software Support Service MembershipThe Standard Service Program (SSP) is a

renewable one-year subscription included with almost every NI software product,
including NI Developer Suite. This program entitles members to direct access to
NI Applications Engineers through phone and email for one-to-one technical support,
as well as exclusive access to online training modules at ni.com/
self-paced-training. NI also offers flexible extended contract options that
guarantee your SSP benefits are available without interruption for as long as you need
them. Visit ni.com/ssp for more information.
Declaration of Conformity (DoC)A DoC is our claim of compliance with the Council
of the European Communities using the manufacturers declaration of conformity. This
system affords the user protection for electromagnetic compatibility (EMC) and product
safety. You can obtain the DoC for your product by visiting ni.com/certification.
For information about other technical support options in your area, visit ni.com/services,
or contact your local office at ni.com/contact.
You also can visit the Worldwide Offices section of ni.com/niglobal to access the branch
office websites, which provide up-to-date contact information, support phone numbers, email
addresses, and current events.
C-4
ni.com

Ni Sbrio-9651: System On Module

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Ni Sbrio-9651: System On Module

Transféré par

Droits d'auteur :

Formats disponibles

NI sbRIO-9651

End-User License Agreements and Third-Party Legal Notices

U.S. Government Restricted Rights

EtherCAT is a registered trademark of and licensed by Beckhoff Automation GmbH.

Export Compliance Information

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

NI sbRIO-9651 System on Module Carrier Board Design Guide

About This Document

Molex 45971-4185 320-pin, 8 40 position, SEARAY

Connector family used for the J1 connector on the sbRIO-9651 SOM.

Physical, electrical, addressable, and logical entity that is attached to

USB Device port

USB Host port

About This Document

Table 1. sbRIO-9651 SOM Terminology in This Document (Continued)

In compliance with the Low-Voltage Transistor-Transistor Logic

In compliance with the Low-Voltage Complementary Metal Oxide

Pull-up During Configuration

The temperature reported digitally by a sensor that measures the die

The temperature reported digitally by a sensor on the Xilinx Zynq SoC

The temperature reported digitally by a sensor on the SEARAY side

NI sbRIO-9651 System on Module Carrier Board Design Guide

Off-page symbol that represents communication to and from the mating

Refers to an unpopulated reference designator.

About This Document

Additional Documentation Resources

What Would You Like to

NI sbRIO-9651 System on Module

NI sbRIO-9651 System on Module

Designing a carrier board

NI sbRIO-9651 System on Module

LabVIEW Help (NI-RIO)

Creating a socketed CLIP that defines the

NI Single-Board RIO CLIP

NI Training and Support

PDF available online at ni.com/manuals

Help file available locally

Included in the shipping kit

Available online at ni.com

Fixed Behavior Signals

Primary Ethernet (GBE0)

USB Host/Device (USB0)

USB Host (USB1)

UART/Console Out (Serial1)

RTC Battery (VBAT)

Primary Ethernet (GBE0)

Fixed Behavior Signals

GBE0 Signal Definitions

Speed LED signals.

I/O direction is with respect to the sbRIO-9651 SOM.

GBE0 Implementation on the Reference Carrier Board

NI sbRIO-9651 System on Module Carrier Board Design Guide

Reference Schematic Design Considerations

MDI data pairs

The LED signals can be used to directly drive connector LEDs.

Gigabit Ethernet Magnetic Requirements

Table 1-3 lists recommended magnetic characteristics.

100 mV, 100kHz, 8 mA

Insertion loss (max)

0 MHz to 100 MHz

Fixed Behavior Signals

sbRIO-9651 SOM PHY

Reference carrier board