EXPERIMENT-3

DIGITAL LOGIC GATES

GATES OF 74XX SERIES
OR GATE-7432

D STM 3

S 1

I m p le m e n t a t io n = C
D STM 4

S 1

U 1A

1
V

Q
V

7432

I m p le m e n t a t io n = D

A 0
B 1
Q 1

0s

0.25us

0.50us
Time

0.75us

NOTE:
We observe a propagation delay of 10ns

AND GATE-7408

D STM 3

S 1

I m p le m e n t a t io n = C
D STM 4

S 1

I m p le m e n t a t io n = D

0
V

U 2A
3

2
7408

Q0
V

1.00us

A 1
B 1
Q 1

0s

0.5us

NOTE:
We observe 2 propagation delays
1) High-to-Low Propagation Delay Tphl
2) Low-to-High Propagation Delay Tplh
So average propagation delay tp = (Tphl + Tplh)/2

NAND GATE-7400

1.0us
Time

1.5us

2.0us

A 1
B 1
Q 0

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

1.25us

1.50us

1.75us

2.00us

Tphl = 6.34 ns
A 0
B 0
Q 1

0s

0.25us

0.50us

0.75us

1.00us
Time

Tplh = 11.11 ns

NOT GATE-7404

A 1
Q 1

0s

0.5us

1.0us
Time

Tphl = 7.94 ns

1.5us

2.0us

A 0
Q 1

0s

0.5us

1.0us
Time

1.5us

Tplh = 12.69 ns

VARIOUS GATES USING UNIVERSAL NAND GATE:

NOT GATE USING NAND GATE:

2.0us

A
Q

0s

0.5us

1.0us
Time

1.5us

2.0us

AND GATE USING NAND GATE:

A
B
Q

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

OR GATE USING NAND GATE:

A
B
Q

0s

0.25us

0.50us

0.75us

NOR GATE USING NAND GATE:

1.00us
Time

1.25us

1.50us

1.75us

2.00us

A
B
Q

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

Ex-OR GATE USING NAND GATE:

A
B
Q

0s

0.25us

0.50us

0.75us

VARIOUS GATES USING UNIVERSAL NOR GATE:

NOT GATE USING NOR GATE:

A
Q

0s

0.25us

0.50us

0.75us

AND GATE USING NOR GATE:

1.00us
Time

1.25us

1.50us

1.75us

2.00us

A
B
Q

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

OR GATE USING NOR GATE:

A
B
Q

0s

0.25us

0.50us

NAND GATE USING NOR GATE:

A
B
Q

0s

0.25us

0.50us

0.75us

Ex-OR GATE USING NOR GATE:

1.00us
Time

1.25us

1.50us

1.75us

2.00us

A
B
Q

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

1.00us
Time

1.25us

1.50us

1.75us

2.00us

APPLICATION:
HALF ADDER USING NAND GATE:

A
B
s
c

0s

0.25us

0.50us

0.75us

HALF ADDER USING NOR GATE:

A
B
S
C

0s

0.25us

0.50us

0.75us

1.00us
Time

1.25us

1.50us

1.75us

DISCUSSION:
1. WHY CALLED HALF ADDER?
2. DIFFERENCE BETWEEN HALF ADDER USING NAND GATE AND NOR GATE?
3. IS THERE ANY SPECIFIC RELATION BETWEEN Tphl AND Tplh ?
4. NAME OF UNIVERSAL GATES?
5. WHAT IS TTL LOGIC?
6. TABULATION AND COMPARATIVE STUDY OF VARIOUS GATES?
7. HOW TO SELECT LOGIC GATES FOR YOUR APPLICATION?

CONCLUSION:

2.00us

IC INFORMATION:
IC NUMBER
7400
7404
7408
7432

DESCRIPTION
Quad 2-Input NAND Gates
14 pin IC
Hex Inverting Gates
16 pin IC
Quad 2-Input AND Gates
14 pin IC
Quad 2-Input OR Gates
14 pin IC

LOGIC TYPE
TTL
TTL
TTL
TTL

NOTE:
74 Indicates that it is TTL type and also shows the temperature range
(COMMERCIAL TEMPARATURE RANGE)
Pin 7-Gnd
Pin 14-Vcc

Commercial: 0C to 85C

Industrial: 40C to 100C

Automotive: 40C to 125C

Extended: 40C to 125C

Military: 55C to 125C

IMPORTANT UNDERSTANDINGS:

IMPORTANT PARAMETERS FOR GATES:

Switching speed
Power dissipation
Delay time
Supply voltage
While selecting logic gate ics for our requirement we choose it the basis of the
above measuring standards

DIFFERENT TECHNOLOGY:
RTL

DDL
DTL
TTL-7400 series
CMOS-4000 series

APPLICATION:
Half adder
Full adder
Encoder
Decoder
Multiplexer
Demultiplexer

USEFUL LINKS:
https://en.wikipedia.org/wiki/7400_series