IEEE-International Conference on Recent Trends in Information Technology, ICRTIT 2011

MIT, Anna University, Chennai. June 3-5, 2011

PCFICH Channel Design for LTE using FPGA

S. Syed Ameer Abbas#1, R. Lakshumi Praba#2, S.J.Thiruvengadam#3,1Assistant Professor, 2PG Student, 3Professor
#

Department of Electronics and Communication Engineering,

Mepco Schlenk Engineering College, Sivaksi-626005, India
3
Thiagarajar College of Engineering , Madurai- 625015, India
1,2

abbas_mepco@yahoo.com
lakshumipraba@gmail.com
3
sjtece@tce.edu

Channel(PHICH)[1].The first three channels are the data

channels. The PDSCH carries the payload and PBCH
broadcast the cell specific information. The PMCH is used for
broadcasting and multicasting information from multiple cells.
The latter three channels are the control channels, where
PDCCH is the main control channel carrying the downlink
scheduling assignments and the uplink scheduling grants. The
PCFICH carries the control Format Indicator(CFI), which
provides the number of OFDM symbols used by the PDCCH
channel. The PHICH carries the hybrid ARQ ACK/NACK
Indicator(HI). The downlink physical signals are Reference
signal and the Synchronization signal. The reference signals
are of three types namely Cell Specific reference signals,
MBSFN reference signals, UE-specific reference signals. The
synchronization signals are primary synchronization signal
and secondary synchronization signal and they provide the
information of physical layer cell identity, which ranges from
0 to 503[1].

Abstract Realization of transmitter and Receiver architecture

for LTE is the major research work being carried out by
implementation experts. There are four Control channels
available in LTE for both uplink and downlink. The uplink
control channel is PUCCH. The downlink control channels are
PDCCH,PCFICH and PHICH. The Physical Control Format
Indicator Channel(PCFICH)
is one among the downlink
physical control channel and it carries the number of OFDM
symbols used by the PDCCH channel, denoted as Control
Format Indicator(CFI).These control channels play a key role in
the correct decoding of the payload information. The CFI is the
first information received by the User and so is important for the
system performance. In this paper, the realization of
architecture for the PCFICH are done using FPGA, where the
main aim is to estimate the CFI correctly in the receiver side. The
simulations are done using Modelsim and are implemented in
Xilinx Spartan 3E kit.
Keywords LTE, FPGA, CFI

I. INTRODUCTION
Long Term Evolution (LTE) is a Fourth generation
wireless broadband technology, which is capable of providing
high peak data rates (100 Mbps downlink and 50 Mbps
uplink),multi antenna support, reduced cost, wide range of
bandwidth(from 1.4 MHZ upto 20 MHZ),backward
compatibility with existing 2G and 3G networks, increased
spectrum efficiency and peak data rates at cell edges[1-3]. All
these criteria are satisfied by the efficient usage of the control
channels. The LTE physical layer is a highly efficient means
of conveying both data and control information between an
enhanced base station(e-Node B) and mobile user
equipment(UE). The LTE physical layer uses OFDM as the
access technology, QAM as the modulation scheme and
MIMO concepts. LTE differs from its predecessors by using
OFDM along with MIMO antennas. OFDM is selected ,owing
to its suitability for MIMO transmission and reception,
resistance of its symbol structure to multi path delay spread,
no need of equalization etc[4].
The downlink physical channels correspond to a set of
resource elements carrying information originating from the
higher layers. There are six physical downlink channels
available namely, Physical Downlink Shared Channel
(PDSCH), Physical Broadcast Channel(PBCH), Physical
Multicast Channel (PMCH), Physical Control Format
Indicator Channel (PCFICH), Physical Downlink Control
Channel (PDCCH), Physical Hybrid ARQ Indicator

978-1-4577-0590-8/11/$26.00 2011 IEEE

58

One radio frame Tf=10ms

One slot Tslot=0.5ms
0

....................................

18

19

One sub frame

Fig. 1 Type I (FDD) frame structure

LTE supports both Time Division (TDD) and Frequency

Division Duplexing (FDD). In this paper FDD is adopted. The
frame structure for FDD used in this realization is shown in
Fig.1. Each downlink frame lasts for 10 ms and consists of 10
sub frames. Each sub frame consists of 2 slots. Each slot
consists of seven OFDM symbols [1].LTE specification
provides capacity enhancing features such as link adaptation ,
Hybrid Automatic Repeat Request(H-ARQ) etc. So, control
channel design and structure plays a lead role in the correct
detection and interpretation of the payload information.
Hence, successful decoding of the control channels is needed
to ensure the overall link and system performance[4].
The objective of this paper is to propose transmitter and
receiver architecture for PCFICH channel and to implement
the architectures using FPGA. The proposed architectures can

IEEE-ICRTIT 2011
be optimized using VLSI DSP techniques of Folding,
Unfolding, Retiming etc.
The rest of the paper is organized as follows. In Section II,
a brief discussion of PCFICH channel is done, followed by
block diagram and modelling of the transmitter and receiver
architecture is done. In Section III, assumptions are provided
and the architectures for the PCFICH transmitter and receiver
are proposed. Section IV, provides the simulation results and
discussion. Section V, contains some concluding remarks.
II. PHYSICAL CONTROL FORMAT INDICATOR CHANNEL
The PCFICH carries the information of number of
OFDM symbols used by the PDCCH to carry the scheduling
assignments and other control information. The information
carried by the PCFICH is called as Control Format Indicator
(CFI) and is located in the first OFDM symbol of each
subframe. The CFI can take the values of 1,2,3 and
4(Reserved) and are represented using two bits. For
bandwidths greater than ten resource blocks, number of
OFDM symbols used to contain the downlink control
information is the same as the actual CFI value. Otherwise
span of the downlink control information is CFI+1 symbols.
The exact position of CFI in the resource grid is based on the
bandwidth and physical layer cell identity. The CFI is the first
information received by the user equipment and so the overall
performance depends on the correctness of CFI detection.
CFI

Transmitter

Block Coding

Scrambling

Mapping to RE

Pre coding

QPSK
Modulation

demapped from the resource elements, decoded and delayer

mapped and then CFI is detected using Maximum Likelihood
method.

A. PCFICH Transmitter
1) Block Coding: The original CFI value to be transmitted
is first represented in two bit format R1,R0 (01-->1,10-->2,11->3).The CFI is first encoded using a (32,2) block code, as
shown in TABLE I. The dmin between the code words is 21[5]. In
order to ensure high robustness, PCFICH use this type of
encoding.
TABLE I
CFI (32,2) Block Code

CFI
1
2
3
4
(Reserved)

2)Scrambling: The 32 bit code words are bit wise XOR ed

with a cell specific scrambling sequence, which is a pseudo
random sequence generated using a length 31 gold sequence
generator. The cell specific sequence is used for the purpose
of inter-cell interference rejection. When a UE descrambles a
received bit stream with a known cell specific scrambling
sequence, interference from other cells will be descrambled
incorrectly and will only appear as uncorrelated noise. The
scrambling is done using

Layer Mapping
~ (q )

b
Channel

CFI

CFI codeword < b0, b1, , b31 >

<0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1
,0,1,1,0,1>
<1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1
,1,0,1,1,0>
<1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0,1,1,0
,1,1,0,1,1>
<0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0>

Demapping
from RE

Decoding

ML Detection

Delayer
mapping

(i ) = (b (q ) (i ) + c (q ) (i ))mod 2 (1)

Where q represents the codeword, c is the gold sequence used,

b is the encoded sequence. The gold sequence is generated
using the formula

x1(n + 31) = ( x1(n + 3) + x1(n)) mod 2 (2 )

x2(n + 31) = ( x2(n + 3) + x2(n + 2) + x2(n + 1) + x2(n)) mod 2 (3)

Receiver

c(n) = ( x1(n) + x 2(n)) mod 2 (4)

Fig. 2 Block Diagram

The block diagram for PCFICH channel is shown in

fig.2.In the transmitter side, the CFI(1,2 or 3), is first block
coded to produce 32 bit codeword. Then it is scrambled using
a gold sequence and then QPSK modulated. The modulated
symbols are then layer mapped and precoded. Then they are
mapped to the Resource Elements (RE) and passed through
the channel. In the receiver side, the complex symbols are

59

3) Modulation: The scrambled sequence is then QPSK

modulated to create a block of modulated symbols. The
scrambled bits are stored in a shift register and first two bits
are given as control lines for the multiplexer. Based upon the
control, the corresponding modulated symbols, stored in RAM
table appear as output. In QPSK modulation pairs of bits are
mapped to complex valued modulation symbols I+jQ,as
shown in Table II and hence the 32 bits are converted to 16

PCFICH Channel Design for LTE using FPGA

TABLE II
QPSK MODULATION

b(i),b(i+1)

2)CFI Estimation: The ML decision rule, by maximizing

the log-likelihood function of y k given hk is given in eqn(6)

00

01

10

11

CFI = min

m =1, 2,3

k =1

which simplifies to
CFI = arg max z (m )

2
2

.. .

(6)

...

(7)

m =1, 2,3

Where the soft outputs are given by

complex modulated symbols. The outputs are represented by

16 bit numbers.

z (m ) =

z(

m)
k

for m=1,2,3.

...

(8)

k =1

Which is simplified as

4) Mapping To Resource Elements: The control channels

modulated symbols are mapped to the resource element
groups(REG), and PCFICH is mapped only in the first OFDM
symbol of each subframe and are transmitted through the
channel. In order to obtain the largest possible frequency
diversity gain, the 16 symbols are distributed in four REGs,
evenly distributed in six resource blocks.

Re{ y
K

CFI = arg max

m =1, 2,3 k =1

5) Channel Estimation and Noise addition: To model the

channel, the modulated output is element by element
multiplied with the channel estimation vector, which is
represented as a 16 bit 16X1 vector. The resultant is a 32 bit
16X1 vector. Then the noise, which is represented as a 16 bit
16X1 noise vector is added .The resultant is a 32 bit 16X1
vector, which also denotes the received subcarrier vector at
the antennas in the receiver side. The transmitter architecture
is presented in fig. 3.

B. PCFICH Receiver
1)Received Signal: In the receiver side, after removal of
cyclic prefix from the received signal, then FFT is performed
and then resource element de mapping is done. The complex
valued output at the k -th receive antenna is modelled in
eqn.(5)
k = 1,2,!, K
(5)
y k = hk d ( n ) + u k ,
where, y k is 16x1 received subcarrier vector, d (n ) is the 16x1
complex QPSK symbol vector corresponding to the 32- bit
CFI code words, where n varies from 1 to 3, hk is 16x1
complex channel frequency response and u k represents the
contribution of thermal noise and interference. The received
signal y k is represented in the Fig. 2,for single antenna case.
The noise term u k is modelled as zero mean circularly
symmetric
complex
Gaussian
with
covariance
E u k u kH = u2 I , since the interferers are uncorrelated due to
independent large scale propagation, short term fading and
uncorrelated scrambling sequences.

y k hk d (m )

60

*
(m )
k hk , d

...

(9)

The received signal y k is element by element multiplied with

the conjugate of the complex channel frequency response
vector hk* .Then this term and three possible values of d (m )
undergoes inner product. The inner product is given by
N

x, y =

x y
i

*
i .The

real part of the resultant value is taken.

i =1

This is done for number of times as the number of antennas

used to receive. Then argument max among the three values is
selected as the CFI value. If CFI is maximum value when
m=1, then the codeword detected is 01, when m=2, it is 10
and when m=3, it is 11.
III. PROPOSED ARCHITECTURE FOR PCFICH TRANSMITTER
AND RECEIVER
TABLE III
ASSUMPTIONS

Parameter
Channel Bandwidth (MHz)
Number of Physical Resource
Blocks
Sampling Frequency(Msps)
Number of occupied subcarriers
Cyclic Prefix
Number of OFDM symbols per sub
frame
Frame Structure
CFI(bits)
Gold Sequence(bits)
dmin between CFI code words (bits)
Modulated Symbol(bits)
Channel
channel
frequency
response
vector(hk)
Conjugate of channel frequency
response vector(hk*)
Noise vector(uk)

Assumption
1.4
6
1.92
73
Normal
14 (7 in each slot)
Type I(FDD)
2
32
21
16
Rayleigh fading
16 bit 16X1 vector
16 bit 16X1 vector
16 bit 16X1 vector

IEEE-ICRTIT 2011
A. Transmitter Architecture
Z1
STA1

R1

Z2

R0

X1

Re + j Im

Change (-j)
STA4

X2
STA3

Z3

Re + j Im

Change (-Re)
STA2

SFA1

Z4

Re + j Im

Change (-j)

Z5

Re + j Im

Change (-Re)

SFA7
SFA5

SFA3

..

SFA10

29

Z6

30
31

31

Re + j Im

Change (-j)

SFA16

31
SFA14

Z7

Re + j Im

Change (-Re)
SFA11

hk

31

30

..

..

..

..

Precoding

1 2 + j1 2

1 2 j1 2
1 2 + j 1 2

14

14

1 2 j 1 2

15

15

Frame

Slots
Memory buffers to store

7
15

14

...

31

30

...

16 QPSK sym.
yk

31

Layer
mapping

30

...

Z1

00-1ant

Z2,Z3

01-2ant

Z4,Z5,Z6,Z7

10-4ant

Parallel to
Serial

IFFT

Cyclic
Prefix

Mapping to Resource Elements

M
U
X

Fig. 3 Transmitter Architecture upto Layer Mapping

The transmitter architecture is presented in Fig.3.The

transmitter architecture consists of Block Coding, Scrambling,
Modulation and layer mapping. The input is the 2 bit CFI
value R1, R0.The 2 bit value is converted to 32 bit value by
block coding. The first two bits are same as the original bits
and the third bit is the XOR value of the first two bits. The 3
bit pattern is repeated until the required 32 bits are obtained.
These 32 bits form the CFI codeword. For scrambling process,
gold sequence generation is needed. The gold sequence is
produced by using the 2 sequences X1 and X2.The X1
sequence
is
a
predefined
sequence,
which
is
1000000000000000000000000000000. The 31 bits of X2
sequence is assumed, since it varies according to the

61

Fig. 4 Transmitter Architecture for Precoding, Mapping to resource elements

applications. The 32nd bit of both the sequences are calculated

using the formula in section II. Then these 2 sequences are
XOR ed to get the gold sequence, which is also a 32 bit value.
Here all the mod 2 addition operations are replaced with XOR
operation, since both produce same results. XOR operation
increases the speed of process. Then scrambling is done by
XOR of the block coded sequence and the gold sequence. The
resultant scrambled sequence is stored in a shift register. The

PCFICH Channel Design for LTE using FPGA

shift register is set to shift 2 bits per clock cycle for QPSK
modulation. The shifted 2 bits are given as control lines for
the multiplexer. The inputs to the multiplexer are stored in
RAM table. The 4 possible complex modulated QPSK
symbols are shown in Fig. 2. Based on the control, the output
appears, which is represented as 16 bit value.
The16 complex modulated symbols are then layer mapped
to one, two or four layers based on the information from
higher layer.Z1 is the output if one antenna is selected.Z2,Z3
are outputs if 2 antennas are selected and Z4,Z5,Z6,Z7 if 4
antennas are selected. These symbols are then precoded as
shown in Fig. 4.For single antenna case, output will be
streamed without any change. For 2 and 4 antenna cases, first
incoming symbol is multiplied with 1 / 2 .Then the original
symbols and the conjugate signals are produced by sign
change, and are arranged in the order to be transmitted. Then
each layer or antenna produces a resource grid structure
carrying the symbols. The modulated symbol is multiplied
with the complex channel frequency response vector hk, which
is also represented as a 16 bit value. The resultant is a 32 bit
value. Then noise which is represented using 16 bits is added.
Thus the resultant signal yk is a 32 bit value.

are done using Verilog HDL. The simulation results and the
device utilization summary, assuming that the channel
response is known are presented in this section.
Decoding
Z1

From
Resource
grids

Re+jim

Change(j)

Error
detection

Change(j)

Error
detection

Z3

Re+jim

Change(j)

Error
detection

Z4

Re+jim

Re+jim

Change(j)

Error
detection

Re+jim

Change(j)

Error
detection

Re+jim

Change(j)

Error
detection

z4,z5,z6,z7 z2,z3

R1

B. Receiver Architecture
The received signal is first demapped from the resource
elements in the grid. Only in 16 positions of first OFDM
symbol, CFI value is available. Decoding is done to get the
original symbols, by selecting the strongest signals. The
delayer mapping is just retrieving back the 16 symbols in
order. The receiver architecture is presented in Fig. 5. The 16
received signals are used to estimate the CFI value
transmitted. It is known that, there are only three possibilities
of signal transmitted, namely 01,10 or 11(CFI-1,2 or 3).So,
the demodulated signal will be one among the three, which is
used in the estimation of the CFI, by finding argument
maximum among three results. The received signal is yk and is
multiplied with the conjugate of the complex channel
frequency response vector hk*, element by element. Then this
resultant term undergoes inner product with the three possible
values of d(m). The three possible values are produced in the
same way as in the transmitter side. The inner product is done
using the formula in section II. The d(m)* is multiplied with
(yko hk*) product. For all the elements the multiplication is
done and the results are accumulated, and the result is a 64 bit
value. The real part of the accumulated value alone is taken,
which is a 32 bit value. This process is done for the three
values viz. d(0),d(1), d(2).Then among the three results, the
codeword which has the maximum argument value is detected
as the CFI.

R0

{}

Z7

z1

DeLayer
Mapping

{}

16 symb.

.
..
.

29
30
31

hk*

..
..

..
..

30

14

31

15

31

47

.. 1

46

d(m)*
31

30

0
1

2 + j1

2 j1

2 + j1

2 j1

..
..

MAC

14

Re| |

15

1
CFI 1

..
..

CFI 2
CFI 3

30
01
CFI

10
11

Count no.of
error bits and
find
minimum
error output

Fig 5: PCFICH Receiver Architecture

62

Z6

yk

IV. RESULTS AND DISCUSSION

The architecture for the PCFICH channel transmitter up to
mapping to resource elements and receiver to estimate CFI are
designed and implemented in FPGA. The simulations are
done using Modelsim and synthesized using Xilinx 8.1i and
Spartan 3E kit is used for implementation. The programming

Z5

ctrl

31

Z2

o/p 1
o/p 2
o/p 3

31

IEEE-ICRTIT 2011
For the transmitter side, the inputs are clock and the two bit
CFI value (01,10 or 11). In fig.6,two bit CFI input is given.

them,14 are 16X16 multipliers,1is 32X16 and 3 are 48X16

multipliers.20 adder/subtractors are used and delay incurred is
30.26 ns.
TABLE IV
FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH TRANSMITTER FOR
THE XILINX SPARTAN 3E ,3S500EFT256-4 DEVICE

Number of slices

582 / 4656 (12%)

Number of Slice Flip Flops

Number of 4 input LUTs
Max. Frequency
Delay(min. period)

616 /9312 ( 6% )
714 / 9312 (7% )
59.830MHz
16.714ns

Total memory usage

143284 kilobytes

TABLE V
FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH RECEIVER FOR THE
XILINX SPARTAN 3E ,3S500EFT256-4 DEVICE

Number of Slices
Number of Slice Flip Flops
Number of 4 input LUTs
Number of MULT18X18SIOs
Max.Frequency
Delay(Min.period)
Total memory usage

Fig.6 Simulation for PCFICH transmitter

The block coding produces 32 bit output, which on scrambling

produces 32 bit output. The modulated symbols are
represented using 16 bits. In simulation, the output is available
at 1600ps. From the synthesis report, the number of
multipliers used is one, which is a 16x16-bit multiplier. The
adders used are one 16-bit carry out adder and one 32-bit
adder. The number of comparators used is five. The symbols
are then layermapped, precoded and mapped to resource
elements. The delay incurred in the transmitter is 16.714ns.

494 /4656 (10% )

322 / 9312 ( 3%)
883 / 9312 (9% )
11 / 20 ( 55% )
33.047MHz
30.260ns
168372 kilobytes

Table IV gives the FPGA resource utilization summary for

the transmitter architecture and the Table V gives the FPGA
resource utilization summary for the receiver architecture.
V. CONCLUSION
The transmitter and receiver architectures for the Physical
Control Format Indicator Channel are proposed in this paper.
The signal to be transmitted is produced, passed through
channel and noise is added. The addition operations in the
existing scheme are replaced by XOR, to increase the speed of
the process. In the receiver side, the CFI is estimated by
maximum likelihood method. The simulations are done and
the device utilization are studied. The simulations are done
using Modelsim. The synthesis are done using Xilinx 8.1i and
implementation is done in Spartan 3E kit. In the transmitter,
implementation is done upto mapping to resource elements
and in receiver, CFI is estimated. The proposed architectures
can be further improved by using VLSI DSP techniques.
REFERENCES
[1]

Fig.7 Simulation for PCFICH receiver

In fig. 7,the received symbols are demapped from resource

grid. The modulated output undergoes multiplication with
input which again undergoes inner product with the modulated
output. The elements, decoded and delayer mapped. In the
receiver side, for all the three possible codewords 01,10,11 the
modulated real part of the output alone is extracted. The three
values are compared and the one with argument max is
selected as CFI. In simulation, the output is available at
400ps.From the synthesis report, 18 multipliers are used. Of

63

[2]
[3]
[4]

[5]

3GPP TS36.211,Evolved Universal Terrestrial Radio Access(EUTRA);Physical Channels and Modlation(Release 8).
3GPP TS36.212,Evolved Universal Terrestrial Radio Access(EUTRA);Multiplexing and Channel Coding(Release 8).
3GPP TS36.306,Evolved Universal Terrestrial Radio Access(EUTRA);User Equipment radio access capabilities (Release 8).
S. J. Thiruvengadam, Louay M. A. Jalloul, Performance Analyis of the
3GPP-LTE Physical Control Channels, EURASIP Journal onWireless
Communications and Networking,vol.2010,Article ID 914934, 10
pages,Nov.2010
R.Love, R.Kuchibhotla, A.Ghosh et al.,Downlink control channel
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