Lecture 2!

ECEN 4517/5517

Upcoming assignments due:

Exp. 1 final report due in D2L dropbox by 5:00 pm Friday Jan. 29
Exp. 3 part 1 prelab assignment due in D2L dropbox by Tuesday
Feb. 2 at noon

This week: Exp. 2 Introduction to MSP 430

Lab kits are available in ECEE Electronics Store, ECEE
1B10
You will need this kit to perform Exp. 2.
You will also need an oscilloscope probe and possibly other small
parts (capacitors) from the undergraduate electronics lab parts kit.
ECEN 4517

Last weeks Exp. 1

The solar resource: direct radiation (red) and
global radiation (green)

Exp. 1 final reports are due in D2L dropbox

by 5:00 pm on Friday
One report per group, with names of
a group members on page 1
See rubric in D2L dropbox for how
Exp. 1 report will be graded
Dropbox will close at 5:00 pm sharp
ECEN 4517

Wed

Thurs

Lab reports
One report per group. Include names of every group
member on first page of report.
Report all data from every step of procedure and
calculations. Adequately document each step.
Discuss every step of procedure and calculations
Interpret the data
It is your job to convince the grader that you understand
what is going on with every step
Regurgitating the data, with no discussion or interpretation,
will not yield very many points
Concise is good

See Exp. 1 rubric

ECEN 4517

Upcoming weeks:!
Design and build MPPT system
Exp. 3: DC-DC converter

Exp. 2:
introduction to
MSP430
microcontroller
ECEN 4517

Experiment 2!

MSP430F51x1
MSP430F51x2

Introduction to MSP 430F5172 Microcontroller

www.ti.com

SLAS619G AUGUST 2010 REVISED AUGUST 2012

Functional Block Diagram, MSP430F51x2

Clocks: ACLK,
SMCLK, MCLK

Programmable multi-use I/O ports (31)

DVCC
AVCC
RST/NMI
DVSS
AVSS

XIN XOUT

Up to
25 MHz
@3.3V
CPU:
16 bit

Unified
Clock
System

ACLK

SMCLK

DVIO
DVSS

32KB
16KB
8KB

2KB
2KB
1KB

Power
Management

Flash

RAM

LDO
SVM/SVS
Brownout

P1.x
8

P2.x
8

P3.x
8

PJ.x
7

SYS

I/O Ports

I/O Ports

I/O Ports

I/O Ports

Watchdog

P1
8 I/Os
2x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors

P2
8 I/Os
8x 5V 20mA
Interrupt
and Wakeup
Pullup/down
Resistors

P3
8 I/Os
2x 5V 20mA

PJ
7 I/Os

Pullup/down
Resistors

Pullup/down
Resistors

Port
Mapping
Controller

MCLK

CPUXV2
and
Working
Registers

3 DMA
Channel

EEM
(S: 3+1)
TD0
JTAG/
SBW
Interface

TA0
MPY32

32-bit

Timer_A
3 CC
Registers

COMP_B

USCI
Timer_D
Timer_D
256 MHz
256 MHz
A0: UART,
3 CC
3 CC
IrDA, SPI
Registers
Registers
With Buffer With Buffer
EventControl EventControl B0: SPI, I2C

Timer D (2)

Functional Block Diagram, MSP430F51x1

multiplier
Timer A (1)
ECEN 4517
XIN XOUT

TD1

DVCC
AVCC
RST/NMI
DVSS
AVSS

DVIO
DVSS

ADC10_A
10 Bit
200 KSPS
9 Channels

10-bit
A/D

5
P1.x
8

P2.x
8

16 Channels
High,
Medium, and
Ultralow
Power
Modes

REF
Voltage
Reference

Analog
comparator
P3.x
8

CRC16

PJ.x
7

Voltage
reference

MSP430F5172: Resources
MSP430F5172 Users Guide

The primary resource for operation and programming of on-chip

peripherals (PWM, ADC, etc.)
Linked to Exp. 2 web page, 1147 page pdf

MSP430F5172 Data Sheet

Describes pinouts, specifications
Linked to Exp. 2 web page, 103 page pdf

Code Composer Studio 5.3

Development system for MSP430; program in C

On lab computers: free 32 kB limited version

Library of Examples

ECEN 4517

Accessible within Code Composer Studio, also linked to web page

Many programming examples for each peripheral
Use directory of examples for 430F5172 chip
Also: Ericksons sample code main.c linked to Exp. 2 web page
6

Microcontroller Pinouts
www.ti.com

MSP430F51x1
MSP430F51x2

SLAS619G AUGUST 2010 REVISED AUGUST 2012

ADC inputs

A0 to A5, A7, A8
Pin Designation, MSP430F51x2IDA and MSP430F51x1IDA

to LED (P1.0 output)

AVCC
Px.y is digital I/O
PJ.4/XOUT
PJ.5/XIN
AVSS
P1.0/PM_UCA0CLK/PM_UCB0STE/A0*/CB0
P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1*/CB1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2*/CB2
P1.3/PM_UCB0CLK/PM_UCA0STE/A3*/CB3
P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4*/CB4
P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5*/CB5
PJ.0/SMCLK/TDO/CB6
PJ.1/MCLK/TDI/TCLK/CB7
PJ.2/ADC10CLK/TMS/CB8
programmer
PJ.3/ACLK/TCK/CB9
P1.6/PM_TD0.0
P1.7/PM_TD0.1
P2.0/PM_TD0.2
P2.1/PM_TD1.0
P2.2/
PM_TD1.1
* Only MSP430F51x2

JTAG

Timer D
PWM
outputs

38

37

36

35

34

33

32

31

9
10

DA PACKAGE 30
29
(TOP VIEW)

11

28

12

27

13

26

14

25

15

24

16

23

17

22

18

21

19

20

PM_TD0.x
PM_TD1.x
See also pins 20, 23-28, 33
ECEN 4517

P3.6/PM_TA0.1/A7*/VEREF-*-/CB11
P3.5/PM_TA0.2/A8*/VEREF+*/CB12
RST/NMI/SBWTDIO
TEST/SBWTCK
P3.3/PM_TA0CLK/PM_CBOUT/CB13
P3.2/PM_TD0.0/PM_SMCLK/CB14
PJ.6/TD1CLK/TD0.1/CB15
DVCC
DVSS
VCORE
P3.1/PM_TEC1FLT0/PM_TD1.2
P3.0/PM_TEC1FLT2/PM_TD1.1
P2.7/PM_TEC1CLR/PM_TEC1FLT1/PM_TD1.0
P2.6/PM_TEC0FLT1/PM_TD0.2
P2.5/PM_TEC0FLT0/PM_TD0.1
P2.4/PM_TEC0CLR/PM_TEC0FLT2/PM_TD0.0
DVSS
DVIO
P2.3/PM_TD1.2

Microcontroller default settings

Upon power-on reset (POR), the MSP430F5172 comes up with the
following conditions:
Watchdog timer is enabled
All pins are set to read state
Processor internal clock and core voltage are set to minimum
values. Default clock frequency = 1.045 MHz
Processor supply voltage is 3.3 V
Internal processor core operates at lower voltage; a programmable
internal voltage regulator reduces the 3.3 V to this lower voltage
Faster clock speeds require higher core voltages
Digital I/O pins can operate at 5 V if 5 V is supplied to DVIO pin.
Otherwise, these pins operate with 3.3 V logic levels

ECEN 4517

Development board!
in your kit
External
power

JTAG
(to computer)

Jumper:
Select power source
JTAG or external

Jumper:
Connect or disconnect
LED from P1.0

Reset button

Header:

Header:

Processor
pins 1-19

Processor
pins 20-38

Jumper:
Select digital I/O power
Internal 3.3 V or external 5 V
ECEN 4517

ww.ti.com NOTE:

2.4 Digital

All registers have word or byte register access. For a generic register ANYREG, the suffix
Digital I/O Registers
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"
I/O(ANYREG_H)
Registers refers to the upper byte of the register (bits 8 through 15).

The digital I/O registers are listed in Table 12-2. The base addresses can be found in the device-specific
data sheet. Each port grouping begins
at its12-2.
baseDigital
address.
address offsets are given in Table 12-2.
Table
I/O The
Registers

Peripherals are controlled by registers in

All registers have word or byte register access. For a generic register ANYREG, the suffix
addressable memory
"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"

Offset

Acronym

Register Name

Type

Access

Reset

Section

0Eh

P1IV

Port 1 Interrupt Vector

Read only

Word

0000h

Section 12.4.1

0Eh

P1IV_L
Byte15).
(ANYREG_H) refers to the upper byte of the registerRead
(bitsonly
8 through
P1IV_H
Read only
Byte

NOTE:

0Fh
1Eh
1Eh
Offset
1Fh
0Eh
00h
0Eh
02h
0Fh
1Eh
04h
1Eh
1Fh
06h
00h

08h
02h
0Ah
04h

00h
00h

P2IV
Port 2 Interrupt Vector
Read only
Word
0000h
Section 12.4.2
Example:
Port P1,
comprised
of eight
pins
P1.0
P1.7.
Digital
input/output
Table 12-2.
Digital
I/Olabeled
Registers
P2IV_L
Acronym
P2IV_H

Read only
Type only
Read

Byte
Access
Byte

00h
Reset
00h

Section

Read only
only
Read
Read only
Read/write
Read only

Word
Byte
Byte
Byte
Byte

0000h

Section 12.4.9
12.4.1
Section

Read input value

00h
undefined
00h

Section 12.4.10

Write output value

Port 2 Interrupt Vector

Port 1 Direction

Read only
Read/write
Read only

Word
Byte
Byte

0000h
00h
00h

Section 12.4.2
Section 12.4.11

Port 1 Resistor Enable

Port 1 Input

Read only
Read/write
Read only

Byte
Byte
Byte

00h
00h

Section 12.4.12
Section 12.4.9

Port 1 Drive Strength

Port 1 Output

Read/write
Read/write

Byte
Byte

00h
undefined

Section 12.4.13
Section 12.4.10

0 = input
1 = output
When input, 1 =
pullup/down
0 = reduced
1 = full drive
0 = off
1 = selected as
digital I/O

Register Name

P1IV
P1IN or
PAIN_L
P1IV_L

Port
Vector
Port 11 Interrupt
Input

P1OUT or
P1IV_H
PAOUT_L
P2IV
P1DIR or
P2IV_L
PADIR_L
P2IV_H
P1REN or

Port 1 Output

PAREN_L
P1IN
or
PAIN_L
P1DS or
PADS_Lor
P1OUT
PAOUT_L
P1SEL or

Port 1 Port Select

Read/write
Byte
00h
Section 12.4.14
PASEL_L
P1DIR
or
Port 1 Direction
Read/write
Byte
00h
Section 12.4.11
PADIR_L
18h
P1IES or
Port 1 Interrupt Edge Select
Read/write
Byte
undefined
Section 12.4.3
PAIES_L
06h
P1REN
or
Port
1
Resistor
Enable
Read/write
Byte
00h
Section
12.4.12
For further documentation, see MSP430x5xx/6xx Family User Guide, Ch
12,
pp. 406ff
PAREN_L
1Ah There
P1IE orare additional
Port 1 P1
Interrupt
Enable
Read/write
Byte
00h
Section
12.4.4
registers related toRead/write
interrupts.Byte
08h
P1DS
or
Port 1 Drive Strength
00h
Section 12.4.13
PAIE_L
PADS_L
1Ch TI P1IFG
or
Port 1 Interrupt
Flagsets up all registers
Read/writewith
Byte
00hvariableSection
12.4.5
provides
a header
file that
C code
names
assigned to
0Ah
P1SEL
or
Port 1 Port Select
Read/write
Byte
00h
Section 12.4.14
PAIFG_L
the
correct addresses, so you dont have to worry about it. Just add the following statement
PASEL_L
01h
P2IN or
Port 2 Input
Read only
Byte
Section 12.4.9
to P1IES
the beginning
of your
C code:
18h
or
Port
1 Interrupt
Edge Select
Read/write
Byte
undefined
Section 12.4.3
PAIN_H
PAIES_L
03h
P2OUT or
Port 2 Output
Read/write
Byte
undefined
Section 12.4.10
#include
<msp430f5172.h>
1Ah
P1IE
or
Port 1 Interrupt Enable
Read/write
Byte
00h
Section 12.4.4
PAOUT_H
PAIE_L
05h
P2DIR
Port 2 Direction
Read/write
Byte peripheral
00h
Section 12.4.11
This
fileoralso defines
constants that are useful
for setting
functions.
1Ch
P1IFG
or
Port 1 Interrupt Flag
Read/write
Byte
00h
Section 12.4.5
PADIR_H
10
ECEN
4517
PAIFG_L
07h
P2REN or
Port 2 Resistor Enable
Read/write
Byte
00h
Section 12.4.12
01h
P2IN
or
Port 2 Input
Read only
Byte
Section 12.4.9
PAREN_H
PAIN_H
09h
P2DS or
Port 2 Drive Strength
Read/write
Byte
00h
Section 12.4.13

Examples
Configure pin P1.0 to be a digital output, and toggle its value
P1DIR |= 0x01;

// OR the contents of register P1DIR with hex 01,

// forcing the first bit high
// This configures pin P1.0 to be an output

P1OUT ^= 0x01;

// EXOR the contents of P1OUT with hex 01,

// toggling the first bit
// This changes the state of logic output P1.0

Turn off the watchdog timer

WDTCTL = WDTPW + WDTHOLD;

ECEN 4517

// Sets the WDT control register WDTCTL to

// disable the watchdog timer function
// WDTPW and WDTHOLD are constants defined
// in the header file supplied by TIsee user guide

11

C code to toggle pin P2.2

#include <msp430f5172.h>

// TI-supplied header file

void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW + WDTHOLD;
P2DIR |= 0x04;
for (;;)
{
P2OUT ^= 0x04;
i = 10000;
do(i--);
while (i != 0);
}
}

// Stop watchdog timer

// Configure pin P2.2 to output direction
// infinite loop
// Toggle P2.2 output
// Wait 10000 counts

The above code will drive P2.2 (pin 19) with a low-frequency square wave.
The development boards have an LED connected to P1.0; if the above code
is modified to drive P1.0 then it will blink the LED.
ECEN 4517

12

Setting the core voltage!

and processor clock frequency
The processor contains a digitally controlled oscillator (DCO) whose
MSP430F51x1
frequency can be programmed.
MSP430F51x2
Although the MSP430F5172
is powered with a 3.3 V supply, the processor
SLAS619G AUGUST 2010 REVISED AUGUST 2012
core operates at a reduced voltage that can be programmed.

ECEN 4517

25
3
System Frequency - MHz

Lower core voltage means less

power dissipation but processor
clock frequency is limited.
At power-on reset: minimum
core voltage (level 0) and low
clock frequency (1.045MHz)
To operate at faster DCO
frequency, we must raise core
voltage one level at a time, then
raise clock frequency. After
each step, wait for circuitry to
stabilize.

20
2

2, 3

1, 2

1, 2, 3

0, 1

0, 1, 2

0, 1, 2, 3

16

12

0
1.8

2.0

2.2

2.4

3.6

Supply Voltage - V

13

The numbers within the fields denote the supported PMMCOREVx settings.

Figure 1. Frequency vs Supply Voltage

Sample Code!
Core voltage = level 3, processor frequency = 25 MHz
// Increase Vcore setting to level 3 to support fsystem= 25 MHz, one level at a time
SetVcoreUp (0x01);
// call subroutine SetVcoreUp: level0 to level1
SetVcoreUp (0x02);
// call subroutine SetVcoreUp: level1 to level2
SetVcoreUp (0x03);
// call subroutine SetVcoreUp: level2 to level3
// Initialize DCO to 25MHz
__bis_SR_register(SCG0);
// Disable the FLL control loop
UCSCTL0 = 0x0000;
// Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_6;
// Select DCO range 4.6MHz-88MHz operation
UCSCTL2 = FLLD_1 + 763;
// Set DCO Multiplier for 25MHz
// (N + 1) * FLLRef = Fdco: (762 + 1) * 32768 = 25MHz. Also set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0);
// Enable the FLL control loop
__delay_cycles(782000);
// wait for DCO to settle
// 32 x 32 x 25 MHz / 32,768 Hz = 782000 = MCLK cycles for DCO to settle; see user guide

ECEN 4517

14

Subroutine SetVcoreUp!
See sample C code, linked to Exp. 2 web page
void SetVcoreUp (unsigned int level)
{
// Subroutine to change core voltage
PMMCTL0_H = PMMPW_H;
// Open PMM registers for write
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Wait till SVM is settled
PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
// Clear already set flags
PMMCTL0_L = PMMCOREV0 * level;
// Set VCore to new level
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Wait till new level reached
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
PMMCTL0_H = 0x00;
// Lock PMM registers for write access
}
ECEN 4517

15

Operation of Timer D as a PWM

ECCN 5E002 TSPA Technology / Software Publicly Available

Timer_D Introduction

www.ti.com

TDAUXCLROUT

See MSP430x5xx/6xx Family User Guide,

Chapter 19

TDSSELx

IDx

IDEXx

00

Divider
/1/2/4/8

Divider
/1.../8

TDCLKMx

ACLK

15

01

00

TDHMx

10

TDHDx

0
16-bit Timer
RC
TDR
8 10 12 16
Clear

01

10
11

EQU0

00
01

7 5
TDAUXCLK
TDHCLKSRx
TDHCLKRx
TDHCLKTRIMx
TDCLR
TDCLR1

Group
Load Logic

Count
Mode
CNTLx

Divider /1/2/4/8
TDHREGEN High Resolution
Generator
TDCLGRPx

One timer block with 16 bit counter

Three capture/compare registers
(CCR0 CCR2)

10

Set TDIFG

11
CCR0*
CCR1

CCR5
CCR6
CCISx

High resolution mode with TDCLK

frequency = n*(DCO frequency)

CMx

logic

CCRx Block

COV
SCS

Use CCR0 to set switching frequency: fs

= (TDCLK freq)/(CCR0)
Use CCR1 and CCR2 to set duty cycles
of outputs: D1 = CCR1/CCR0 etc.
Need to configure Timer D, and write
values to set fs and duty cycle(s)
ECEN 4517

Timer Block

MCx
TDCLK

SMCLK

The MSP430F5172 has two Timer Ds

Each Timer D includes:

Timer Clock

16

CCI6A

00

CCI6B

01

GND

10

VCC

11

Capture
Mode

15
Sync

Timer Clock

TDCCR6

1
Load

CLLDx
Group
Load Logic

CCI
VCC
TDR=0
EQU0
UP/DOWN

Compare Latch TDCL6

00
01
10
11

Comparator 6

CCR5
CCR4

EQU6

CAP

CCR1
0

Set TDCCR6

CCIFG

TD6CMB
CH0EVNT
CH5EVNT

OUT

0
Output
Unit6

Set

Timer Clock

EXTCLR

Reset
POR
CH6EVNT

OUTMODx

Figure 19-1. Timer_D Block Diagram

EQU6

OUT6 Signal

Example: Configuring Timer D0 as a

PWM with 100 kHz switching frequency

// insert startup code to set DCO to 25 MHz, etc.

P1SEL |= BIT7;
// Configure P1.7 (pin 16)
P1DIR |= BIT7;
// (TD0.1 output)
P2SEL |= BIT0;
// Configure P2.0 (pin 17)
P2DIR |= BIT0;
// (TD0.2 output)
TD0CTL0 = TDSSEL_2;
// TDCLK is based on SMCLK = 25MHz
TD0CTL1 |= TDCLKM_1;
// Select Hi-res local clock for TD0
TD0HCTL0 = TDHM_0 + TDHCALEN + TDHEN; // Hi-res clock is 8 x TDCLK = 200MHz
// Calibration and Hi-res mode enable
TD0HINT |= TDHLKIE;
// Enable hi-res clock lock to TDCKL
TD0CCR0 = 2000;
// PWM freq = 200 MHz/2000 = 100 kHz
TD0CCTL1 = OUTMOD_7 + CLLD_1;
// CCR1 reset/set mode, buffered
TD0CCR1 = 1000;
// CCR1 duty cycle = 1000/2000 = 0.5
TD0CCTL2 = OUTMOD_7 + CLLD_1;
// CCR2 reset/set mode, buffered
TBCCR2 = 500;
// CCR2 duty cycle = 500/2000 = 0.25
TD0CTL0 |= TDCLR + MC_1;
// clear TDR, use up mode, start TD0

The TD0.1 and TD0.2 outputs will now continue to run at 100 kHz with duty cycles
of 0.5 and 0.25. Subsequent writes to TD0CCR1 or TD0CCR2 will cause the
output duty cycle to change at the next 100 kHz switching period.
ECEN 4517

17

Timer D!

ECCN 5E002 TSPA Technology / Software Publicly Available

Control Register TD0CTL0

Timer_D Registers

www.ti.com

19.3.1 TDxCTL0 Register

Timer_D x Control Register 0
Figure 19-24. TDxCTL0 Register
15

See MSP430x5xx/6xx Family User

Guide, Chapter 19, p. 535
C code:
TD0CTL0 = TDSSEL_2;

14

Reserved

13

12

TDCLGRPx

10

Reserved

8
TDSSELx

r0

rw-(0)

rw-(0)

rw-(0)

rw-(0)

r0

rw-(0)

Reserved

TDCLR

TDIE

TDIFG

r0

w-(0)

rw-(0)

rw-(0)

ID
rw-(0)

MCx
rw-(0)

rw-(0)

rw-(0)

rw-(0)

Table 19-9. TDxCTL0 Register Description

Bit

Field

Type

Reset

Description

15

Reserved

0h

Reserved. Always reads as 0.

14-13

TDCLGRPx

RW

0h

TDCLx group
00b = Each TDCLx latch loads independently.
01b = TDxCL1+TDxCL2 (TDxCCR1 CLLDx bits control the update)

This sets the Timer D clock source to

SMCLK (derived from processor clock
DCO)

TDxCL3+TDxCL4 (TDxCCR3 CLLDx bits control the update)

TDxCL5+TDxCL6 (TDxCCR5 CLLDx bits control the update)
TDxCL0 independent
10b = TDxCL1+TDxCL2+TDxCL3 (TDxCCR1 CLLDx bits control the update)
TDxCL4+TDxCL5+TDxCL6 (TDxCCR4 CLLDx bits control the update)
TDxCL0 independent
11b = TDxCL0+TDxCL1+TDxCL2+TDxCL3+TDxCL4+TDxCL5+TDxCL6
(TDxCCR1 CLLDx bits control the update)

TD0CTL0 is a variable associated with

this control register in the header file
msp430f5172.h
TDSSEL_2 is a constant defined in the
standard header file, having 01b as bits
9-8. The header file msp430f5172.h
defines such constants for every control
register field.
ECEN 4517

11
CNTLx

18

12-11

CNTLx

RW

0h

Counter length
00b = 16-bit, TDR(max) = 0FFFFh
01b = 12-bit, TDR(max) = 0FFFh
10b = 10-bit, TDR(max) = 03FFh
11b = 8-bit, TDR(max) = 0FFh

10

Reserved

0h

Reserved. Always reads as 0.

9-8

TDSSELx

RW

0h

Timer_D clock source select

00b = TDCLK
01b = ACLK
10b = SMCLK
11b = Inverted TDCLK

7-6

ID

RW

0h

Input divider. These bits, along with the IDEX bits in TDxCTL1, select the divider
for the input clock.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8

5-4

MCx

RW

0h

Mode control. Setting MCx = 00h when Timer_D is not in use saves power.
00b = Stop mode: Timer is halted
01b = Up mode: Timer counts up to TDCL0
10b = Continuous mode: Timer counts up to the value set by CNTLx (counter
length)
11b = Up/down mode: Timer counts up to TDCL0 and down to 0000h

Reserved

0h

Reserved. Always reads as 0.

TDCLR

0h

Timer_D clear. Setting this bit resets TDR, the TDCLK divider, and the count
direction. The TDCLR bit always read as zero.

SLAU208L June 2008 Revised January 2013

Submit Documentation Feedback

Copyright 20082013, Texas Instruments Incorporated

Timer_D

535

Timer D!

ECCN 5E002 TSPA Technology / Software Publicly Available

Control Register TD0HCTL0

Timer_D Registers

www.ti.com

19.3.8 TDxHCTL0 Register

Timer_D x High-Resolution Control Register 0
Figure 19-31. TDxHCTL0 Register

See MSP430x5xx/6xx Family User

Guide, Chapter 19, p. 543
C code:
TD0HCTL0 = TDHM_0 +
TDHCALEN + TDHEN;
This sets the TDHEN bit to enable
high resolution mode

15

14

13

12

ECEN 4517

10

8
TDHFW

r0

r0

r0

r0

r0

r0

r0

TDHRON

TDHEAEN

TDHREGEN

TDHEN

rw-(0)

rw-(0)

rw-(0)

rw-(0)

TDHDx
rw-(0)

TDHMx
rw-(0)

rw-(0)

rw-(0)

rw-(0)

Table 19-16. TDxHCTL0 Register Description

Bit

Field

Type

Reset

Description

15-9

Reserved

0h

Reserved. Always reads as 0.

TDHFW

RW

0h

High-resolution generator fast wakeup enable

0b = High-resolution generator fast wakeup disabled
1b = High-resolution generator fast wakeup enable

7-6

TDHDx

RW

0h

High-resolution clock divider. These bits select the divider for the high resolution
clock.
00b = Divide by 1
01b = Divide by 2
10b = Divide by 4
11b = Divide by 8

5-4

TDHMx

RW

0h

Timer_D high-resolution clock multiplication factor

00b = High-resolution clock 8x Timer_D clock
01b = High-resolution clock 16x Timer_D clock
10b = Reserved
11b = Reserved

TDHRON

RW

0h

Timer_D high-resolution generator forced on.

0b = High-resolution generator is on if the Timer_D counter MCx bits are 01, 10
or 11.
1b = High-resolution generator is on in all Timer_D MCx modes. The PMM
remains in high-current mode.

TDHEAEN

RW

0h

Timer_D high-resolution clock enhanced accuracy enable bit. Setting this bit
reduces the accumulated frequency offset of the high-resolution clock generator
and the reference clock.
0b = Normal accuracy
1b = Enhanced accuracy enable

TDHREGEN

RW

0h

Timer_D regulation enable. Set this bit to synchronize the high-resolution clock to
the Timer_D input clock defined by TDSSELx.
0b = Regulation disabled
1b = Regulation enabled

TDHEN

RW

0h

Timer_D high-resolution enable bit. This bit must be set to enable high-resolution
operation mode. Whenever a high-resolution TDAUXCLK from another Timer_D
instance is used, this bit must also be set.
0b = High-resolution mode disable
1b = High-resolution mode enable

The enhanced accuracy bit is set

The TDHM bits are set to 0, which
causes the hi-res clock to be 8x
SMCLK = 8 x 25 MHz = 200 MHz.
So each clock count is 5 ns

11

Reserved

19

ADC10: The 10-Bit A/D Converter!

ECCN 5E002 TSPA Technology / Software Publicly Available

of the MSP430

ADC10_A Introduction

www.ti.com
VEREF+

Key features:
Multiplexed inputs
Sample and hold circuit
Successive approximation
register, driven by
selectable clock
Selectable reference
sources
Buffered output memory

ADC10SR

VEREF-

ADC10INCHx

10

Reference
Buffer

01

ADC10CONSEQx

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
TempSense
Batt.Monitor
A12
A13
A14
A15

Vcc
VSS

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

ADC10SREF2

S/H

11 10 01 00

ADC10DIVx

ADC10
PDIVx

Divider
/1 .. /8

00
01
10

ADC10
SSELx

00

VR+
10-bit ADC Core

:1
:4
:64

ADC10CLK

Convert

SHI

1
0

0
ADC10
MSC

ACLK

10

MCLK

11

SMCLK

00

Sample Timer
/4 .. /1024

MODOSC from UCS

01

ADC10ISSH

ADC10BUSY

ADC10SHP

SAMPCON

ADC10SREFx

ADC10ON

VR-

Sample
and
Hold

10 bit or 8 bit conversion

ADC10
SHTx

Sync

ADC10SC

01
10

3 inputs
from Timers

11

ADC10
SHSx

ADC10DF

Data Format

ADC10HIx

10-bit Window
Comparator
ADC10MEM
ADC10LOx

The MODOSC is part of the UCS. See the UCS chapter for more information.

When using ADC10SHP = 0 no synchronisation of the trigger input is done.

Figure 27-1. ADC10_A Block Diagram

ECEN 4517

VREF 1.5 / 2.0 / 2.5 V from shared reference

Auto

20

To Interrupt Logic

Successive Approximations
After the input signal has
been sampled, the 10-bit
SAR requires 11 clock
cycles to generate an
output
Compare analog input with
references
The MSP430 uses a
switched capacitor scheme
to perform the comparisons
See MSP430x5xx Family
Users Guide, Ch. 27
Reference: John H. Davies, MSP430
Microcontroller Basics, Elsevier, 2008,
ISBN 987-7506-8276-3.
ECEN 4517

21

Capacitor bypassing is required

What the Users Guide
recommends:
Also need capacitance at
analog input pin

ECEN 4517

22

Setting up the A/D Converter ADC10

// Configure ADC10
ADC10CTL0 = ADC10SHT_2 + ADC10ON;

// sample time of 16 clocks, turn on

// use internal ADC 5 MHz clock
ADC10CTL1 = ADC10SHP + ADC10CONSEQ_0; // software trigger to start a sample
// single channel conversion
ADC10CTL2 = ADC10RES;
// use full 10 bit resolution
ADC10MCTL0 = ADC10SREF_1+ADC10INCH_5; // ADC10 ref: use VREF and AVSS
// input channel A5 (pin 10)
// Configure internal reference VREF
while(REFCTL0 & REFGENBUSY);
// if ref gen is busy, wait
REFCTL0 |= REFVSEL_0 + REFON;
// select VREF = 1.5 V, turn on
_delay_cycles(75);
// delay for VREF to settle

The above code sets up the 10-bit ADC with A5 as its only input, with 1.5 V
giving a reading of 210 1, and 0 V giving a reading of 0. Each reading will
employ a sampling window of 16 ADC clocks = 3.2 sec.
ECEN 4517

23

Sampling the ADC input

ADC10CTL0 |= ADC10ENC + ADC10SC;

while(ADC10CTL1 & ADC10BUSY);
X = ADC10MEM0;

// sampling and conversion start

// wait for completion
// ADC10MEM0 contains result

The above code is simple and a good start. See CCS5 code examples for
use of interrupts that do not require the processor to wait during the
conversion time.

ECEN 4517

24

This Weeks Experiment 2

Become familiar with MSP430
Set up your MSP 430 to drive a MOSFET at a programmable duty
cycle
No prelab assignment
Follow the Exp. 2 procedure on the Exp. 2 website. Demonstrate
each result to your TA and get his initials on scoresheet. Turn in the
Exp. 2 scoresheet, no report otherwise needed.

ECEN 4517

25