A Comparison of RISC and CISC Architectures

Chevtchenko, S. F.1; Vale, R. F.2

Department of Statistics and Informatics
UFRPE
Recife, Brazil
1
sergio.chf@gmail.com, 2rafavaleufrpe@gmail.com
Abstract Both CISC and RISC architectures continue to be
widely used. RISC processors are present in most embedded
devices, while x86 is the most popular architecture for desktops.
Since modern processors have to address both power consumption
and performance, it is important to compare these architectures to
support future project decisions.
KeywordsRISC; CISC; comparison

I. INTRODUCTION
RISC and CISC architectures have evolved in different
applications. Most modern CISC processors are used in servers
and desktop computers, while modern RISC processors
dominate the embedded applications. Because of this historical
difference, RISC processors have been optimized for low power
systems and CISC processors for performance.
Since power consumption is becoming a major concern for
current and future projects [1], it is of great importance to
maintain adequate performance, while meeting modern power
constraints.
In the following paragraphs the authors discuss recent
studies that compare modern CISC and RISC processors
regarding ISA, performance and power consumption.

productivity. The extensive use of complex instructions provides

a direct implementation of central mechanisms of high level
programming languages, facilitating the translation to machine
code [2] [3]. Also, with the variable length in CISC instructions
and the enhanced encoding, there is a possible decrease in
program size and the amount of main memory access, allowing
a faster execution because the CPU will depend less on a slower
resource [2] [4].
B. RISC
This architecture was designed to address the problems
discussed above by reducing instruction complexity. RISC
processors employ fixed-size instructions, unlike their CISC
counterparts, thus simplifying the instruction decoding process.
Figure 1 shows the idea behind micro-operations used in CISC
systems as opposed to the simplified process in RISC.
To summarize the main characteristics of this architecture
[2] [3] [5]:

Instructions are optimized and with similar

structure, hence complex operations are a sequence
of simpler instructions generated by the compiler.

A large number of registers is required for

arithmetic operations. Memory access is achieved
through load and store-type instructions, limiting
interaction with memory.

Due to the previous points, pipelining becomes

more efficient. The simplicity found in RISC
operations allows processors to have a CPI of one
clock cycle per instruction, while CISC minimizes
the number of instructions per program.

II. ISA COMPARISON

This section exposes the main differences between the CISC
and RISC architectures. Here, benefits and drawbacks are
introduced, providing an outline for both CPU designs.
A. CISC
Computer designers created CISC processors to simplify the
compilers job. This architecture typically implements over a
hundred instructions with varying byte count and complexity.
Some of these instructions can manipulate data directly from
memory and, therefore, must include a large memory address in
the encoding [2]. This characteristic has, aside from variations
in the length of instructions, the following disadvantages:

More complex ILP and pipeline implementation

due to non-uniform instruction size and encoding.

Instruction decoding and scheduling are difficult to

perform.

Increase in ISA complexity, which leads to a

greater maintenance cost.

Despite these side effects, the CISC architecture presents

some appealing features. As a motivation for the development
of this design, there was a desire to improve programming

Figure 1. CISC makes use of microcode to enable decoding of complex

instructions, while RISC already employs simple instructions. As a consequence,
the decoding process is more concise.

However, this CPU design comes with its obstacles. Because

RISC instructions have a fixed length, more RAM is required to
store them compared to the CISC architecture, so the code
becomes larger. In addition to this, translation of high-level
language statements into machine language is harder, making
the compiler work more.

The difference in performance and power consumption

between the studied processors seems to be determined by the
intended application rather than by the choice of ISA. In other
words, in modern processors, the way the ISA is implemented,
that is, the microarchitecture, plays a more significant role in
determining performance and power characteristics than ISA.

III. PERFORMANCE COMPARISON

In a recent analysis measuring different aspects of ARM and
x86 microprocessors [6] [7], it was found that the ISA does not
have a significant impact on performance. This aspect is
determined mainly by the application domain targeted by the
processor design [8].
While the purpose of the ARM architecture is to achieve low
energy consumption and high performance following the RISC
philosophy [3], the x86 architecture aims to obtain backward
compatibility and efficiency by using micro-operations, i.e.,
splitting instructions in smaller sequences, primarily as a CISC
design [9].
Regardless of the contrasts between both architectures,
studies showed that the effects of ISA on performance are
identical on ARM and x86 processors [6]. The distinctions,
however, become clear when comparing microarchitectures.
Benchmarks indicated that large performance gaps between both
architectures were due to specific microarchitectural decisions.
IV. POWER AND ENERGY CONSUMPTION
According to results gathered from this same analysis [6],
power use depends more on the choice of core design
optimization, which can emphasize either power or
performance. Because of this, the instruction set architecture
does not significantly influence how much energy and power a
processor will consume.
On average, x86 implementations consume more power than
ARM implementations. The x86 ISA demands more energy for
micro-operations translation, but this was shown to cause a
considerably small impact. Again, the microarchitecture plays
an important role in determining energy efficiency.
To sum up these results, energy and power-efficiency is
effectively independent of ISA. Microarchitecture and design
methodology are the main factors weighing on consumption. If
a core design is highly focused on either power or performance
optimization, it may have high energy overheads, and, as
expected, higher performance processors need more power than
lower performance processors. In the end, microarchitecture and
design choices are what make a difference when comparing
power and energy consumption of processors, not the ISA.
V. CONCLUSION
Based on recent studies it seems reasonable to conclude that
the gap between RISC and CISC architectures is becoming
thinner. Recent x86 processors use pipelining as well as
maintain a complex instruction set. Internally, these processors
break x86 instructions into MIPS-like ones. This way, typical
RISC features, such as low cost and fixed execution time, are no
longer restricted to RISC.

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