Sample midterm exam

1. IC industry economics (10 pts)

An IC manufacturing plant can process 1000 wafers per week. Assume that each wafer
contains 700 chips, and each can be sold for $50 if it works. The yield of producing these
chips is currently 50%. If the yield can be increased, the incremental income is almost
pure profit. What is the minimal yield that has to be reached in order to produce an
annual profit increase of $100,000,000?
2. Crystal growth (30 pts)
(a) (10 pts) Floating zone (FZ) and Czochralski (CZ) are two typical crystal growth
methods for single crystals. What are the difference in FZ and CZ techniques?
(b) (20 pts) A Czochralski crystal is grown with an initial Sb concentration in the melt of
1 x 1016 cm-3. After 70% of the melt has been used up in pulling the crystal, pure silicon
is added to return the melt to its original volume. Growth is then resumed. What will the
Sb concentration be in the crystal after 50% of the new melt has been consumed by
growth? Assume ko = 0.02 for Sb.
3. Oxidation & gate dielectrics (30 pts)
(a) (15 pts) A cut of 1 m width is made in a silicon dioxide film that is 0.4 m thick; the
(100) silicon substrate is exposed where the window is patterned. Additional oxide is
grown in dry oxygen for 1 hr at 1100 oC, followed by another oxidation in water vapor
ambient for 30 minute at 1000 oC. Sketch a cross-section of the resulting Si/SiO2
structure, showing the thickness of the oxide in all locations, the Si/SiO2 interface at all
locations, and the height of all resulting steps.
(b) (10 pts) LOCOS (LOCal Oxidation of Silicon) is a microfabrication process in which
SiO2 is formed in selected areas on a Si wafer. The Si/SiO2 interface is formed at a lower
point than the rest of the Si surface so that the oxide can be used for lateral isolation.
Typical process steps involves: (i) Preparation of silicon substrate; (ii) deposition of SiO2;
(iii) deposition of Si3N4; (iv) patterning and selective etching of Si3N4 and SiO2; (v)
thermal growth of SiO2; (vii) removal of Si3N4 mask. Based on the description, draw
cross sectional schematics for the LOCOS process.
(c) (5 pts) Materials with high dielectric constants are desired for gate dielectrics
especially when the feature sizes of MOSFET become smaller and smaller. Hafnium
dioxide (HfO2, dielectric constant: 25) was one of the leading contenders in this field. If
a transistor needs 1 nm SiO2 to achieve the designed electrical behavior, how thick a
HfO2 can be used?
4. Optical lithography (30 pts)
(a) (10 pts) The processor in your computer (smallest feature size 32 nm) is likely made
with 193 nm optical lithography. Given that the lowest k1 is 0.25, the largest numerical
aperture is 0.93. What is the smallest feature size the 193 nm optical lithography
technique can make? How does this number compare with 32 nm? Can you explain how
it is possible if there is any discrepancy?
(b) (10 pts) Back in 1678, Hooke wrote in a publication, "that if you would have a
microscope with one single refraction, and consequently capable of the greatest clearness
and brightness, spread a little of the fluid to be examined on a glass plate, bring this under
one of the globules, and then move it gently upward till the fluid touches and adheres to

the globule Why a drop of fluid is going to give us better clearness in optical
microscopy? If the lens material has a refractive index of 1.56, and the oil used has an
index of refraction of 1.515, what is the maximum angle of incident light (collecting
angle) that will be used for imaging? How much improvement is achieved as compared to
imaging in air?
(c) (10 pts) To further improve the resolution, one straightforward approach is to use
shorter and shorter wavelength. This, however, will significantly change the requirement
for optical exposure system. Compare the optical systems for DUV, EUV and X-ray
lithography, comment on their difference and explain why they are different.
5. Bonus credit question (10 pts) (You can get 10, 5, or 0 extra pts depending ONLY on
the level of details you provide)
As stated in the syllabus, the goals of ECE 571 are: 1) To introduce basic
technologies and knowledge (science) of IC fabrication; 2) To fabricate semiconductor
devices and integrated circuits starting from bare silicon wafers; 3) To test
devices/circuits and analyze their performance using your knowledge in semiconductor
physics and electronics. Also stated in the lab manual is that I would like to train your
ability and habit working in the lab, taking notes and analyzing raw data. As far as this
course goes, how do you think we have done so far? Any comments and suggestions to
the instructor and TAs to make this course a more enjoyable journey and memorable part
of your academic life?

Sample solutions