1st Hourly Test

Course with Branch : M.E.-ECE- (Micro-electronics and VLSI Design)

Semester : 3rd
Subject Code : ECT-709
verification methodology

Subject

VLSI

Section A (2 Marks Each)

S.
N
o.
1
2
3
4
5
6

Topic/Chapter

Question

Basic of
SVM_Chp.1

The purpose of a testbench is to determine

the correctness of the design under test
(DUT). This is accomplished by which steps.
What is need of randomization in system
verilog testing?
What is the concept of layered test bench in
system verilog?
In the concept of layered test bench at
functional layer what are the various
component that needed used?
For developing layered test bench why
environment class is used?
In layered test bench what is the role of
Scenario layer and and what its various
component?
At the top of layered test bench which layer us
used and how it controls the complete test
bench?
Why driver unit is used between agent unit
and DUT?
Why two-states data is preferred in system
Verilog?
Differentiate 2-state and 4-state data types in
system verilog.
What is similarity and difference in reg and
logic data types?
Different between packed and unpacked
structure type with the help example.
Different between packed array and unpacked
array with the help example.
If at runtime size of array is to be change
which type of array is preferred and why, give
an example?
How fork and join is different from forkjoin_any, example required?
How fork and join is different from forkjoin_none, give an example?
How fork and join_none is different from forkjoin_any with help of example?

Basic of
SVM_Chp.1
Basic of
SVM_Chp.1
Basic of
SVM_Chp.1
Basic of
SVM_Chp.1
Basic of
SVM_Chp.1

Basic of
SVM_Chp.1

8
9

Basic of
SVM_Chp.1
Data_types_Chp.1

10

Data_types_Chp.1

11

Data_types_Chp.1

12

Data_types_Chp.1

13

Data_types_Chp.1

14

Data_types_Chp.1

15

Fork_join_Chp.2

16

Fork_join _Chp.2

17

Fork_join_Chp.2

Level
#

Easy
Easy
Easy
Mediu
m
Mediu
m
Easy
Easy
Difficu
lt
Mediu
m
Difficu
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Easy
Easy
Easy
Easy
Easy
Mediu
m
Difficu
lt

18

Fork_join _Chp.2

19

Fork_join_Chp.2

20

Fork_join _Chp.2

21
22

OOPS_chp.3
OOPS_chp.3

23

OOPS_chp.3

24
25

OOPS_chp.3
OOPS_chp.3

26

Data type_Chp.1

27

Data type_Chp.1

28

Data type_Chp.1

29

Data type_Chp.1

30

Data type_Chp.1

31

Data type_Chp.1

32

Functions_chp.2

33

Functions_chp.2

34

Functions_chp.2

35

Data type_Chp.1

S.
N
o.
1

Topic
OOPS_chp.3

Functions_chp
.2

Functions_chp
.2
OOPS_chp.3

How you simulate a forkjoin test bench in

questasim? give an example for this with
required commands of questasim
If fork and join are not used in test bench
what id the alternate for this
Forkjoin , join_any, join_none, are these
execute sequentially or concurrently, give
comments the some explanation.
Why OOPs is introduced in system verilog?
Give the abstract information regarding the
main components of OOPS .
When and with help of which inbuilt function
objects are created at runtime, give an
example.
How to add elements at the end of que?
How do you call the variable of class from
another class, give an example.
Which operator is used for creating a dynamic
array, give an example.
Where associative arrays are used in system
verilog array give an example?
Does associative array have any storage
allocation, why?
How the ques in system verilog is different
from ques in C?
How to have size of que item, give an
example?
How the functions in system verilog is
different from functions in verilog?
How tasks in system verilog is different from
tasks in verilog?
Is it possible to return value from function is
system verilog?
What are the various mechanism with which
one can return value from functions from
system Verilog?
Is it better to use 2 state data type if yes then
why?
Section B (12 Marks Each)
Question

Develop a test bench for utilizing the variables of

one class to another class without inheritance.
Write test bench for testing a DUT for dividing two
numbers, function for dividing two numbers must
be in class.
Differentiate between tasks and functions, for
every point example is required .
Write a test bench that includes two separate
classes one class includes UP_counter fucntion,

Mediu
m
Mediu
m
Mediu
m
Easy
Easy
Easy
Easy
Difficu
lt
Easy
Easy
Easy
Easy
Easy
Easy
Easy
Easy
Easy
Easy

Level
#

Mediu
m
Easy
Easy
Difficu
lt

Fork_join_Chp.
2

Fork_join_Chp.
2

Fork_join_Chp.
2

Data_types_C
hp.1
Basic_SVM_Ch
p.1
Data
types_cjp.1
Fork_join_Chp.
2
Fork_join_Chp.
2

9
10
11
12
13

Interface_chp.
3

14

Functiontasks_chp.2

15

Forkjoin_chp.2

and second includes down_counter, you have to

access the fucntion up_counter with the help of
handles of down_counter.
Which test bench execute in less time forkjoin or
for-join_any, justify you statement with the help of
program?
Which test bench execute in less time forkjoin or
for-join_noe, justify you statement with the help of
program?
Which test bench execute in less time fork
join_none or for-join_any, justify you statement
with the help of program?
Differentiate between fixed array and associative array with an
example.
How system verilog test bench is a layered testbench?

Mediu
m
Mediu
m
Mediu
m
Easy
Easy

Differentiate between fixed array and queue with an example.

Easy

Let you are having two events e1, e2, use these
with non-blocking statement in system verilog
Let you are having two events e1, e2, use these
with blocking and non-blocking statement in
system verilog.
How interface is used in system verilog and what
is the need of clocking block. Discuss with the
help of j-k flip-flop?
How function and tasks are in system Verilog is
different from verilog function and tasks. And also
differentiate function and tasks in system Verilog
with the help proper program?
Differentiate between fork_join, Fork_join-any,
Fork_join-none Full program is must.

Difficu
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Easy