Vous êtes sur la page 1sur 16

PART 6 – Logic Gates, Binary,

and Hex Logic by John Becker


So we now have five parts of Teach-In 2000 We have covered the basic “passive”
under our belts and we know that you are components and provided you with a means by
greatly enjoying and learning from this 10-part which to create waveforms and display them
series. We are pleased to have been told on on a PC-compatible computer screen. This
many occasions that you appreciate the way in enables us to now explore somewhat more
which we are leading you by the hand, on the sophisticated components of an “active”
assumption that you knew little or nothing nature. Our experimental subjects this month
about electronics before you started reading are not only gates but binary counters to
the series. Your complementary comments are complement the Tutorial, and a decimal
very welcome. counter – for fun as well as instruction!

In previous parts of Teach-In, other input is high. Another is to its functional title) and one out-
the term AND has been used indicate whether or not all inputs put. The logic levels applied to
from time-to-time. Indeed, in Part are high, allowing, for example, the two inputs can be regarded
4 we gave a brief description of a process to start if several pre- as the bits to which we referred
what it does. The term occurs in ceding processes have been a few paragraphs earlier when
both computing and electronics. completed. stating what AND means in an
In both instances, the implemen- Let’s use your breadboard electronic or computing context.
tation of AND is physically carried and the oscillator you were us- It is worth noting that there
out by an electronic device or cir- ing last month, plus an elec- are other AND gates which have
cuit somewhere in the system. tronic AND gate, to demonstrate more than two inputs. We shall
We explained that if two logic the AND principle, and in doing not discuss them, but just com-
bits are ANDed together then the so to show its use as a signal ment that similar principles apply
result will be logic 1 only if both switch. to all types. There are also other
source bits are also at logic 1. If The symbol for a 2-input quad 2-input AND gates with
either or both bits are at logic 0, AND gate is given at the top of different type numbers (indeed
the result will also be logic 0. Fig.6.1a (the table below it will all the devices we use in this Tu-
be discussed presently). torial are available with different
type numbers to those quoted,
AND NOW THE From your bag of compo- but not necessarily with the
nents, select a 74HC08 inte- same pinouts).
GATES grated circuit (IC). This IC is an-
The first subject to be cov- other digital electronic device
ered this month is the expansion (as are the 74HC04 and PRELIMINARIES
of the AND concept, and to de- 74HC14 inverters you have al-
Before you remove the
scribe not only integrated devices ready been using). It is a quad
74HC08 from its packaging,
that use AND, but those that use 2-input AND gate, and as such
briefly touch something that is
the other five main logic functions, has four separate AND gate cir-
earthed to discharge any static
NAND, OR, NOR, XOR and cuits within it. Its pinouts are
electricity from your body. (See
XNOR. shown in Fig.6.2.
also Panel 6.1.)
One of the uses for an AND Whereas the inverters each
Plug the IC (call it IC3) into
gate is as a signal (data) switch, had one input and one output,
your breadboard and connect it
only allowing the signal on one the AND gate we are about to
up as shown in Fig.6.3. Ensure
input to pass to the output if the use has two inputs (as stated in
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 299
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
AND GATE OR GATE XOR GATE
A) C) E) QUAD 2-INPUT AND
A A A
Y Y Y 74HC08
B B B
1 14
B A Y B A Y B A Y A1 +VE
2 13
0 0 0 0 0 0 0 0 0
B1 B4
0 1 0 0 1 1 0 1 1
3 12
1 0 0 1 0 1 1 0 1
Y1 A4
1 1 1 1 1 1 1 1 0
4 11
A2 Y4
NAND GATE NOR GATE XNOR GATE 5 10
B) D) F)
A A A B2 B3
Y Y Y
B B B 6 9
Y2 A3
7 8
B A Y B A Y B A Y
GND Y3
0 0 1 0 0 1 0 0 1
0 1 1 0 1 0 0 1 0
1 0 1 1 0 0 1 0 0 Fig.6.2. Pinouts for a 74HC08
1 1 0 1 1 0 1 1 1 2-input AND gate.

Fig.6.1. Symbols and truth tables for the six 2-input logic
gate functions.
+6V

22
21
20

23
24

26

30
25

27
28
29

31
32
R11
10k IC3a
74HC08
INPUT "A" (A) 14
1
3 (Y)
FROM 1C1a 2
PIN 2 (B)
R
7 R12 11 IC3
470W
ALTERNATIVE LINK
(SEE TEXT) a
D4 R12
k k D4
0V a

Fig.6.4. Circuit diagram for LINK (B)


22
20

23
24
25
26
27
28
29
30
31
32
(SEE TEXT)
the AND gate experiment.
The circuits for the other
gates are similar.
Photo 6.1. Breadboard showing
the 74HC00 and 74HC02 con-
that it is placed in the correct figured for the demos. Note that SIGNAL IN (A)
FROM IC1a PIN 2 SIGNAL OUT (Y)
way round (as we discussed in they are not in the final recom-
Part 2). Fig.6.3. Breadboard layout
mended board positions. for the AND, NAND, OR and
We are using just one AND
gate from within IC3, and shall tions are automatically made to XOR 2-input gate
refer to it as IC3a. Pin 1 (call it the battery when it is connected experiments.
Input A) of IC3a connects back to the board as in previous ex- tor should be 100uF.
to the output of oscillator IC1a periments.
pin 2 (see Part 4). Pin 2 (Input Incidentally, the A and B
A LED (D4) is connected to names given to the gate inputs
B) of IC3a is linked to the posi- the output of IC3a (pin 3) via the
tive power line via resistor R11. do not have to be in that order,
usual ballast resistor (R12). or even with those names. They
The power line connections The circuit diagram for this could even be called Input John
for IC3 are positive to pin 14 and set up is shown in Fig.6.4. and Input Gill if you wanted to.
0V to pin 7. With the breadboard Nor is it necessary to use the
links as shown, these connec- Capacitor C1 of the oscilla-
same suffix letters as those
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 300
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
used here, the gate having pins AND gate has been set to logic lustrations and tables).
1, 2 and 3 could be named IC3d 1 via the 10kW resistor R11. Truth tables can be com-
in another circuit (or even The data (bit) for Input B (pin 2) piled for any number of inputs
IC54c). It is entirely up to the is alternating between logic 1 and outputs of any digital logic
circuit designer to give ICs what- and logic 0, as provided by the device. Some can become very
ever circuit part numbers he or oscillator. As we said before, the long indeed! For example, AND
she prefers. conditions in which an AND gate gates (and other members of
will produce an output of logic 1 the logic family) can have three,
is when both ANDed bits are at four, eight or even more inputs.
FIRST TEST logic 1. The number of permutations of
Connect power to the board In the circuit you are run- 2-state (digital) logic on those
and adjust preset VR1 (Fig.4.1 ning, one bit (A) is already at inputs is two to the power of the
in Part 4) until the oscillator’s logic 1 (via R11), and the other input quantity, e.g.:
LED (D1) flashes on and off at a bit (B) is switching between the
fairly even and slow rate. You INPUTS PERMUTATIONS
two logic states. When bit B is at
should see that LED D4 also logic 1, the AND condition has 1 21 = 2
flashes on and off in time with been met and the output goes 2 22 = 4
D1. high, to turn on LED D4. With bit 3 23 = 8
Now make a temporary link B low, the condition is not met 4 24 = 16
between IC3a pin 2 (Input B) and so the output is low, and D4 5 25 = 32
and the 0V power line (see is off. 6 26 = 64
Fig.6.3 – Link B). Leave R11 in When you take bit A low by 7 27 = 128
place – it prevents the input connecting Input A to 0V, the 8 28 = 256
from “floating”, a condition in AND condition can never be
which the gate would be unsure met, irrespective of what hap- NAND GATE LOGIC
of what logic state is on that in- pens on Input B. Thus LED D4 We stated earlier that as
put should you remove and remains off. well as AND gates, other types
swap a link wire between it and of gate exist to meet other logi-
either of the power lines. cal conditions. The repertoire
You will now find that LED TRUTH OF THE comprises AND, NAND, OR,
D1 continues to flash, but LED MATTER NOR, XOR, XNOR, NOT
D4 is turned off. Remove the (another term for inverter). Hav-
As you will have deduced,
link and D4 should flash again. ing met AND and NOT (the
there is a permutation of four
This is what’s happening: 74HC04 and 74HC14 inverters
logic states that can occur on
In the first instance, the data you’ve been using in the oscilla-
the two inputs of the AND gate.
(bit) at Input A (pin 1) of the tors), we shall now discuss the
There is only one combination of
others in turn, starting with the
those input states in which the
NAND gate.
QUAD 2-INPUT NAND output can go high. This permu-
74HC00 tation of states and their resul- The term NAND simply
1 14
tant outputs can be tabulated, as means NOT-AND. A NAND gate
A1 +VE in Fig.6.1a, below the gate’s is thus an AND gate whose out-
2 13 logic symbol. Tables such as put is inverted. Its logic symbol
B1 B4
this are called Truth Tables. and truth table are shown in
3 12
Fig.6.1b.
Y1 A4
The truth table in Fig.6.1a
A2
4 11
Y4
(and in those we give later and The symbol is almost identi-
5 10
in the computer program) is cal to that for the AND gate, ex-
B2 B3 headed with the inputs in order cept that the output has a small
6 9 of B and A, which allows the circle on it. This symbol is fre-
Y2 A3
table to be arranged so that the quently encountered on outputs
7 8
GND Y3 logic on these inputs is shown in (and inputs) to signify that the
binary value order (discussed logic is inverted.
Fig.6.5. Pinouts for the later in this Tutorial). The output You can, in fact, achieve a
is headed with a Y (a common NAND situation by taking the
74HC00 quad 2-input
letter encountered with many, output of an AND gate through
NAND gate. but not all, output-indicating il-
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 301
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
QUAD 2-INPUT OR
an inverter (try it sometime). 74HC32
Whilst NOR gates are avail-
There are, though, logic devices able with several inputs, it is one
1 14
manufactured to specifically per- A1 +VE
of the quad 2-input types we use
form the NAND function. One 2 13
now, the 74HC02. Its pinouts
such is the 74HC00. B1 B4 are shown in Fig.6.7. Note that
The 74HC00 is a quad 2- Y1
3 12
A4
its pinouts are different per gate
input NAND gate, and its pinouts 4 11
section to the previous gates.
A2 Y4
are shown in Fig.6.5. Note that The reason for this differ-
5 10
the order of the pins per gate is B2 B3 ence is unknown – it seems il-
identical to that for the 74HC08 6 9 logical. It has to be said, though,
Y2 A3
AND gate. that there are occasional incon-
7 8
With the breadboard power GND Y3 sistencies between what one
off, remove the 74HC08 and in might expect of a digital IC com-
its place put a 74HC00. Again Fig.6.6. Pinouts for the pared to what the situation actu-
touch something that is earthed 74HC32. ally is.
immediately prior to handling it QUAD 2-INPUT NOR One reason given to the au-
(as we advise you in Panel 6.1). 74HC02 thor many years ago is that digi-
With power on again, do the tal logic devices were originally
1 14
same tests as you did with the Y1 +VE designed for the United States
74HC08, connecting Input A (pin 2 13 Military and that this had an af-
1) variously between +VE (via
A1 Y4
fect upon how devices were
3 12
R11) and 0V. Note the way in B1 B4
manufactured.
which LED D4 flashes co 4 11 Insert a 74HC02 into the
Y2 A4
mpared with LED D1. breadboard in place of the previ-
5 10
You should find that D4 will A2 Y3 ous OR gate, but connect it,
only be turned off when inputs A 6 9 plus the resistor and LED, ac-
B2 B3
and B are both at logic 1, the cording to Fig.6.8. Do your tests
7 8
opposite of the situation with the GND A3
in the same way as before.
AND gate. Indeed, your findings
should correspond to the data XOR GATE LOGIC
shown in the NAND gate truth
Fig.6.7. Pinouts for the
table in Fig.6.1b. 74HC02. Note that the pin The term XOR stands for
order is different to the other Exclusive-OR and such gates
gates discussed. are only likely to be encountered
OR GATE LOGIC as 2-input types. The logic sym-
input OR gate is the 74HC32. bol and truth table are given in
With a 2-input OR gate, the Put one into your breadboard in
output is high if either Input A Fig.6.1e.
place of the 74HC00. The
OR Input B is high. If neither is pinouts are identical to the previ- The important thing to note
high, the output will be low. As ous two gates. about an XOR gate is that the
with the AND and NAND gates, output only goes high if the two
OR gates are available with Do the same tests as you inputs do not have equal logic
more than two inputs. In these did before, and compare your values on them. If the inputs do
cases if any of the inputs are results with the truth table. have equal logic, then the output
high, so too will be the output. will be low.
OR gates allow, for exam- NOR GATE LOGIC This condition is highly use-
ple, a process to start or con- For a given input combina- ful in many situations, such as
tinue if any preceding processes tion, a NOR (NOT-OR) gate pro- when you need to compare
have been completed or are still duces an inverted output com- whether or not signals from two
in progress. pared to that for an OR gate. sources have equal logic values.
The logic symbol and truth The symbol and truth table for a The principle in computing al-
table for a 2-input OR gate are 2-input NOR gate are shown in lows easy assessment for the
shown in Fig.6.1c. Fig.6.1d. Again note the inver- equality between byte values (8-
sion circle on the output. bits being compared simultane-
An example of a quad 2- ously, with a single output bit

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 302
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
being set to represent the an-
swer).
XNOR GATE LOGIC
XOR gates also allow, for With an XNOR gate
22 (Exclusive-NOT-OR), the output
21
20

23
24

26

30
25

27
28
29

31
32
instance, signal logic levels to
be dealt with “as are” or in- logic is the inversion of that
verted, just by changing the which applies to an XOR gate.
logic level on one input. One ap- The logic symbol and truth table
plication for this is in the control are shown in Fig.6.1f. Again the
R
11
74HC02
of some simple types of liquid circle on the output indicates the
crystal display (LCD) – as we inversion.
R12
k D4
shall see later in the Teach-In Whilst XNOR gates are
a series. manufactured, they are not
LINK (B) The quad 2-input XOR gate readily available through hobby-
22
20

23
24
25
26
27
28
29
30
31
32

(SEE TEXT)
we want you to examine now is ist retailers and are not amongst
the 74HC86. Its pinouts are the list of components we sug-
shown in Fig.6.9 – they are in gested that you bought for this
the same order as the first three Teach-In series.
SIGNAL IN (A) gates you examined. Use the However, we can actively
SIGNAL OUT (Y) FROM IC1a PIN 2
breadboard layout shown in demonstrate an XNOR gate via
Fig.6.8. Breadboard layout Fig.6.3, and run the usual tests. another of our interactive com-
for the NOR gate puter programs. The same pro-

PANEL 6.1 – HANDLING INTEGRATED CIRCUITS


Although modern integrated circuits (ICs) are very reliable, they have to be handled with respect. They
must be inserted into circuit boards the correct way round, stated maximum voltages should not be ex-
ceeded, and current limits should be adhered to (although many devices have current limiting circuits built
into them). One point which must always be observed, is that ICs should not be exposed to the dangers
created by static electricity discharges, especially ICs which have the term CMOS (complementary metal
oxide silicon) in their datasheet/catalog description.
Although we have not mentioned it before, all the ICs with the 74HC prefix that you have, and will be
handling for this Teach-In, are CMOS devices. The 74HC type was chosen for its particularly hardy nature,
including the ability to operate at up to 7V and to provide a reasonable amount of current to drive the LEDs.
(Note that there are many other digital logic devices with a 74 prefix, but with a different set of letters follow-
ing it, and with different characteristics.) Whilst CMOS devices have diodes protecting certain external con-
nections, particularly the inputs, the diodes can only drain away excessive applied voltages up to finite lim-
its. The discharges from static electricity can be many thousands of volts, levels that are way beyond what
the protecting diodes can handle.
It is easy to avoid static electricity from discharging into an IC when handled by always touching a
grounded item (one which is connected to electrical “earth”) before touching it. This discharges static from
your body or the tool you might be handling. The metal rear panel of a plugged-in mains-powered computer
is a good place to touch; even its printer port cable has bare metal earthed connectors at each end.
In professional electronics, those handling ICs do so in conditions where sophisticated earthing tech-
niques are used to prevent static electricity build-up. There is no need for the average constructor to go to
such lengths and the “touching ground” method normally proves satisfactory. Also, any mains powered item
of test or construction gear (e.g. soldering iron) should be firmly earthed.
Whenever possible, use sockets for ICs on any printed circuit board or stripboard (e.g. Veroboard) as-
sembly where soldering is required. This enables the ICs to be easily replaced if necessary. It also prevents
them from becoming overheated during soldering, even though they can be quite robust in this situation.
Do not feel unduly alarmed by the warnings about static electricity and its effect on ICs. Providing you
observe the basic precautions, you can enjoy using ICs without endangering them, and most are actually
far more resilient than many texts suggest.

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 303
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
QUAD 2-INPUT XOR
74HC86
PANEL 6.2 – SAMPLING RATIOS
1 14
A1 +VE You will recall that when discussing frequency counting in Part 4,
2 13 we commented on the problems created by sampling at too slow a
B1 B4
rate.
3 12
Y1 A4 There is a simple ratio of minimum sampling rate to original fre-
4 11 quency rate that allows the essence of the waveform (whether it’s
A2 Y4
above or below a midway reference level) to still be discerned. The
5 10
B2 B3 ratio is 2:1, i.e. sampling should be at a frequency no less than twice
6 9 that of the waveform being sampled.
Y2 A3
7 8
It was a certain Mr. Nyquist (dates and history unknown) who for-
GND Y3 mally expressed this ratio, apparently defining the minimum sampling
rate that allows accurate reconstruction of a signal in pulse-coded
Fig. 6.9. Pinouts for the communications systems.
74HC86. So far as audio signal sampling is concerned, where the shape of
the waveform needs to be closely preserved, rather than its high or
gram allows you to examine on- low status, a sampling frequency that is much higher than the fre-
screen the other logic gates quency of the audio signal is required. This is very much apparent in
we’ve been discussing. From the ADC Demo, which we discussed last month.
the main menu, run the 2-Input
Logic Gates program. There does, though, seem to be a general consensus that for the
upper audio frequencies (at the top end of human hearing) a mini-
mum ratio of 3:1 is acceptable. It is worth noting that when reconsti-
LOGIC GATES tuting a digitally sampled audio signal back to analog, the harmonics
PROGRAM created by the original sampling frequency need to be filtered out us-
ing additional electronic circuits.
With the 2-Input Logic
Gates program running, the
screen displays the logic sym- SELF-TEST All the control key options
bols and truth tables for the six are stated on screen. When you
When you are confident press <P> the waveform for Sig-
2-input gates just discussed.
enough, have a go at another of nal B alternates between a nar-
You can interact with any of our Self-Test options. Press <S> row pulse and a square wave.
the symbols, using the left and and correctly answer the ques-
right keyboard arrows to select Whilst experimenting with
tions asked! (We hope you will be
which one. The selected table is different frequency rates, con-
mildly amused by the result of cor-
indicated by a light-blue back- sider the implications of what
rectly answering each of them –
ground in the table heading. the result would be if you were
and doubly so for getting all right!)
using one waveform to sample
Up and down keyboard ar- the other. In the screen demo,
rows highlight different rows in
the selected table. Notations on
LOGIC WAVEFORMS it’s the AND result that is your
best guide to sampling results.
the logic symbol reflect the logic DEMO
shown for the selected row. It is You will see, for example,
The next demonstration we’ve that when the edges of Signal A
stated in binary (0 or 1) and red prepared illustrates two wave-
“flags’’ also show whether the and Signal B cross, the ANDed
forms before and after they pass result can be a pulse much
logic is high or low (just a bit of through three logic gates, AND,
fun the author enjoyed putting shorter than Signal B’s pulse. In
OR and XOR. Run program Digi- any practical sampling circuit it
in!).
tal Sampling and Logic Demo. is likely that some sort of addi-
We suggest you explore the tional circuit would be required
The cycle width for the input
symbols and try to memorize the to detect whether or not a sam-
square waves displayed (Signals
logic tables (or at least the logic pled result occurs for less than a
A and B) is changeable, and the
behind the creation of the tables, specified minimum duration.
waveforms traverse the screen to
as discussed earlier).
show how their relationships If the result is too short, it
change with time.

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 304
Maxfield & Montrose Interactive Inc
TEACH-IN 2000

Photo 6.3. Interactive digital sampling


Photo 6.2. The interactive logic gates
demo screen, which highlights the rela-
screen, in which all permutations of 2-input
tionship between two logic signals.
logic are demonstrated.

could be that it has been caused each of the A/B bit pairs as sep- BINARY TABLE
by “noise” in other parts of a arate items, combining them as
complex circuit (think of how the required by the logic function Before we get into the busi-
electrical noise from some vehi- stated. For information only, the ness of illustrating binary con-
cles can interfere with your TV decimal values for the full 8-bit version, have a look at the pro-
or radio reception). binary values are given in green. gram Binary, Hex, Decimal
(Binary/decimal conversion is Table 0-255. It’s what it says it
There’s a snippet of further
examined a bit later in this Tuto- is, decimal values from 0 to 255,
info on sampling in Panel 6.2.
rial.) with their 8-bit binary and hex-
You will find Panel 6.3 interest-
adecimal equivalents.
ing as well (relatively speaking!). We believe the rest of the
screen’s functions are obvious, There are three screen
including the Self-Test option. pages, rotating on a cycle at
8-BIT LOGIC Except – there’s a small clarifi- each press of the space bar (or
Earlier in this Tutorial we cation: when in the Self-Test any key except <M>, which
discussed digital logic from the mode and you want to use <M> brings back the menu display).
point of view of 2-input (2-bit) or <S> to return to the menu or This table will prove invalu-
gates. It is now worth consider- terminate Self-Test, you must able on many a future occasion!
ing 8-bit logic, not in terms of press <ENTER> to activate the Keep it on screen while you read
actual electronic logic gate de- letter once keyed in. Otherwise, this next section.
vices, but from the point of view with the Control keys stated, just
There is also a text file of
of computers and computing press and see what happens!
the data that you can print out
programs. From the main menu from your usual word processor
select 8-Bit Binary Logic.
The screen now displays six
boxes comprising data for eight
combined 2-bit versions (two
bytes) of the logic functions pre-
viously discussed. The formula
for each function is shown as
(for example) Y = A OR B where
the three letters are the same as
those used in the 2-input gate
logic demo.
Below the formulae are the
eight 2-bit values for A and B,
together with their Y answer.
Eight steps are needed for you Photo 6.5. Interactive screen illustrating the principle of 8-
to produce the answer, taking
bit logic functions.

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 305
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
16 is as shown that if a bit in a binary number is
in Table 6.1. a 1, it represents the same deci-
In many in- mal power of 2 as its bit number.
stances it is con- If there is a 0 in a bit position,
ventional to the value represented by that bit
Photo 6.4. Part of the decimal-binary-hex place leading is also 0. For example, take the
conversion screen displays, covering decimal zeros before the binary number 11010110, we
0 to 255. binary value, so can analyze it as illustrated in
that its length is, Table 6.4.
software. It’s in directory C:\ for example, eight digits long (or Try this with other binary
TY2KPROG (where the rest of 8 bits to use the commonplace numbers you think up, and
your Teach-In 2000 programs term, where “bit” stands for bi- cross-check your result with the
are held) and is named nary digit). conversion table.
TY2KBDHX.TXT.
Referring back to the con-
version table still on your HEXADECIMAL
BINARY CONVER- screen, you will see the 8-bit
structure applied to the first 256 NUMBERS
SION binary values. Yes, we deliber- We have commented that
So, you’ve had a glance at ately said “256” rather than the symbols for decimal num-
the binary conversion program “255” – remember that 0 is a bers run from 0 to 9 and that bi-
pages, and you’ve been ex- value as well! nary just uses 0 and 1. The hex-
posed to binary numbers in vari- So what about binary num- adecimal (hex) system uses 16
ous ways since we discussed bers beyond decimal 255? You symbols, 0 to 9 plus A to F. The
the installation and operation of just extend the principle: keep
your computer interface board in on increasing the length of the
Part 4. Table 6.1: Decimal and
binary number, but, perhaps Binary Symbols
In case you’ve not yet showing as two (or more) 8-bit
DECIMAL BINARY
figured-out the logic behind bi- lengths, separated by a space,
nary numbers, let’s explain it e.g. 256 could be shown as: 0 0
here and now! 1 1
00000001 00000000 2 10
We’ve told you several
times that digital logic can be in or just 100000000 3 11
one of two states, variously ex- 4 100
pressed as high or low, logic 1 What you have probably 5 101
or logic 0, 1 or 0, on or off, H or spotted is that there are several 6 110
L, set or cleared. Using 1 or 0 is situations in a binary number 7 111
the most convenient method of when just one bit is a 1, the oth- 8 1000
expressing binary numbers, in ers being 0. Run through the bi- 9 1001
the same way that decimal val- nary table on your screen – con- 10 1010
ues are expressed using the nu- firm that the single bit numbers 11 1011
meric symbols 0 to 9. and their decimal conversions 12 1100
As you well know, in deci- are as shown in Table 6.2. Each 13 1101
mal we count from 0 to 9 and of the decimal values is, of
14 1110
then cycle over to 0 again, but course, twice that of the previ-
15 1111
placing symbol 1 in front of 0 to ous one, and it is also a power
of 2, as shown in the third col- 16 10000
produce 10 (ten), and so on. etc. etc.
umn. From Table 2 we can get
In binary, we count from 0 to the values shown in Table 6.3.
1 and cycle back to 0, again following thus applies:
placing a 1 in front of 0 to pro- You will recall that the bit
numbers in binary are numbered Decimal 16 then becomes
duce 10, but this time the sym- hex 10, decimal 17 = hex 11,
bol “10” represents decimal 2. from left to right as 7 to 0, which
is the same order and number decimal 31 = hex 1F, decimal 32
Next we get “11” (decimal 3) fol- = hex 20, etc., always incre-
lowed by “100” (decimal 4), and of the above power values.
menting through groups of 16
so on. The sequence from 0 to What we can say, then, is before roll-over to the next prefix

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 306
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
Table 6.2 (decimal). In some instances a BIT VALUE
BINARY DECIMAL POWER
numerical suffix is given to indi-
cate the value system used, e.g. 0 1
00000001 1 20 10010 (decimal), 1002 (binary), 3 8
00000010 2 21 10016 (hex). 4 16
00000100 3 22 8 256
Obviously, when there is
00001000 4 23 10 1024
any doubt about which system a
00010000 16 24 value is expressed in, clarifica- 11 2048
00100000 32 25 tion should always be given, ei- down the value of 2 to the power
01000000 64 26 ther in words, or as a prefix or of that bit number:
10000000 128 27 suffix, unless the context in Now add up the second col-
which it appears umn: 3353 in this example.
Table 6.3 makes its value
obvious. If, for ex-
POWER 7 6 5 4 3 2 1 0 ample, you saw HEX TO DECIMAL
DECIMAL 128 64 32 16 8 4 2 1 the value 100 writ-
Converting a hex value to
decimal is nearly as easy. Take
Table 6.4 $FD58 for example: from right to
left, write down in a column the
BIT NO. 7 6 5 4 3 2 1 0
place number for individual hex
DECIMAL 128 64 32 16 8 4 2 1 numbers within the full number.
BINARY 1 1 0 1 0 1 1 0 In column 2 write down the
VALUE 128 +64 +0 +16 +0 +4 +2 +0 = 214 value of 16 to the power of each
position. In column 3 write the
symbol change, whereas in dec- ten on its own, you might not be individual hex values them-
imal you increment in groups of sure if it meant decimal 100, bi- selves, and beside them the
ten before roll-over. nary 100 (decimal 4), or hex 100 decimal equivalent for each of
This is illustrated in the con- (decimal 256) – which gives ob- those values. Now multiply the
version table on screen, where vious scope for confusion! values in column 2 and column
the blue values prefixed by “$” For the remainder of this 4, and write down the answer in
are the hexadecimal representa- text we shall use “$’’ to indicate column 5. Then add up
tions of the decimal and binary a hex value. column 5:
numbers to their left. The total for this example is
For incrementing from deci- 64856.
BINARY TO
mal 255 to 256, the roll-over be-
comes $FF to $100. DECIMAL PLACE(x) 16x HEX DEC RESULT
Hex values are indicated as For converting 0 1 8 8 8
such in a variety of ways. On binary or hex num- 1 16 5 5 80
screen now the symbol “$” indi- bers to decimal you 2 256 D 13 3328
cates hex, the prefix “&H” is also need a pen and pa- 3 4096 F 15 61440
used (as required by the Quick- per, and/or a calcula-
BASIC software in which the tor (or the program we discuss
program you are now viewing in a moment!). Neither conver- DECIMAL TO HEX
was originally written). The letter sion is difficult. It gets a bit more compli-
“H” (or “h”) is also often used as Take a binary number of cated for decimal to hex conver-
a prefix or suffix. 00001101 00011001, for exam- sion. First, have the following
Value systems can also be ple (16 bits split into two groups table to hand:
stated by prefixes or suffixes of of eight as discussed a moment Let’s take decimal 39,923
“b” or “B” (binary), and “d” or “D” ago). From right to left, write as the example.
down in a column
the bit numbers for By inspection, establish
DECIMAL
which is the highest decimal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 each bit that has a
1 in it. Beside each value in the table that will divide
HEXADECIMAL
bit number write into your starting value. In this
0 1 2 3 4 5 6 7 8 9 A B C D E F case it is 4,096 and (noting that
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 307
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
POWER VALUE
0
16 1
1
16 16
2
16 256
3
16 4,096
4
16 65,536
5
16 1,048,576
6
16 16,777,216
7
16 268,435,456

only integer values – whole Photo 6.6. Interactive decimal-binary-hex conversion


numbers – are used in the divi- screen, catering for up to 32-bit numbers.
sion answers) the sequence be-
binary: In reverse order, from 3 to
comes:
First write down as a table 0, write down your nibbles:
39923 / 4096 = 9 (= $9) the powers of 2 that make up a 1010 0111 0101 1101
4096 x 9 = 36864 4-bit binary value (nibble):
39923 - 36864 = 3059 which is the binary conver-
POWER 23 22 21 20 sion for $A75D (or 10100111
3059 / 256 = 11 (= $B) DECIMAL 8 4 2 1 01011101 as a 2-byte value
256 x 11 = 2816 rather than four nibbles).
3059 - 2816 = 243 Take as our example
$A75D. The right-hand value is
243 / 16 = 15 (= $F) $D. Hopefully, you will recall, or VALUE CONVER-
16 x 15 = 240 can work it out, that D is decimal
13, which is made up from the SION PROGRAM
243 - 240 = 3 (= $3)
following power-of-two values: A program that allows con-
Collecting the integer an- version between decimal, binary
swers plus the final remainder 8 + 4 + 1 = 13 and hex is available from the
gives us: 9, 11, 15, 3. Convert- So your table now becomes: main menu: run Binary, Hex,
ing the decimal integer answers Decimal Converter.
to hex gives: $9BF3. POWER 23 22 21 20 The program caters
DECIMAL 8 4 2 1 for binary numbers up to
HEX TO BINARY $D = 13 = 8 4 0 1 32 bits long – decimal
We before go any further we BINARY 1 1 0 1 (nibble 0) and hex maximums of
4,294,967,295 and
must explain the term nibble Therefore $D = 13 decimal $FFFFFFFF.
that’s about to be used. A nibble = binary 1101.
(or nybble) is a quaint computing The central box is split into
term and refers to a group of In a similar fashion, work seven horizontal sections (see
four bits, whereas a group of right to left taking each hex Photo 6.6). Sections 3 to 7
eight bits is generally known as value in turn. In this instance to (Binary to Decimal) can be se-
a byte. produce: lected using the up/down arrow
keys. In each section any
Conventionally, a byte is $5 = 5 = 0 4 0 1 individual character
split equally into two nibbles, left BINARY 0 1 0 1 (nibble 1) within the full value can
and right, comprising bits 7 to 4, be accessed using the
and 3 to 0. You would not, for $7 = 7 = 0 4 2 1 left and right arrows.
example, take the group com- BINARY 0 1 1 1 (nibble 2)
prising bit 5 to 2 as being a nib- The selected charac-
ble. ter can be changed and
$A = 10 = 8 0 2 0 the result of that change
Having clarified that, here’s BINARY 1 0 1 0 (nibble 3) is calculated in relation to
how to convert a hex value to the other four control-

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 308
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
lable sections and the results PANEL 6.3 – RELATIVELY SPEAKING
displayed. Try it! The full range
of control keys available is An important concept to appreciate in electronics is that nothing
stated in the left-hand box. happens instantaneously; everything takes a certain length of time to
change from one state to another, whether it is a switch changing
We believe the display and
from on to off, or a voltage changing from one level to another, or just
its options are obvious, but we
a fuse blowing.
will just clarify one small matter:
the “^’’ symbol will be seen in It may seem that the switch is either open or closed, contacts ei-
the Bit Value line, this indicates ther apart or touching, and at a molecular level this is true, but the
that the following number is a physical nature of a switch means that because of the broad area of
power (index), e.g. 2^4 means its conducting contacts, there is a period during switching off, for ex-
2.
4 ample, when the area of each contact which is actually touching the
other is changing progressively from full-area contact to point contact,
and only at the very final moment is the ultimate point contact broken.
DIRECT ENTRY During this period, the resistance between the contacts increases
The Binary, Hex and Deci- to the current flowing between them, and even at the moment when
mal Converter program allows the physical point contact is broken, an electrical arc might be formed
you to directly enter your own between the two open points, allowing current to still flow across them
values for conversion. When the until they are even further apart. So much for the instantaneous na-
highlight is active on one of the ture of an on-off switch!
five Binary to Decimal options, In digital electronic circuits, it is customary to think of the logic
press <ENTER>. At the bottom gates involved as responding to an instantaneous change from, say,
of the screen, value entry then logic 0 to logic 1 (from a low voltage to a high one). No such immedi-
becomes available. Enter the ate change takes place, it takes time for the change to occur and
value, press <ENTER> again there is a constant gradient through which the actual voltage level has
and the value is converted to the to pass; it does not just suddenly jump from 0V to 5V, for example.
other modes.
The time taken to make the transition may be short, possibly only
There are a few intercepts fractions of a millionth of a second, but it still exists, and the concept
to prevent you “crashing” the of synchronicity – two things occurring at the same moment – is only
program with most practical joke a convenience when working out the logic of a digital circuit.
entries! (But nothing to stop ma-
licious intent if you are really set In reality, the synchronization of various actions taking place in
on it! If you do get the screen order to create a further change is related to a “window” in time, dur-
messed up, return to the menu ing which all the required changes can occur at their own separate
and re-select the program.) rates. The window could be a mere picosecond; it could be half of
eternity; how it matters depends on what the circuit is required to do,
and as long as all those changes happen while the window is “open”,
SELF-TEST the circuit will behave as though they had all occurred at the same
moment. But, if any of them occur outside the window, the result may
Press <S> to test your un-
be unpredictable and undesirable.
derstanding of bin-hex-dec con-
version! With a bit of practice, swers for yourself, the ability to
and reference to our earlier dis- NEXT MONTH
do such conversions is invalu-
cussions, you should find that able. In part 7 we examine
it’s actually easier than you opamps, which are integrated
might think. circuits for use with analog sig-
Note that when asked to MORE EXPERI- nals and voltages. Amongst
convert a value to binary, you MENTS other things, opamps allow
enter the answer in groups of waveforms to be amplified,
You’ve learned that you can mixed, and generally processed
nibbles separated by a space.
count on us to offer you some in a variety of ways. We shall
This makes it easier to examine
interesting hands-on ideas each illustrate their principles and
your answer if it’s wrong.
month – you can count on us some of the ways in which they
If you really cannot work out again in this month’s Experi- can be used, to allow you, for
an answer, press <A> plus mental section, so clock onto it! example, to listen to the wave-
<ENTER> for it to be revealed. forms we discussed in Part 5.
But it’s worth trying to get an-
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 309
Maxfield & Montrose Interactive Inc
TEACH-IN 2000

TEACH-IN 2000 – EXPERIMENTAL 6


BINARY AND DECIMAL COUNTERS
In the latter part of this device (which is increasingly the
month’s Tutorial, we discussed case with integrated circuits that
binary numbers and the way in become more and more com-
which they relate to decimal and plex).
hexadecimal values. We are R R R

22
23
24

26

30

33

35
25

27
28
29

34
0 1 2 What we have to content
now in a position to introduce an ourselves with is a boxed outline
integrated circuit that allows you with some pin numbers and their
to physically see the binary D a D a a D descriptions. In the circuit dia-
counting process in action. We k 0 k 1 2 k
gram, note first the pins to which
refer, of course, to a binary 74HC4024 the power lines are connected.
counter plus some LEDs! As with the logic gates dis-
There are numerous types cussed in the Tutorial these are
of counter manufactured, with D a D a a D a D pin 7 for 0V (GND) and pin 14
k 6 k 5 4 k 3 k
such descriptive names as bi- for +VE (this is not always true
nary ripple counter, synchronous R R R R for other digital devices). The
22
23
24
25
26
27
28
29
30

33
6 5 4 3
binary counter, asynchronous recommended operating volt-
binary counter, binary-coded- ages are between 2V and 6V,
decimal counter, Gray counter, although this device will with-
decade counter, Johnson stand up to 7V for short periods
CLOCK IN
counter, up/down counter, and FROM IC1a PIN 2 (but never above 7V).
so on. Far too many to discuss The Clock input is the next
in detail – and there are even Fig.6.10. Breadboard layout
for the binary ripple counter important pin. This is the pin into
variants on these! which the data pulses that the
We shall just concentrate on
experiment. counter has to count are input.
two types, a 7-bit binary ripple The “>” symbol in the pinout dia-
counter, and an 11-output quencies. gram also indicates that this is
decade counter. the Clock input pin. It is fre-
SYMBOLICS quently omitted in many circuit
diagrams.
BINARY COUNTER The circuit diagram for this
Note also the small circle at
The 7-bit binary ripple setup is shown in Fig.6.11, and
this input pin. It indicates that
counter we shall use is the the pinouts for the 74HC4024
inside the device the pulse logic
74HC4024. Find one from your are in Fig.6.12. Unlike with logic
level to which the device re-
components bag and connect it gates, there is no “official” sym-
sponds is “inverted”. You met a
into your breadboard, together bol to illustrate the nature of this
with the required LEDs and re- +6V
14
sistors, as shown in Fig.6.10. As +VE
12
usual, touch a grounded 1
Q0
CLOCK 11
(earthed) item to discharge INPUT
CLOCK Q1
9
Q2
static electricity from your body 74HC4024
Q3
6

before handling the device (and 2 Q4


5
RESET 4
ensure that it’s the right way Q5
3
Q6
round!). a a a a a a a
GND D6 D5 D4 D3 D2 D1 D0
If you only have five 470W 7 k k k k k k k
resistors available, you could R6 R5 R4 R3 R2 R1 R0
470W 470W 470W 470W 470W 470W 470W
use any value between 100W
and 1kW for the other two.
0V
Connect up power and
watch the LEDs while adjusting
Fig.6.11. Circuit diagram for the binary ripple counter
the oscillator for different fre- experiment.
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 310
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
SYMBOL PINOUTS
(SEE TEXT) N.C. = NO CONNECTION

14 74HC4024
+VE
12
Q0 1 CLOCK +VE 14
1 11
CLOCK Q1
9 2 RESET N.C. 13
Q2
6 3 Q6 Q0 12
Q3
5
2 Q4 4 Q5 Q1 11
RESET 4
Q5
3 5 Q4 N.C. 10
Q6
GND 6 Q3 Q2 9
7 GND N.C. 8
7

FUNCTION TABLE
CLOCK RESET OUTPUT STATE

L NO CHANGE

L ADVANCE TO NEXT STATE

X H ALL OUTPUTS ARE LOW

X = DON'T CARE
Photo 6.7. Breadboard showing the binary Fig.6.12. Symbol, pinouts and
counter and LEDs. Part of the oscillator is function table for a 74HC4024
shown at the left. binary ripple counter.

similar situation with the NAND, cle even though inversion oc- function (Reset, Clock, Enable,
NOR and XNOR gates, although curs. Some circuits show a bar etc.) is permitted or occurs when
in their case the inversion took line above the description for that pin is taken (or is already at)
place on the output data. such a pin (as we have done in high.
The significance about the Fig.6.11). Indeed, the use of a
logic level to which a device bar to signify inversion is ar-
guably more commonplace than “Q” OUTPUTS
such as a counter responds is
important to note. Many devices the circle. The remaining useful pins
do not respond to the actual are labeled Q0 to Q6 (in some
voltage level at an input (as did circuits or pinout diagrams, they
RESET LOGIC may be labeled as Q1 to Q7).
the logic gates in the Tutorial)
but to the change in logic level. Pin 2 of the 74HC4024 is Note that three pins have no
the Reset pin. When Reset is at function (8, 10 and 13). Note
In the case of the
logic 0 (low), the counter is per- also the use of “Q” to signify an
74HC4024, the change re-
mitted to count any pulses that output; conventionally, this is the
sponded to is that from high to
enter the Clock pin. Two things letter normally used with digital
low, and the counter adds 1 to
happen when the Reset pin is devices such as counters
its internal count value. The de-
taken high (logic 1). First, the (whereas “Y” was used with the
vice is said to respond to the
entire count within the device is gates, earlier).
trailing edge of a pulse (a term
reset to zero. Second, the We have said that the
we used when looking at pulses
counter is prevented from count- 74H4024 is a 7-bit counter. Pins
in the Tutorial).
ing any further pulses until Re- Q0 to Q6 are the outputs at
When the pulse changes set has been returned low. which the seven bits of the inter-
from low to high, the device
Note that in some types of nal binary count value are ac-
does not respond in any way
counter, Reset may be active- cessed. Referring you back to
and the count remains as it was.
low, in other words, Reset oc- what you have learned about
(The 74HC4017 we shall use
curs when the pin is set low binary numbers, output Q0 cor-
later responds to the change
(logic 0), but counting is permit- responds to bit 0, Q1 to bit 1,
from low to high – i.e. to the
ted when the pin is high. etc. It is to tie in with this num-
leading edge).
The terms active-low and bering that the resistors and
Be aware that not all circuit LEDs are numbered from 0 to 6
active-high are frequently en-
diagrams show the inversion cir- in Fig.6.11.
countered in electronics. The
latter means that the stated BINARY COUNT-UP
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 311
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
CLOCK IN
FROM IC1a PIN 2
If you run the 8-Bit Binary actual decimal value that the bits
Logic program and set the 8-Bit represent shown in the Cor-
OR line A to zero, and then keep rected Input Byte box.
pressing the <+> key the binary R

16

26

36
14
15

17

20
21

23
24
25

27
28
29
30
31
32
33
34
35
22
sequence will count up in ones 2

(increment) at each press, from FREQUENCY


0 to 255 and then back to zero DIVISION D a D a a D a D a D
4 k 8 k 9
k 10 k 9
to start counting again. k

A further experiment you IC1 74HC4017


This is what’s happening can try is to select any of the
inside the 74HC4024 (except counter outputs as the source of
that it only has seven bits). From the data signal when running the k D k D k D
5 a 1 a 0 a
D k D k D k
a 2 a 6 a 7
a reset value of 0000000, it will Computer As Frequency R
increment each time the clock

26

36
14
15

18

20

24

27

29
30
31

33
34
35
19

21
22
23

25

28

32
Counter program. 1

pulse goes from high to low.


When it reaches a count of deci- This will enable you to really
mal 127 (binary 1111111), at the wind up the oscillator rate, yet
next negative-going clock pulse still be able to see a meaningful
frequency value displayed on
Fig.6.13. Breadboard layout
it rolls-over to 0000000 again. for the 74HC4017 decade
screen (which you should men-
That, then, is the sequence tally multiply by the division rate counter.
you should be seeing on the provided by the counter pin se-
LEDs connected to your lected – each output is at half disconnect the counter’s Clock
74HC4024 (although the bread- the rate of the previous one, re- input pin 1 from the oscillator,
board space available prevents member!). and couple it to interface OUT3
them from being inserted in the (controlled by key <3>). This
ideal visual sequence). What we also suggest you
do is to put the 74HC4024’s Re- puts the counter’s Clock and
As with the logic gates, set under computer control. Dis- Reset total under finger-tip con-
there is a truth table for the connect the link between the trol. The Mutual Melding of Man,
74HC4024, except that it is ac- counter’s pin 2 and 0V. Now link Mind and Machine, no less!
tually referred to as a Function pin 2 to OUT2 of the interface.
Table and takes a somewhat Repeatedly pressing key <2>
different format. It is shown as
RIPPLE
will then cause the counter to
part of Fig.6.12. run or be reset. You should be Ripple, incidentally (but sig-
The table shows the output able to see the result on the nificantly), in this context refers
state in relation to the conditions LEDs and on the screen. to the way that the counter’s in-
on the counter’s Clock and Re- ternal sections respond. (Note
If you are feeling further ad- that ripple has a different mean-
set pins. Note the upwards and venturous (and why not?!), also
downwards waveforms in the +6V
clock column. The first signifies 16
the rising (leading) edge of an +VE
3
Q0
input clock pulse, the second CLOCK 14
CLOCK Q1
2
INPUT a
4
shows the falling (trailing) edge. Q2 a D0
74HC4017 7
These are commonly encoun- Q3
10
a D1 k
Q4
tered symbols in digital electron- 15
RESET 1 a D2 k
Q5 a D3 k
ics. Q6
5
a D4 k
6
Q7
If the counter’s Q0 to Q4 13 9
a D5 k
ENABLE Q8 a D6 k
pins are linked to the computer Q9
11
a D7 k
12
interface input pins IN0 to IN4, CARRY OUT a D8 k
you can observe the count se- GND D9 k
8 a
quence for the first five bits via D10
k

the Parallel Port Data Display/ k

Set program. With the oscillator R2 R1


470W 470W
rate set slow enough, the bits
will be seen to change state in
0V
the two upper boxes, with the
Fig.6.14. Circuit diagram for the 74HC4017 decade counter.
Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 312
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
SYMBOL PINOUTS
74HC4017
16
+VE
3
Q0
14 2 1 Q5 +VE 16
CLOCK Q1
4 2 Q1 RESET 15
Q2
7
Q3 3 Q0 CLOCK 14
10
15 Q4
RESET 1 4 Q2 ENABLE 13
Q5
5 5 Q6 CARRY OUT 12
Q6
6
Q7 6 Q7 Q9 11
13 9
ENABLE Q8
11 7 Q3 Q4 10
Q9
12 8 GND Q8 9
CARRY OUT
GND
8

FUNCTION TABLE
CLOCK CLOCK RESET *OUTPUT STATE
ENABLE

Photo 6.8. Breadboard showing the L X L NO CHANGE

X H L NO CHANGE
decade counter experimental circuit, X X H RESET COUNTER
with part of the oscillator seen to the Q0=H, Q1 TO Q9=L
C.O.=H

left, and part of the ADC chip to L L ADVANCE TO NEXT STATE

the right. Take care that crossing X L NO CHANGE


X L NO CHANGE
link wires do not touch. H L ADVANCE TO NEXT STATE

X = DON'T CARE
ing in the context of power sup- 74HC4024 and in- * CARRY OUT = H FOR Q0, Q1, Q2, Q3 OR Q4 = H
CARRY OUT = L OTHERWISE
plies – which we will discuss sert the
later in this Teach-In series.) In 74HC4017. Con- Fig.6.15. Symbol, pinouts and function
simple terms, the counter con- nect its pins as table for the 74HC4017 decade counter.
tains several divide-by-two cir- shown in
ne
cuits in a chain. It takes time for Fig.6.13, complete with LEDs
eded for the 10 LEDs D0 to D9,
each counter to react to a trigger D0 to D9 and resistors R1 and
since only one can ever be on at
pulse from the preceding R2. You will need to “steal” the
once.
counter. tenth LED from the oscillator,
unless you bought more than You will see from the circuit
The delay is only short
the suggested quantity of 10. diagram that, in common with
(nanoseconds for the
Ignore D10 for the moment. the binary counter, this decade
74HC4024), but the total delay
counter has a Clock input (pin
as the pulses ripple through Power up your breadboard
14) and a Reset pin (pin 15). As
stages to the final output can be and watch the sequence of the
we said earlier, the 74HC4017
critical to other circuits, which LEDs. Adjust the oscillator rate
increments the count on each
may rely on the synchronization so that you clearly see the steps
rising edge of the clock pulse.
between a multi-stage counter’s of the count.
clock pulse and the setting of an The count is reset to 0 when
Whereas the 74HC4024
output pin. the Reset pin is high. However,
counted in binary, from 0 to 127,
when the Reset pin is low, the
There are counters in which the 74HC4017 decade counter
continuation of the count de-
the internal circuitry is designed counts in steps from 0 to 9,
pends on the status of a third
so that each section is triggered rolling over to begin the count
pin, Enable, pin 13. Not surpris-
at the same time. These coun- from 0 again following 9. During
ingly, this pin enables or inhibits
ters are referred to as syn- the count only one output is ever
the clock count. Because there
chronous. high at any time.
is a bar-line above the word En-
The pinouts for the able (or a circle on its input), we
DECIMAL COUNTER 74HC4017 are shown in know that the counter is enabled
Fig.6.15, the circuit diagram for when the pin is low.
When you can tear yourself the connections on your bread-
away from the fascination of bi- The ten outputs are labeled
board is illustrated in Fig.6.14.
nary counting, have a look at the Q0 to Q9, which ties in with the
Again the LEDs are numbered
attributes of a decade counter, count value that a logic 1 on the
from zero to correspond with the
the 74HC4017. Remove the respective pin represents.
output numbers. Note that only
one ballast resistor (R1) is The function table for the

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 313
Maxfield & Montrose Interactive Inc
TEACH-IN 2000
74HC4017 is shown as part of When you are ready to consider LED from one of the outputs
Fig.6.14. An interesting point to them, you’ll find that data sheets (but not from outputs 0 or 5).
note is that the Enable pin can give typical timing values for Add the LED to the Carry Out
also act as a clock signal to the practically everything! pin as D10, via the already in-
counter. When Clock is held There is an eleventh output serted resistor R2). Power back
high and Enable is taken from pin, the Carry Out pin. This pin up again and observe the se-
high to low, the count advances goes high when the counter is quence.
to the next state. reset or rolls over to zero. It re- As with the 74HC4024, you
In most circuits it is more mains high until a count of five is can connect up to five outputs to
usual to use Clock rather than reached. the computer interface at IN0 to
Enable as the clocking signal. The Carry Out signal is of IN4. You can also connect the
However, what this option high- benefit in a variety of situations; Clock, Reset and Enable pins to
lights is that Enable should such as where you might wish to the interface outputs OUT2 to
never be taken low when the couple (cascade) two or more OUT4, controlling them from
clock is high if you wish to pre- decade counters in series, for your keyboard when running
serve the count value existing at example. In this case the rising program Parallel Port Data Dis-
the last clock pulse. edge of the Carry Out signal play/Set.
It is subtleties like this that would be used as the clock So there’s a whole raft of
abound in digital electronic cir- pulse for the next stage. Thus ideas to play around with until
cuits, especially when the overall the first counter would count next month. You could also in-
circuit complexity is great. You units from 0 to 9 and the second clude some experiments with
always need to consider the im- stage count the decades from the logic gates, interfacing them
plications of how the timing of 10 to 90. A third stage could to the computer and counters as
different signals can affect the count the hundreds, 100 to 900, well. Till then this author’s out
response. In reality, at this stage and so on. for the count!
of your learning, you need not Observe the Carry Out pin
concern yourself about them. in action by removing, say, the CORRECTION
In Part 5, Fig.5.6. Add link
wire to join rows E and F of col-
umn 42.

Copyright © 2000 Wimborne Publishing Ltd and EPE Online, April 2000 - www.epemag.com - 314
Maxfield & Montrose Interactive Inc