Trng i Hc Bch Khoa H Ni

Vin in T - Vin Thng

======o0o======

BO CO KT QU THC TP K THUT
ti:

Trin khai h thng

FFT 128 radix 22 trn FPGA

Sinh vin thc hin: Vng ng Huy

M s sinh vin: 20131809
Lp: K s ti nng
Kha: 58

H Ni, 8/2016

Bo co thc tp k thut

Li ni u
Trong t thc tp trung tm th nghim thit k vi mch v tch hp h thng
EDA-BK thuc phng nghin cu BKIC, Vin in t - vin thng, i hc Bch
Khoa H Ni, nh c s quan tm gip nhit tnh ca thy, cc anh, cc bn ang
lm vic trn phng nghin cu to iu kin thun li nht gip em hon thnh
tt nhim v thc tp ca mnh. Trc khi bc vo t thc tp, em xc nh r
mc ch ca t thc tp ny: lm quen vi mi trng lm vic, ci thin v nng
cao cc k nng mm cn thit cho cng vic sau ny nh vit bo co, trnh by mt
vn , c ti liu ting anh, v c cng c nng cao cc k nng chuyn ngnh.
t thc tp ko di mt thng (t ngy 11/7/2016 n ngy 19/8/2016) gip
em hc c rt nhiu iu, khng ch cc k nng chuyn ngnh m cn c v thi
, cch gii quyt khi gp mt vn kh khn, gip em quen vi mi trng lm
vic ca k s, i hi s tp trung, nghim tc gip hon thnh cng vic v nhim
v c giao. c lm vic vi cc bn v cc anh, cc ch cng cc thy, c cng
gip em ci thin c cc k nng lm vic nhm.
Trung tm th nghim thit k vi mch v tch hp h thng l phng nghin cu
c trang b cc trang thit b hin i phc v cho vic hp tc v nghin cu vi
mch, rt thun li gip cho sinh vin c tip cn v tm hiu cc cng ngh thit
k vi mch thc t, cng c cho kin thc hc c sch v trn trng lp. Bc
vo thc tp vi rt nhiu b ng, l lm nhng s nhit tnh, thn thin v ci m
ca cc anh v cc bn ang lm vic trong phng nghin cu gip em bt b ng
v lm quen nhanh chng vi mi trng v bt tay vo lm cc cng vic c giao.
Em xin chn thnh cm n Tin S Nguyn c Minh, Tin S ng Quang Hiu,
Thc S Dng Tn Ngha tn tnh hng dn v h tr em trong qu trnh thc
tp. Em cng xin gi li cm n n bn b, cng tp th thy c v cc bn trong
phng th nghim BKIC lun ng h, gip v to iu kin cho em hon thnh
tt t thc tp ny.

Bo co thc tp k thut
1. Ni dung
1.1 Gii thiu chc nng, nhim v, c cu t chc ca n v tip nhn
1.1.1 C cu t chc ca n v tip nhn
Trung tm th nghim thit k vi mch v tch hp h thng (gi tt l EDABK)
c thnh lp ngy 28/4/2011, l mt trong nhng phng nghin cu thuc Vin
in t - vin thng i hc Bch Khoa H Ni. EDA-BK hin c rt nhiu nh
khoa hc l tin s, thc s v hn 30 sinh vin, nghin cu sinh c am m nghin
cu trong lnh vc in t - Vin thng.
Hin ti, trung tm c hot ng, qun l di s iu hnh ca cc thy, c:
TS. Nguyn c Minh
Thit k v kim tra t ng cc h thng s v cc h nhng.
TS. Nguyn c Minh tt nghip tin s ti i hc Kaiserslautern, CHLB c
vo thng 2 nm 2009. Hin nay, TS. Minh nghin cu v ging dy ti Vin in
t Vin thng, trng i hc Bch Khoa H Ni. TS. Minh tng l nghin
cu vin tham gia cc d n nghin cu trong cng nghip vi cc cng ty Onespin
Solutions, Acatel-Lucent, Infineon Technologies. TS. Minh quan tm nghin cu v
thit k vi mch s, c bit l cc vi mch x l bng gc trong thng tin di ng
nh: WCDMA, OFDM, UWB, MIMO,... Ngoi ra TS.Minh cn tp trung vo cc
thut ton m hnh ha v kim chng ton hc cc h thng trn chip cng nh h
thng nhng.
TS. ng Quang Hiu
Pht trin cc thut ton x l tn hiu trong thng tin
Tt nghip PhD t trng TU Delft (H Lan) vo 2/2008. Hng chuyn mn
chnh v x l tn hiu trong thng tin v tuyn. Chuyn gia v cng ngh mi trong
truyn tin nh: WCDMA, OFDM, UWB, MIMO,... Thit k v m phng cc h
thng thng tin v tuyn th h mi bng cng c Matlab/Simulink. Ngoi ra, TS.
Hiu cn ang nghin cu v cc k thut giu tin trong thng tin qung b,
cognitive radio, cooperative communications, cc thut ton trin khai m knh

Bo co thc tp k thut
(LDPC) vi tc cao, tn hao t nng lng, cc h thng thng tin phc v y t
(body area wireless sensor networks) v c bit l cc k thut thng tin ng dng
trong in thoi di ng (NFC, Bluetooth LE, v.v.)
TS. Hong Phng Chi
Qun l d n
ThS. Trn Mnh Hong
Qun l nhn s, i tc v hc bng
ThS. Dng Tn Ngha
X l tn hiu trong thng tin v tuyn, truyn thng bng siu rng, nhn din
du vn tay.
TS. Phm Nguyn Thanh Loan
Chuyn v thit k vi mch tng t.
Phng nghin cu c t ti phng 611 v 618 ti th vin in t T Quang
Bu, i hc Bch Khoa H Ni, s 1, i C Vit, Hai B Trng, H Ni.
1.1.2 Hng nghin cu
Mc tiu nghin cu chnh ca EDA-BK l pht trin cc b x l bng c s
(baseband processor) cho thng tin v tuyn / di ng th h mi. Cc ni dung
nghin cu bao gm:

Pht trin cc thut ton x l tn hiu cho cc h thng tin v tuyn th h

mi (UWB, OFDM, WCDMA, v.v.) v ng dng.

Pht trin cc thut ton v thit k b thu pht tn hiu s tn hao t nng

lng phc v cho cc mng vin thng th h mi (WSN, RFID, cognitive radio,
relay networks, v.v.)

Thit k phn mm chuyn dng cho in thoi di ng (trn nn Android,

iOS).

Bo co thc tp k thut

Pht trin cc ng dng h tr tng tc vi ngi s dng trong thng tin

qung b (pht thanh, truyn hnh).

Thit k IC v h thng nhng x l video v audio dng trong mng di ng

th h mi.

Kim tra t ng h thng s, IC v h thng nhng

Xy dng h thng t ng thu thp d liu t xa; lu tr, tng hp v phn

tch d liu.

Pht trin cc thut ton h tr nh v vi chnh xc cao (GPS, localization).

1.1.3 Hng o to
Ngoi nhng kha hc chnh qui theo cc chng trnh i hc / sau i hc do
trng H BK qui nh, EDA-BK cn cung cp cc kha hc ngn hn v DSP,
Embedded Systems, Digital Communications, v.v. cng nh cc kha hc chuyn
su khc theo yu cu ca doanh nghip.
Cc kha hc ngn hn gm c :

Thit k vi mch s c bn s dng Verilog/VHDL, thc hin trn FPGA

Thit k vi mch s nng cao bng phn mm Synopsys

Thc hin cc thut ton x l tn hiu s trn Matlab

Thit k, m phng b thu pht s (WCDMA, MIMO-OFDM, UWB) dng

Matlab / Simulink

Thit k vi mch h thng thng tin s dng DSP Builder kt hp

Matlab/Simulink thc hin trn FPGA

Thit k h thng nhng

Lp trnh nhng trn in thoi di ng Android / iOS

Bo co thc tp k thut
1.1.4 Hc bng
Nhng sinh vin xut sc trong EDA-BK s c cp hc bng vi nhiu mc
khc nhau, c ti tr t nhiu ngun khc nhau. Ngoi ra, EDABK cng h tr c
s vt cht gip sinh vin thc hin tt cc ti ca mnh.
1.1.5 Tuyn dng
EDA-BK lin tc tuyn chn cc sinh vin (bt u t nm th 2, h i hc chnh
qui), cc hc vin cao hc v cc nghin cu sinh chuyn ngnh in t Vin thng,
in, CNTT. Ti EDA-BK, cc hc vin v sinh vin c th tham gia lm n tt
nghip (i hc, cao hc, tin s), n mn hc, v ti cc cp. Ngoi ra, ty
theo nh hng ca tng c nhn, ngi theo hc cn c trc tip o to chuyn
su theo nhiu lnh vc, tham gia cc kha hc ngn hn v i thc tp cc doanh
nghip bn ngoi.

Bo co thc tp k thut
1.2 Ni dung thc tp
1.2.1 t vn
Trong ngnh in t vin thng chng ta, vic phn tch ph nh ph nng lng,
ph bin , ph pha ca tn hiu ni chung v ph ca tn hiu s ni ring trong
min tn s ng mt vai tr ht sc quan trng. N cho ta bit vai tr ng gp ca
cc thnh phn tn s trong tn hiu nh th no, nng lng ca chng ra lm sao,
t chng ta c phng hng x l tn hiu mt cch thch hp. Vn t ra
l lm th no thc hin bin i tn hiu s t min thi gian sang min tn s
quan st ph ca n. Cu tr li n gin nht chnh l s dng bin i Fourier ri
rc DFT (Discrete Fourier Transform).
Bin i Fourier ri rc c s dng trong rt nhiu cc lnh vc, n c s
dng trong vic x l ting ni, x l nh,. S khng phi l phng i nu nh ni
l bt c vic g lin quan n x l tn hiu s u phi dng n bin i Fourier.
Tuy nhin vic s dng bin i Fourier ri rc c mt vn , l vic tnh ton
tng i phc tp khi chiu di d liu cn tnh ton tng ln. M nh ta bit mt
file nh, hay mt tn hiu bt k thng c di kh l ln, do nu ch tnh DFT
thng thng th thi gian thc hin s rt l lu v phc tp, do s khng p ng
c yu cu v mt thi gian ca ngi thc hin. Th tng tng DFT nh l 1
c my sn xut sn phm, nh sn xut th mun my lm vic cng nng sut, cho
ra cng nhiu sn phm trong thi gian ngn nht thu li lng gi tr thng d ln
hn so vi cc i th khc, th nhng c my DFT tuy c lm ra sn phm tt nhng
tc qu chm th chc chn nh sn xut s khng hi lng mt cht no. Khi
nh sn xut phi thay i, phi s dng khoa hc k thut nng cp cho c my
ny sao cho cng cho ra kt qu tt y nh c m tc phi c ci thin nn
nhiu ln. Chnh v vy m thut ton bin i Fourier nhanh FFT (Fast Fourier
Transform) ra i.
tng ca thut ton FFT l k thut chia tr. Thay v vic tnh DFT cho c
1 tn hiu c di ln chng ta s thc hin tnh DFT cho tng on tn hiu nh
hn trong tn hiu ri t kt qu thu c chng ta tnh ngc li DFT ca tn hiu
cn tnh ban u.

Bo co thc tp k thut
Mt trong nhng cch tnh rt FFT ph bin l khi di dy l ly tha ca 2 do
Cooley v Tukey a ra vo nm 1965 (thng gi l FFT c s 2). Yu cu ca
phng php ny l dy tn hiu cn tnh phi c di N phi l ly tha ca 2.
Cch tnh ca phng php ny l thc hin chia dy tn hiu cn tnh thnh 2 na c
di N/2 ri tnh DFT ca 2 dy nh ny. Mi dy nh li c th c tnh bng
cch tip tc chia nh chng ra thnh 2 dy con nh hnCng vic trn c lp
li n khi no vic tnh DFT ca dy con tr nn n gin ri, khng cn chia na
(thng l khi di dy con ch cn l 2), khi t kt qu DFT ca dy con chng
ta tnh ngc li DFT ca dy to.
Di y l s gii thut ca thut ton FFT c s 2:

Start
N = 2^k

False

Chia thnh 2 dy con

di N/2

Chiu di dy con = 2

True

Tnh DFT

End

Figure 1.1 S gii thut ca thut ton FFT c s 2

Bo co thc tp k thut
FFT c vai tr rt quan trng:
-

FFT nng cao tc , chnh xc ca x l s tn hiu.

FFT m ra mt lnh vc rt rng ca phn tch ph: vin thng, thin vn, a
l, chn on y khoa,

FFT khi li li ch ca nhiu ngnh ton hc m trc y ngi ta cha

khai thc ht.

FFT t nn mng cho vic tnh ton cc bin i khc nh bin i Walsh,
bin i Hamadard, bin i Haar,

T FFT c s 2, gi y chng ta cn c cc c s khc nh c s 4, c s 8, c

s 2^2, c s 2^3 cng vi nhiu kiu cu trc tnh FFT khc nhau nh song song,
SDF(single delay feedback), MDC (multipath delay commutator), ti ch (in place),
thc l,ngy cng khng nh c vai tr quan trng ca FFT.
Chnh v tm quan trng ca vic tnh ton FFT, phng nghin cu EDA BK
v ang pht trin vic trin khai thut ton tnh FFT 128 im theo kin trc SDF s
dng c s 2^2 trn bo mch FPGA phc v cho cc mc tiu v sau. B cng c
c s dng l phn mm MATLAB cng cng c m phng Simulink, phn mm
m phng ModelSim, cng c tng hp phn cng l phn mm ISE Design Suit ca
Xilinx v s dng trn kit Atlys.
1.2.2 M t ti
Cc yu cu cn phi thc hin:
-

Trin khai thut ton tnh FFT 128 im vi c s 2^2 theo kin trc SDF.

S dng phn mm MatLab, Simulink xy dng m hnh v kim tra kt

qu.

Vit code Verilog m t phn cng ca khi FFT trin khai trn FPGA, tng
hp code Verilog bng cng c trn MatLab hoc dng phn mm ISE Design
Suit.

Thc hin m phng ng thi (Co Simulation) kin trc xy dng trn
Simulink v khi phn cng xy dng t code Verilog, kim tra kt qu.

Bo co thc tp k thut
-

Trin khai thut ton trn kit Atlys ca Xilinx bng phn mm tng hp ISE
Design Suit.

Thc hin FPGA in loop, kim tra kt qu.

T nhng yu cu m ti a ra, thc hin c n, yu cu ngi thc hin

u tin phi c nhng kin thc c bn v FFT, tip l kin thc v lp trnh trn
MatLab, bit thc hin m phng trn Simulink, Co Simulation vi ModeSim v
FPGA in loop v c nhng kin thc c bn v FPGA v ngn ng lp trnh phn
cng Verilog.
1.2.3 Bo co cng vic c giao
1.2.3.1 Nhng kin thc c bn v FFT
y chng ta ch nghin cu v FFT phn theo tn s DIF.
Cho x[n] l 1 dy c chiu di N. Bin i Fourier ri rc DFT ca x[n] c tnh
theo cng thc sau y:
N 1

X k x n .e

2
kn
N

, k 0, N 1

1.2.3.1

n 0

Nu t W

kn
N

2
kn
N

, h s ny gi l twiddle factor th cng thc (1) c th c

vit li nh sau:
N 1

X k x n .WNkn , k 0, N 1

1.2.3.2

n 0

T cng thc (1.2.3.1) ta thy, vi mi gi tr ca k ta phi tnh N php nhn phc

v N 1 php cng phc. M k ly N gi tr t 0 n N 1 nn tng s php nhn
phc cn thc hin l N 2 php tnh, tng s php cng phc cn thc hin l

N N 1 N 2 php tnh. T s php nhn thc cn thc hin l 4N 2 php tnh,

cn s php cng thc cn thc hin l N 4 N 1 4 N 2 php tnh. Nh vy khi
di N ca dy tn hiu cn thc hin DFT x[n] tng ln, s lng php nhn v php
cng thc s v cng ln, lm tn thi gian tnh ton v dung lng b nh my.
Th cn khi s dng FFT th sao?

Bo co thc tp k thut
Trc tin ta s xem xt FFT vi c s 2.
T cng thc (1.2.3.2) ta c:
N 1

X k x n .WNkn
n 0

N /2 1

N /2 1

n 0

n 0

= x n .WNkn

N /2 1

k
= x n 1
n 0

N k ( n N )

x n .WN 2
2

x n .WNkn
2

Do ta c th tch dy X(k) ra thnh 2 dy nh sau:

X 1 2k1

N /2 1

n 0

X 2 2k1 1
k 0,

x n x n 2 .W
N /2 1

kn
N /2

x n x n 2 .W

n
N

n 0

.WNkn/2

N
1
2

Ta thy X1 v X2 chnh l bin i DFT N/2 im, vy ta c th t:

x1 n
x2 n
n 0,

N /2 1

x n x n 2
n 0

N /2 1

x n x n 2 .W
n 0

n
N

N
1
2

Nh vy ta tch vic tnh DFT ca dy x[n] c di N ra thnh vic tnh DFT

ca 2 dy con x1 n , x2 n vi di N/2. S tnh ton c minh ha nh sau:

Figure 1.2 M hnh cnh bm ca FFT c s 2

10

Bo co thc tp k thut
Kin trc trn c gi l kin trc cnh bm, y l 1 phn t c bn trong mi
k thut tnh ton FFT.
2

N
Nh vy s php nhn thc cn thc hin l 4 N 2 , s php tnh thc cn
2
thc hin cng l N 2 . Nh vy s php tnh cn thc hin gim i ng k so vi
vic thc hin tnh trc tip DFT ca dy x[n]. t c hiu qu hn na ta li
c th thc hin chia dy x1(n) v x2(n) ra thnh 2 dy con. S thc hin c th
xem li ti Figure 1 trong phn 1.2.1. Di y l 1 s tnh ton cho thut ton
FFT c s 2 khi u vo x(n) c di N = 8.
Radix 2 8-points FFT
x(0)

X(0)

x(1)

X(4)

x(2)

X(2)
W(0,8)

x(3)

X(6)
W(2,8)

x(4)

X(1)
W(0,8)

x(5)

X(5)
W(1,8)

x(6)

X(3)
W(2,8)

W(0,8)

x(7)

X(7)
W(2,8)

W(3,8)

Figure 1.3 S thut ton FFT c s 2 cho 8 im

y l bng so snh s lng cc php tnh phc cn thc hin gia vic tnh DFT
trc tip v vic s dng FFT c s 2:

11

Bo co thc tp k thut
Table 1.1 Bng so snh s lng php tnh phc cn thc hin gia tnh DFT trc
tip v dng FFT c s 2.
Dng FFT c s 2

Tnh DFT trc tip

S im

S php nhn

S php cng

S php nhn

S php cng

phc

phc

phc

phc

N2

N2 N

N
log 2 N
2

N log 2 N

16

12

16

256

240

32

64

64

4096

4032

192

384

256

65536

65280

1024

2048

1024

1048576

1047552

5120

10240

Nh ta thy trong bng 1, s lng php tnh phc cn thc hin gim i mt cch
ng k khi di N tng ln.
1.2.3.2 FFT c s 2^2
T cng thc (1.2.3.2):
N 1

X k x n .WNkn , k 0, N 1

1.2.3.2

n 0

t:
N
N
n1 n2 n3
2
4
k k1 2k 2 4k3
n

Vi n1 0,1, n2 0,1, n3 0,

N
N
1, k1 0,1, k2 0,1, k3 0, 1 th (1.2.3.2) c
4
4

th vit li nh sau:

12

Bo co thc tp k thut

N /4 1 1

X k1 2k2 4k3

n3 0

N /4 1 1

x 2 n 4 n
1

n3 0 n2 0 n1 0

N /4 1 1

N
N
k1 2 k2 4 k3 2 n1 4 n2 n3
x n1 n2 n3 .WN

n2 0 n1 0 2
1

x 4 n

n3 0 n2 0

n k n k
nk

n3 . 1 1 1 2 2 . j 2 1 .WNn3 ( k1 2 k2 ) .WNn3/4k3

N
k
nk
nk

N
n3 1 1 x n2 n3 . 1 2 2 . j 2 1
2

.WNn3 ( k1 2 k2 ) .WNn3/4k3
T y ta c th tch X(k) ra thnh 2 dy con c chiu di N/2 nh sau:

X 0, k2 , k3
X 1, k2 , k3

N /4 1 1

x 4 n

n3 0 n2 0
N /4 1 1

x 4 n

n3 0 n2 0

N
nk

N
n3 x n2 n 3 . 1 2 2 .WN2 k2n3 .WNn3/4k3
2

4
N
nk
n
N
1 2 k n
n3 x n2 n 3 . 1 2 2 . j 2 .WN 2 3 .WNn3/4k3
2
4

t:

N
N

N
x1 n2 , n3 x n2 n3 x n2 n3
2
4

4
N
N
N
x2 n2 , n3 x n2 n3 x n2 n3
2
4
4
Khi ta li c th tip tc khai trin tip X 0, k2 , k3 , X 1, k2 , k3 ging

X k1 , k2 , k3 nh sau:
X 0, k1 , k2

N /4 1 1

x n , n . 1

n3 0 n2 0

N /4 1

x n 1

n3 0

k2

n2 k2

.WN2 k2n3 .WNn3/4k3

x1 n3 .WN2 k 2n3 .WNn3/4k3

4

Tip tc tch X 0, k2 , k3 thnh 2 dy c di N/4:

13

Bo co thc tp k thut
X 0,0, k3
X 0,1, k3

N /4 1

x n x n
1

n3 0

N /4 1

x n x n
1

n3 0

N 0 n3 n3k3
.WN .WN /4
4

N 2 n3 n3k3
.WN .WN /4
4

Tng t vi X 1, k2 , k3 ta c:

X 1, k1 , k2

N /4 1 1

x n , n . 1

n3 0 n2 0

n2 k2

. j 2 .WN
n

1 2 k2 n3

.WNn3/4k3

N 1 2 k n
k

= x2 n3 j. 1 2 x2 n3 .WN 2 3 .WNn3/4k3
4

n3 0
N /4 1

X 1,1, k3

x n j.x

N n3 n3k3

n3 .WN .WN /4
4

x n j.x

N 3n3 n3k3

n3 .WN .WN /4
4

N /4 1

X 1,0, k3

n3 0

N /4 1

n3 0

Nh vy ta tch X(k) ra c thnh 4 dy con c di = N/4, mi dy con ny

chnh l bin i DFT di N/4 ca cc dy con c di N/4 c chia ra t x(n).
x1(n)

W(0n,N)

x(n)
W(2n,N)
x(n)+N/4
W(n,N)
x(n)+N/2
W(3n,N)
x(n)+3N/4
x2(n)

-j

FFT N/4
im

FFT N/4
im

X(4k)

X(4k+2)

FFT N/4
im

X(4k+1)

FFT N/4
im

X(4k+3)

Figure 1.4 Kin trc ca thut ton FFT c s 2^2

Trn hnh 1.3 l kin trc ca thut ton FFT vi c s 2^2. Thc cht ca thut
ton ny l ghp 2 tng c s 2 thnh 1 tng c s 2^2. Tuy nhin thut ton c s
2^2 c 1 u im so vi thut ton c s 2. Nu chng ta nhn vo hnh 1.2 th ta thy,
c sau mi mt tng c s 2 chng ta phi nhn thm h s twiddle factor, cn trong
c s 2^2 chng ta ch nhn twiddle factor sau tng th 2 cn tng trc ch nhn

14

Bo co thc tp k thut
vi h s -j h s tm thng, do khi thc hin bng my tnh s bt c s
lng php tnh ton phc v ci thin c phc tp.
Di y l 1 v d v s tnh FFT c s 2^2 cho dy u vo di 8 im:
X[0]

X[0]

X[1]

X[4]

X[2]

X[2]

X[3]

W(2,8)

X[4]

X[1]

X[5]

X[6]

X[7]

X[6]

W(1,8)

-j

X[5]

X[3]

-j

W(3,8)

X[7]

Figure 1.5 S tnh FFT c s 2^2 cho cho dy u vo di = 8.

1.2.3.3 Kin trc SDF
Trong cc v d trn hnh 1.3 v 1.4, kin trc m chng ta s dng l kin trc
song song, tc l chng ta tri ht tt c cc u vo (FFT bao nhiu im th dng
ngn y u vo) v thc hin tnh ton. u im ca kin trc ny l tc x
l cao, khng c delay, ch cn c N u vo l lp tc tnh ton ra c kt qu
u ra. Tuy nhin trong thc t, cc b FFT thng c s dng trong cc thit b
chy thi gian thc real time, u vo ca chng ta khng phi l 1 mng c sn N
phn t m ch l tng phn t 1, do kin trc song song nh th ny khng ph
hp.
khc phc nhc im ny, ngi ta s s dng 1 kin trc khc. Mt trong
nhng kin trc n gin, hay c s dng l kin trc SDF (single delay feedback).
Di y l 1 v d v FFT c s 2 dng kin trc SDF vi di N = 4.

15

Bo co thc tp k thut

Figure 1.6 FFT 8 im dng c s 2 SDF

Nh ta bit, trong FFT c s 2, ti tng u tin, s l tnh ton vi cc cp
x(n) v x(n+N/2). Nhn vo trong hnh 1.5 ti tng u tin ta thy bn trn khi tnh
ton Butterfly c 1 khi delay di = 4, mt cch tng qut, tng th k th di
delay s l

N
. S d phi c khi delay ny l v u vo ca chng ta khng phi
2k

l mt mng c sn N phn t m l ln lt tng s vo 1. Do u vo 1 s phi tnh

ton vi u vo th 1 + 8/2 = 5, do phi cn delay 4 nhp. Do u ra sau khi qua
khi Butterfly gm 2 u ra bao gm tng v hiu ca 2 phn t, do u ra cng
s c a ra khi khi lm u vo ca tng tip theo, cn u ra tr s li c
a vo khi delay. Sau 8 nhp (4 nhp lu cc u vo t 1 n 4, 4 nhp tnh ton
vi cc u vo t 5 n 8), cc u vo t 1 n 4 c tnh ton vi ht v cc
u ra tng c a ra, trong khi delay ch cn cc u ra hiu, lc ny, khi c
u vo mi, cc u vo ny s c a vo khi delay ch khng thc hin tnh
ton, ng thi khi delay s y cc u ra hiu lc trc ra. C nh vy chng ta
s c c kt qu ging nh trong hnh 1.3.

16

Bo co thc tp k thut
1.2.3.4 Trin khai FFT 128 im c s 2^2 theo kin trc SDF

Figure 1.7 FFT 128 im c s 2^2 kin trc SDF

17

Bo co thc tp k thut
Trn hnh 1.7 l s thut ton tnh FFT 128 im c s 2^2 theo kin trc SDF
c thc hin trn phn mm Simulink ca MatLab. Nh ta thy n c gm 7 Stage
v 1 khi Revorder. Ngoi ra cn c 1 b m 7 bit.
Chc nng cc khi:
-

Trong 7 Stage th Stage 1 l c s 2 cn li l c s 2^2, c 2 tng lin tip to

thnh 1 tng c s 2^2. Cc Stage c kt ni theo kin trc SDF v c chc
nng thc hin vic tnh ton FFT. V d hnh 1.8 bn di l kin trc ca
Stage 2. Ta thy n c 1 b cnh bm c s 2 theo kiu SDF, u vo data_i
s c a vo b ny thc hin tnh ton. Sau khi tnh ton cnh bm
c 1 b nhn dng nhn kt qu u ra vi cc gi tr twiddle factor hoc l
j.

Figure 1.8 Kin trc ca khi Stage 2

-

Khi m 7 bit c chc nng m t 0 n 127, khi ny c nhim v to ra

gi tr u vo Address (t 0 n 127) cho cc Stage thc hin iu khin
vic tnh FFT v khi Revorder thc hin vic sp xp.

Khi Revorder c chc nng sp xp li cc gi tr u ra. Nhn vo cc v d

trong hnh 1.3 v 1.4 chng ta thy th t ca cc gi tr u ra khng theo
ng trt t t nhin, do cn phi c 1 khi c nhim v sp xp li cc gi

18

Bo co thc tp k thut
tr ny trc khi cho ra u ra. hnh 1.9 bn di l kin trc ca khi
Revorder. N gm c 2 thanh RAM c chc nng lu tr gi tr u ra ca b
FFT sp xp li trc khi cho ra u ra. Ti 1 thi im, s ch c 1 thanh
RAM v ghi vo thanh RAM khc, khi SelectMem c chc nng la chn
vic c v ghi vo 2 thanh RAM ny. Ngoi ra cn c khi Bitrevorder c
chc nng o bit gi tr Address u vo to a ch ng cho vic c v
ghi vo RAM.

Figure 1.9 Kin trc ca khi Revorder

Sau khi xy dng kin trc xong, chng ta tin hnh m phng. u tin l m
phng ri so snh vi kt qu thu c khi s dng hm fft ca MatLab.

19

Bo co thc tp k thut

Figure 1.10 Sai s gia Simulink v hm fft ca MatLab

Nh ta thy trn hnh 1.10, gi tr sai s ch khong 10 13 , ngha l khi FFT ca
chng ta xy dng kh l chnh xc.
1.2.3.5 Chuyn i sang kiu d liu dy phy tnh (Fixed point)
Kiu d liu du phy tnh l 1 cch biu din s thc nhng s dng s nguyn
biu din trong s bit biu din phn nguyn v phn thp phn ca s thc
c la chn c nh. iu ny khc vi du phy ng khi m trong s thc du
phy ng, du phy thp phn c th thay i v tr bng cch thay i gi tr trng
m.

Figure 1.11 Biu din s thc du phy tnh 32 bit vi 16 bit thp phn dng nh
phn

20

Bo co thc tp k thut
Trn hnh 1.11 l cch biu din 1 s thc c du di dng du phy tnh 32 bit
vi 16 bit phn thp phn. Cch tnh gi tr ca s c biu din c tnh bnh
thng ging nh khi chuyn gi tr ca 1 s nh phn sang h 10.
Di y l bng so snh gia kiu d liu du phy ng chnh xc n vi
kiu d liu du phy tnh 32 bit, 16 bit thp phn.
Table 1.2 Bng so snh gia kiu d liu du phy ng chnh xc n vi kiu
d liu du phy tnh 32 bit, 16 bit thp phn.
Gi tr
Gi tr dng ln
nht
Gi tr dng nh

Du phy ng chnh

Du phy tnh 32 bit, 16

xc n

bit thp phn

2 2 .2
23

127

3.403 .1038

2.9527900159 4.5056 .10 4

2126 1.175 .1038

216 1.5259 .105

Gi tr m nh nht

3.4028 .1038

215 3.0518 .105

chnh xc

232 1.192 .10 7

216 1.5259 .105

nht

T bng 1.2 c th thy vi cng chiu di bit biu din, th di biu din cng nh
chnh xc ca du phy ng ln hn ca du phy tnh rt nhiu. Tuy nhin kiu
d liu du phy tnh c 1 u im l tc tnh ton cao, phn cng n gin hn
nhiu v c th trin khai trn FPGA mt cch d dng.
thc hin chuyn i m hnh ca chng ta t kiu d liu du phy ng sang
kiu d liu du phy tnh chng ta dng m phng Monte Carlo, bng cch s
dng 1 bin param_var lm di bit biu din v cho bin ny chy trong 1 khong
no . Vi mi gi tr ca param_var, chng ta thc hin m phng n_sims ln, so
snh kt qu ca mi ln vi gi tr tnh ton FFT theo floating point, tm sai s ln
nht ca n v lu li. Sau khi chy song, chng ta s so snh sai s vi 1 gi tr
epxilon t trc, gi tr ny chnh l gi tr sai s ti a cn chp nhn c, la
chn di bit biu din cho thch hp.
Code m phng v la chn c th xem ti phn ph lc.

21

Bo co thc tp k thut
1.2.3.6 Trin khai trn FPGA
Sau khi thc hin bin i m hnh FFT sang kiu d liu fixed point, chng ta s
dng cng c HDL Coder ca MatLab thc hin gen code Verilog. m cng
c ny, trn ca s ca Simulink chng ta chn Code/HDL Code/HDL Workflow
Advisor
y l giao din ca ca s HDL Workflow Advisor

Figure 1.12 Giao din ca ca s HDL Workflow Advisor

Ti ca s ny chng ta cn la chn cc thit lp thch hp cho vic gen code
HDL, nu mun thc hin FPGA in loop th ti mc 1. Set Target, phn 1.1 ti
Target Flow chng ta chn FPGA in loop, sau chn Target platform cng nh
cng c tng hp Synthesis Tool thch hp. Do c thc hin FPGA in loop nn
y chng ta chn Target platform l XUP Atlys Xilinx Spartan 6 development
board, cn Synthesis Tool l Xilinx ISE. mc 2 cho php chng ta kim tra cc
thng s khc ca m hnh xem c thch hp vi vic gen code HDL hay khng, cn
mc 3 cho php chng ta la chn cc thit lp nh ngn ng gen ra l VHDL hay
l Verilog, cc thng s ca Clock, Reset, Testbench. Lu l c 1 la chn y l
c thc hin Co simulation vi ModelSim hay khng, y chng ta chn c.

22

Bo co thc tp k thut
Sau khi thc hin tt c cc bc trn th phn mm s tin hnh gen code Verilog
cho chng ta.
Di y l kt qu sau khi gen m phng vi ModelSim.

Figure 1.13 Co - Simulation model vi ModelSim

Phn mm ModelSim y m em dng l ModelSim SE 10.1c cng vi phn
mm MatLab R2014a.
bn di l kt qu Co Simulation vi ModelSim. Vic m phng c thc
hin 10 ln, vi u vo l cc s nguyn 8 bit t -128 n 127 v c thc hin
theo m phng Monte Carlo.

23

Bo co thc tp k thut

Figure 1.14 Kt qu thc hin Co - Simulation vi ModelSim

T trn hnh 1.14 ta thy khi phn cng tng hp bng ngn ng Verilog cho kt
qu ging vi m hnh Simulink, vy l khi hot ng ng.

24

Bo co thc tp k thut
Cn di y l kt qu sau khi gen FPGA in loop vi HDL Workflow Advisor
ca MatLab.

Figure 1.15 Khi Co - Simulation FPGA - in loop

Sau khi thc hin gen FPGA in loop thnh cng, ta cn s dng phn mm
Xilinx ISE Design Suit np file sau khi tng hp code Verilog xung kit Atlys
thc hin kim tra.
Vic m phng Co Simulation FPGA in loop cng c thc hin bng m
phng Monte Carlo, thc hin m phng 300 ln vi u vo khi FFT vn l cc
s nguyn c du nm trong khong [-128 127]. Di y l kt qu m phng.

25

Bo co thc tp k thut

Figure 1.16 Kt qu m phng Co - Simulation FPGA - in loop

T trn hnh 1.16 ta thy khi FFT c trin khai trn kit Atlys chy ng kt
qu, nh vy ti c hon thnh.

26

Bo co thc tp k thut
1.3 Nhn xt, xut
1.3.1 u im
-

Kha thc tp gip sinh vin lm quen c vi mi trng lm vic trong

lnh vc k thut, tc phong cn c trong cng vic, gip sinh vin bt b ng khi ra
trng.
-

Pht trin cc k nng vit bo co k thut, ci thin c k nng c ting

anh chuyn ngnh.

-

Phng lab EDABK c cc thy c chuyn mn cao, nhit tnh v chu o vi

sinh vin, ng thi c cc bn, cc anh u l cc sinh vin xut sc ca khoa lun
nhit tnh gip v ch bo, to iu kin thun li cho em trong qu trnh thc tp.
C s vt cht ca EDABK cng rt y , thun tin cho qu trnh hc tp v
nghin cu cho cc sinh vin.
-

Trong qu trnh lm nhim v c giao, em c hc cc k nng lp trnh

MatLab, Simulink, c hc thm v ngn ng m t phn cng Verilog, tm hiu

v FPGA, Xilinx, ModelSim, FPGA in loop,
1.3.2 Nhc im
-

Qu trnh thc tp ch ko di 1 thng, khin sinh vin ch lm quen vi mi

trng.
-

Nhiu kin thc cha c dy trn trng, sinh vin phi t tm hiu hoc

o to li khin cho qu trnh thc tp cha lm vic c nhiu, m ch yu c

o to.
1.3.3 xut
-

Phng nghin cu nn to iu kin cc sinh vin c nhu cu lm vic v

nghin cu tip ti lab sau khi thc tp.

-

Vic lin h vi cc n v thc tp bn ngoi kh kh khn, v vy em mong

Vin v lnh o trng s c gng gip sinh vin nhiu hn na trong vic tm n
v thc tp.

27

Bo co thc tp k thut
-

t thc tp c thi gian kh ngn nn sinh vin cha lm c nhiu cng

vic, vin nn ko di thi gian thc tp sinh vin c th hc hi c nhiu hn.

2. Kt lun
Kt qu thu c sau t thc tp:
-

Tm hiu v c cu cng ty, cc v tr sau ny sinh vin ra trng c th ng

tuyn.
-

Nng cao cc k nng mm nh lm vic nhm, lp k hoch, phn chia thi

gian, giao tip.

-

nh hng c cc cng vic sau sau khi ra trng, nng cao kin thc c

s, chuyn ngnh in t.
-

Thy c nhng thiu st, hn ch v kin thc v k nng ca bn thn

c th b sung kp thi.
-

ng dng cc kin thc c hc trn lp v cc kin thc t tm hiu gii

quyt bi ton.
-

c hc thm nhiu kin thc b ch nh lp trnh MatLab, Simulink, ngn

ng Verilog,
-

Hiu c s b v qu trnh kim chng phn cng trong thit k vi mch.

28

Bo co thc tp k thut
3. Ph lc: M ngun mt s hm MatLab s dng trong qui trnh chuyn i m
hnh sang kiu d liu du phy tnh
3.1 Hm to m hnh sim_log
% Create log system by adding Toworkspace blocks after interested
blocks to log signal max, min values
% Input: system, dut: system and dut
%
file [system '_block_tags.mat'] contains variable block_tags
%
which are an array of struct whose elements are block name and
its
%
tag. Blocks with same tag are in the same group. Block without
tag
%
will not be logged.
% Output: file [system '_log'] is new model in which new ToWorkspace
blocks
%
are added
%
file [system '_block_attrs.mat'] contains variable
block_attrs
%
which are an array of struct whose elements are name, min,
max,
%
range, out_wl, prod_wl, coeff_wl, round. Those elements are
block
%
properties for designing fixed-point
function newsystem = create_log_system(system, dut, block_tags_file)
load_system(system);
newsystem = [system '_log'];
save_system(system, newsystem);
a = isempty(block_tags_file);
if (a)
%%Find out blocks in systems
blocks=find_system([newsystem '/' dut],'LookUnderMasks','all');
block_tags=struct('name',{},'tag',{});
for blk_i=1:length(blocks)
block_tags(blk_i).name=char(blocks(blk_i));
block_tags(blk_i).tag=get_param(blocks(blk_i),'tag');
end
disp('Create blog_tags file, edit the file to group blocks
(signals)');
save([newsystem '_block_tags.mat'], 'block_tags');
save_system(newsystem);
close_system(newsystem);
return;
end
load ('-mat', [block_tags_file '.mat']);
n_block_grps=0;
for blk_i=1:length(block_tags)
a = block_tags(blk_i).tag;
if (isnumeric(a))
block_name=block_tags(blk_i).name;
set_param(block_name,'tag',num2str(block_tags(blk_i).tag));
if (n_block_grps<block_tags(blk_i).tag)
n_block_grps=block_tags(blk_i).tag;end
end
end
block_attrs=struct('name',{},'OutMin',{},'OutMax',{},'range',{},...

29

Bo co thc tp k thut
'OutDataTypeStr',{},'ProductDataTypeStr',{},'CoefDataTypeStr',{},'RndMe
th',{},'AccumDataTypeStr',{},'ParamDataTypeStr',{});
%% Find the groups and add ToWorkspace block to log values
for grp_i=1:n_block_grps
block_names=find_system([newsystem '/'
dut],'LookUnderMasks','all','tag',num2str(grp_i));
block_attrs(grp_i).name=block_names;
block_id=get_param(char(block_names(1)),'Handle');
block_parent=get_param(block_id,'Parent');
block_ports=get_param(block_id,'PortHandles');
block_pos=get_param(block_id,'Position');
log=add_block('built-in/ToWorkspace',[char(block_parent) '/log'
num2str(grp_i)]);
set_param(log,'VariableName',['sig_log' num2str(grp_i)]);
set_param(log,'MaxDataPoints',['inf']);
set_param(log,'SampleTime','-1');
set_param(log,'Position',[block_pos(1)+50 block_pos(2)-20
block_pos(1)+90 block_pos(2)]);
log_ports=get_param(log,'PortHandles');
add_line(block_parent,block_ports.Outport,log_ports.Inport);
end
save([newsystem '_block_attrs.mat'],'block_attrs');
save([newsystem '_block_tags.mat'], 'block_tags');
save_system(newsystem);
close_system(newsystem);
end

3.2 Hm m phng sim_log

% This script is used to run Monte Carlo simulation for FFT 128 points
radix 2^2 SDF
% Simulink models
% Input:
%
+ mdl: model name
%
+ block_attrs_file: file stores block_attrs variable used to
log min,
%
max values of signals. In case block_attrs is not empty, model
%
should be generated by create_log_model function together with
the
%
block_attrs file
%
+ minimum, maximum: is the minimum and maximum value of input x
%
+ n_sims: number of simulations be executed
%
+ n_samples: number of samples in one simulation
%
+ Ts: sample time
% Output: result file stores the range of OutMin, OutMax of each group.
%% First load the parameter file
function sim_log(mdl, minimum, maximum, n_sims, Ts, n_samples,
block_attrs_file)
%
a = Ts*(n_samples - 1);

30

Bo co thc tp k thut
if (~isempty(block_attrs_file))
load('-mat',[block_attrs_file '.mat']);
n_block_grps=size(block_attrs);
n_block_grps=n_block_grps(2);
else
n_block_grps=0;
end
load_system(mdl);
save_system(mdl,[mdl '_sim_log']);
newmdl=[mdl '_sim_log'];
assignin('base','Ts',Ts);
assignin('base','n_samples',n_samples);
set_param(newmdl,'StopTime','Ts*(n_samples - 1)');
tic
for sim_i=1:n_sims
% log signal ranges
%% Input signal allocation
x = randi([minimum maximum], 128, 1);
assignin('base','x',x);
%%Simulation
sim(newmdl);
if (n_block_grps)
if (sim_i==1)
for grp_i=1:n_block_grps
block_attrs(grp_i).OutMin = min(eval(['sig_log'
num2str(grp_i)]));
block_attrs(grp_i).OutMax= max(eval(['sig_log'
num2str(grp_i)]));
end
else
for grp_i=1:n_block_grps
min_tmp = min(eval(['sig_log' num2str(grp_i)]));
block_attrs(grp_i).OutMin=min(block_attrs(grp_i).OutMin,min_tmp);
max_tmp = max(eval(['sig_log' num2str(grp_i)]));
block_attrs(grp_i).OutMax=max(block_attrs(grp_i).OutMax,max_tmp);
end
end
end
end
toc
%% save the result
%clear sig;
result_file=[mdl '_multisim_' num2str(n_sims)];
if (n_block_grps>0)
save(result_file,'block_attrs');
end
save_system(newmdl);
close_system(newmdl);

3.3 Hm to m hnh sim_fixed

% Create fixed point model by setting OutMin, OutMax, OutDataTypeStr

31

Bo co thc tp k thut
% RndMeth, CoefDataTypeStr, ProductDataTypeStr of model blocks
according
% the correspondent block_attrs.range, block_attrs.out_wl,
% block_attrs.coeff_wl, block_attrs.prod_wl, block_attrs.round
% Input: system, dut: system and dut
%
block_attrs_file contains variable block_tags
%
which are an array of struct whose elements are block name and
its
%
tag. Blocks with same tag are in the same group. Block without
tag
%
will not be logged.
% Output: file [system '_log'] is new model in which new ToWorkspace
blocks
%
are added
%
file [system '_block_attrs.mat'] contains variable
block_attrs
%
which are an array of struct whose elements are name, min,
max,
%
range, out_wl, prod_wl, coeff_wl, round. Those elements are
block
%
properties for designing fixed-point
function newsystem = create_fixed_system(system, block_attrs_file)
load_system(system);
newsystem=[system '_fixed'];
save_system(system,newsystem);
load('-mat',[block_attrs_file '.mat'],'block_attrs');
%% After above step, the user should edit the block_tags variable
manually to set block groups
% And then the tag will be set to the blocks
n_block_grps=size(block_attrs);
n_block_grps=n_block_grps(2);
%% Find the groups and add ToWorkspace block to log values
for grp_i=1:n_block_grps % for each block groups
block_names=block_attrs(grp_i).name; % all block names in the
group
n_blocks=size(block_names);
outmin=block_attrs(grp_i).OutMin;
outmax=block_attrs(grp_i).OutMax;
if (isempty(outmin) || isempty(outmax))
close_system(newsystem);
return;
end
outrange=block_attrs(grp_i).range;
if (isempty(outrange))
outrange = max(abs(outmin),abs(outmax));
block_attrs(grp_i).range=outrange;
end
round_mode=block_attrs(grp_i).RndMeth;
if (isempty(round_mode))
round_mode='round';
block_attrs(grp_i).RndMeth='round';
end
OutDataTypeStr=block_attrs(grp_i).OutDataTypeStr;
ProductDataTypeStr=block_attrs(grp_i).ProductDataTypeStr;
CoefDataTypeStr=block_attrs(grp_i).CoefDataTypeStr;
AccumDataTypeStr=block_attrs(grp_i).AccumDataTypeStr;
ParamDataTypeStr=block_attrs(grp_i).ParamDataTypeStr;

32

Bo co thc tp k thut

n_blocks=n_blocks(1);
for blk_i=1:n_blocks % for each block in group
block_name=block_names(blk_i); % block name (path)
block_name_vec=strsplit(char(block_name),'/');
% block path should be in the newsystem
% e.g. before 'cal55_log/calibration/acc1/acc_in'
% now it should be 'cal55_fix/calibration/acc1/acc_in'
block_name_vec{1}=newsystem;
block_name=strjoin(block_name_vec,'/');
block_id=get_param(char(block_name),'Handle');

set_param(block_id,'OutMin',['[-1.3*' num2str(outrange)
']']);
set_param(block_id,'OutMax',['[1.3*' num2str(outrange)
']']);
set_param(block_id,'RndMeth',round_mode);
if (~isempty(OutDataTypeStr))
set_param(block_id,'OutDataTypeStr',OutDataTypeStr);
end
if (~isempty(ProductDataTypeStr))
set_param(block_id,'ProductDataTypeStr',ProductDataTypeStr);
end
if (~isempty(CoefDataTypeStr))
set_param(block_id,'CoefDataTypeStr',CoefDataTypeStr);
end
if (~isempty(AccumDataTypeStr))
set_param(block_id,'AccumDataTypeStr',AccumDataTypeStr);
end
if (~isempty(ParamDataTypeStr))
set_param(block_id,'ParamDataTypeStr',ParamDataTypeStr);
end
set_param(block_id,'Tag',num2str(grp_i));
inout_id=get_param(block_id,'LineHandles');
out_id=inout_id.Outport;
set_param(out_id,'Name',[char(block_name_vec(length(block_name_vec)))
'_grp' num2str(grp_i)]);
%set_param(block_id,'OutputSignalNames',{[char(block_name_v
ec(length(block_name_vec))) '_grp' num2str(grp_i)]});
end
end
save([system '_block_attrs.mat'],'block_attrs');
save_system(newsystem);
close_system(newsystem);
% param=['cal55_log' ...
%
'.' num2str(n_freqs) ' fins-' num2str(fin(1)/fs) '-'
num2str(fin(n_freqs)/fs)];
% paramfile = [param '.mat'];
% resultfile=[param '.res.mat'];
% save(paramfile);

33

Bo co thc tp k thut
3.4 Hm to m phng sim_fixed
% This script is used to simulate fixed point model
% Input:
%
+ mdl: fixed point model name which is created by function
%
create_fixed_model
%
+ block_attrs_file: file stores block_attrs variable used to
log min,
%
max values of signals. In case block_attrs is not empty, model
%
should be generated by create_log_model function together with
the
%
block_attrs file
%
+ n_sims: number of simulations be executed
%
+ n_samples: number of samples in one simulation
%
+ Ts: sample time
% Behavior:
%
1) the parameter param_name in all blocks of group
block_attrs(grp)
%
will be set to a value in the array params
%
2) model is MC simulation and sfdr, sndr, snr performance are
%
collected
%
3) do that for all parameter values in array params
%
4) the performance vs. parameters curves are drawn
%
5) user can choose the appropriate wordlength
%
6) choosen appropriate wordlength is set to block_attrs(grp)
% Output: result file stores the wordlength of each group.

%% First load the parameter file

function sim_fix(mdl, n_sims, Ts, n_samples, block_attrs_file)
%
a = Ts*(n_samples - 1);
if (~isempty(block_attrs_file))
load('-mat',[block_attrs_file '.mat']);
n_block_grps=size(block_attrs);
n_block_grps=n_block_grps(2);
else
n_block_grps=0;
end
load_system(mdl);
newmdl = [mdl '_sim'];
save_system(mdl,newmdl);
open_system(newmdl);
assignin('base','Ts',Ts);
assignin('base','n_samples',n_samples);
set_param(newmdl,'StopTime','Ts*(n_samples - 1)');
range = zeros(n_block_grps, 23);
for i = 1:n_block_grps
range(i,:) = 10:32;
end
eps = 10^(-4); % acceptable maximum error
%% Simulation
tic
for n_grps = n_block_grps:-1:1
PARAM_VAR = range(n_grps,:);
sim_err_max = zeros(1,length(range(n_grps,:)));
block_names = block_attrs(n_grps).name;
n_blocks = size(block_names);
n_blocks = n_blocks(1);
for param_var = 1:length(range(n_grps,:))

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Bo co thc tp k thut
fx = 'fixdt(1,param_var)';
assignin ('base','param_var',PARAM_VAR(param_var));
for blk_i = 1:n_blocks
block_name = block_names(blk_i);
block_name_vec = strsplit(char(block_name),'/');
block_name_vec{1} = newmdl;
block_name = strjoin(block_name_vec,'/');
block_id = get_param(char(block_name),'Handle');
set_param(block_id,'OutDataTypeSTr',fx);
end
%MC simulation
for sim_i = 1:n_sims
x = randi([-128 127], 128, 1);
assignin('base','x',x);
sim(newmdl);
x_fft = fft(x);
result = reshape(simout(:,:,258:385),[128 1]);
err = result - x_fft;
err_max = max(err);
if (sim_i==1)
sim_err_max(param_var) = err_max;
else
sim_err_max(param_var) =
max(sim_err_max(param_var), err_max);
end
end
end
figure;
stem(10:32,abs(sim_err_max));
xlabel('WordLength');
ylabel('Error');
title(['SigLog' num2str(n_grps)]);
for i = 1:length(sim_err_max)
if (abs(sim_err_max(i))<eps)
wl = i+9;
break;
else
wl = 32;
end
end
% Set wordlength for each block in group
fx = ['fixdt(1,' num2str(wl) ')'];
block_attrs(n_grps).OutDataTypeStr = fx;
for blk_i = 1:n_blocks
block_name = block_names(blk_i);
block_name_vec = strsplit(char(block_name),'/');
block_name_vec{1} = newmdl;
block_name = strjoin(block_name_vec,'/');
block_id = get_param(char(block_name),'Handle');
set_param(block_id,'OutDataTypeSTr',fx);
end
end
toc
%%
save(newmdl, 'block_attrs');
save_system(newmdl);
close_system(newmdl);
end

35

Bo co thc tp k thut

Mc lc
Li ni u ..................................................................................................................1
1. Ni dung ..................................................................................................................2
1.1 Gii thiu chc nng, nhim v, c cu t chc ca n v tip nhn .............2
1.1.1 C cu t chc ca n v tip nhn ..........................................................2
1.1.2 Hng nghin cu ......................................................................................3
1.1.3 Hng o to ............................................................................................4
1.1.4 Hc bng ....................................................................................................5
1.1.5 Tuyn dng.................................................................................................5
1.2 Ni dung thc tp ..............................................................................................6
1.2.1 t vn ..................................................................................................6
1.2.2 M t ti.................................................................................................8
1.2.3 Bo co cng vic c giao .....................................................................9
1.2.3.1 Nhng kin thc c bn v FFT .........................................................9
1.2.3.2 FFT c s 2^2....................................................................................12
1.2.3.3 Kin trc SDF ...................................................................................15
1.2.3.4 Trin khai FFT 128 im c s 2^2 theo kin trc SDF ..................17
1.2.3.5 Chuyn i sang kiu d liu dy phy tnh (Fixed point) ...............20
1.2.3.6 Trin khai trn FPGA ........................................................................22
1.3 Nhn xt, xut.............................................................................................27
1.3.1 u im ....................................................................................................27
1.3.2 Nhc im ..............................................................................................27
1.3.3 xut .....................................................................................................27
2. Kt lun .................................................................................................................28

36

Bo co thc tp k thut
3. Ph lc: M ngun mt s hm MatLab s dng trong qui trnh chuyn i m
hnh sang kiu d liu du phy tnh ........................................................................29
3.1 Hm to m hnh sim_log ...............................................................................29
3.2 Hm m phng sim_log ..................................................................................30
3.3 Hm to m hnh sim_fixed ............................................................................31
3.4 Hm to m phng sim_fixed .........................................................................34
Mc lc ......................................................................................................................36
Danh mc hnh v .....................................................................................................38
Danh mc bng biu..................................................................................................39
Ti liu tham kho .....................................................................................................40

37

Bo co thc tp k thut

Danh mc hnh v
Figure 1.1 S gii thut ca thut ton FFT c s 2 ..............................................7
Figure 1.2 M hnh cnh bm ca FFT c s 2 ......................................................10
Figure 1.3 S thut ton FFT c s 2 cho 8 im ................................................11
Figure 1.4 Kin trc ca thut ton FFT c s 2^2...................................................14
Figure 1.5 S tnh FFT c s 2^2 cho cho dy u vo di = 8. ....................15
Figure 1.6 FFT 8 im dng c s 2 SDF.................................................................16
Figure 1.7 FFT 128 im c s 2^2 kin trc SDF...................................................17
Figure 1.8 Kin trc ca khi Stage 2 .......................................................................18
Figure 1.9 Kin trc ca khi Revorder ....................................................................19
Figure 1.10 Sai s gia Simulink v hm fft ca MatLab ........................................20
Figure 1.11 Biu din s thc du phy tnh 32 bit vi 16 bit thp phn dng nh
phn ...........................................................................................................................20
Figure 1.12 Giao din ca ca s HDL Workflow Advisor .....................................22
Figure 1.13 Co - Simulation model vi ModelSim...................................................23
Figure 1.14 Kt qu thc hin Co - Simulation vi ModelSim ................................24
Figure 1.15 Khi Co - Simulation FPGA - in loop ................................................25
Figure 1.16 Kt qu m phng Co - Simulation FPGA - in loop ..........................26

38

Bo co thc tp k thut

Danh mc bng biu

Table 1.1 Bng so snh s lng php tnh phc cn thc hin gia tnh DFT trc
tip v dng FFT c s 2. ..........................................................................................12
Table 1.2 Bng so snh gia kiu d liu du phy ng chnh xc n vi kiu
d liu du phy tnh 32 bit, 16 bit thp phn...........................................................21

39

Bo co thc tp k thut

Ti liu tham kho

[1] Nguyn Quc Trung, X l tn hiu v lc s Tp 2, Nh xut bn khoa hc v
k thut.
[2] Guoan Bi, Gang Li, Pipelined Structure Based on Radix 22 FFT Algorithm
in Industrial Electronics and Applications (ICIEA). 2011 6th IEEE Conference.
[3] Trio Adiono, Rella Mareta, Low Latency Parellel Pipelined Configurable
FFT/IFFT 128/256/512/1024/2048 for LTE in Intelligent and Advanced Systems
(ICIAS), 2012 4th International Conference.

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