Design For Testability

Assignment #2
Due Date: Sep 7th, 2016
1) Consider the combinational logic circuit below:

Fig-1
a)
b)
c)
d)

How many possible single stuck-at faults does this circuit have?
How many possible multiple stuck-at faults does this circuit have?
How many collapsed single stuck-at faults does this circuit have?
Generate all possible test vectors (truth table) and also the minimum set of test vectors to
completely test above circuit.

2) Show an example where a combinational logic circuit will become a sequential circuit in the
presence of a bridging fault.
3) Generate a minimum set of test vectors to detect all single stuck-at faults for a cascade of
(n1) exclusive-OR gates for an n-bit parity checker, where each exclusive-OR gate is
implemented by elementary logic gates (AND, OR, NAND, NOR, NOT). How many test
vectors are needed?
4) What logic function is implemented by the circuit shown below, if it includes,
a. Simultaneous faults x3 stuck-at-one and x2 stuck-at-zero
b. A bridging fault corresponding to logic AND between the inputs of gate G1.

Fig-2

5) Which of the following test vectors detect the fault X1 stuck-at-zero in the circuit shown
below?
a. 0111
b. 1111
c. 1101
d. 1011

Fig-3
6) Find test vectors in above circuit that can detect:
a. X3 stuck-at-zero
b. X2 stuck-at-zero
c.

X2 stuck-at-one