Samples of Exercise Solutions From Part I Chapters 1-18

Digital Electronics and Design with VHDL, Volnei A.
Pedroni, ElsevierMorgan Kaufmann, 2008
Digital Electronics and Design with VHDL

Volnei A. Pedroni
ElsevierMorgan Kaufmann, 2008
Samples of Exercise Solutions for Part I (Chapters 1-18)

Below are solutions for some of the 545 exercises contained in the book.
Chapter 2: Binary Representations
Exercise 2.33: Decimal to floating-point conversion #1
Find the single-precision floating-point representation for the following decimals:
a. 0.1875
b. 0.1875
c. 1
d. 4.75
Solution
a. 0.1875 = 3/16 = 1124 = 1.123 S=0, F=100, and E=01111100 (=124)
b. 0.1875 S=1, F=100, and E=01111100
c. 1 = 1.020 S=0, F=000, and E=01111111 (=127)
d. 4.75 = 19/4 = 1001122 = 1.001122 S=0, F=001100, and E=10000001 (=129)
Exercise 2.41: UTF-8 unicode encoding #2
Using UTF-8 encoding, determine the total number of bytes necessary to transmit the following sequence
of Unicode characters (given in hexadecimal format): U+0031, U+0020, U+1000, U+0020, U+020000.
Solution
U+0031 U+0020 U+1000 U+0020 U+020000 1 + 1 + 3 + 1 + 4 = 10 bytes
Chapter 3: Binary Arithmetic
Exercise 3.15: Shift versus unsigned division
Logically shift each of the unsigned numbers below two positions to the right and check whether the
number gets divided by 4. Are there any restrictions in this case?
a. "001100"
b. "000110"
c. "111101"
Solution
a. "001100" (=12) "000011" (=3; correct)
b. "000110" (=6) "000001" (=1; correct)
c. "111101" (=61) "001111" (=15; correct)
There are no restrictions other than that the result gets rounded down.
Exercise 3.27: Floating-point multiplication #2
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
Using single-precision floating-point representations and the procedure described in Section 3.9, determine
the products below. The result should be truncated (and rounded) to 3 fraction bits (if necessary).
a. 8.125 (8)
b. (19) (12.5)
Solution
a. 8.125 (8) = 1.00000123 (123) = 1.00000126. Truncating to 3 fraction bits, 1.00026 results.
Hence, S = '1', F = "000", and E = "10000101" (=133).
b. (19) (12.5) = (1.001124) (1.100123) = 1.1101101127. After truncation, 1.11127 results.
Hence, S = '0', F = "111", and E = "10000110" (=134).
Chapter 4: Introduction to Digital Circuits
Exercise 4.3: Static power consumption #3
a. Consider the CMOS inverter shown in Figure 4.5(a). Assuming that it does not exhibit any current
leakage when in steady state, what is its static power consumption?
b. Suppose that the circuit presents a leakage current from VDD to GND of 1 pA while in steady state and
biased with VDD = 3.3 V. Calculate the corresponding static power consumption.
Solution
a. Pstatic = VDD.ID = 0
b. Pstatic = VDD.ID = 3.3V 1pA = 3.3 pW
Exercise 4.13: OR-NOR timing analysis
Suppose that the OR-NOR circuit of Figure E4.13 is submitted to the stimuli also included in the figure
where every time slot is 10 ns wide. Adopting the simplifi ed timing diagram style of Figure 4.8(b), draw
the corresponding waveforms at nodes x and y for the following two cases:
a. Assuming that the propagation delays through the gates are negligible.
b. Assuming that the propagation delays through the OR and NOR gates are 2 ns and 1 ns, respectively.
a
a
b
y
b
c
c
x
y
Solution
See the figure below.
a
2ns
(a)
Chapter 5: Boolean Algebra

Exercise 5.3: Common-term theorem
2ns
1ns
(b)
1ns
1ns
Prove Equation 5.8(b) of the common-term theorem.

Solution
Applying the principle of duality (Equation 5.7) to y = (a + b1).(a + b2)(a + bN), the following results:
y = a.b1 + a.b1 + + a.bN
Factoring this expression:
y = a(b1 + b1 + + bN)
and reapplying the principle of duality:
y = a + b1.b2bN
Exercise 5.23: Function implementation #2
Draw a circuit capable of implementing the function y = a + b + c + d using:
a. Only OR gates.
b. Only NOR gates.
c. Only 2-input NOR gates.
d. Only NAND gates.
Solution
The circuits are shown below. The inverters are represented either explicitly (using their traditional symbol)
or by dark bubbles. In (b) and (c), the inverter can be constructed with a NOR gate with all inputs but one
connected to 0, while in (d) it can be constructed with all inputs except one connected to 1 (as in Figures
5.13(c)-(d)).
(a)
a
b
c
d
(b)
(c)
(d)
a
b
c
d
a
b
c
d
b
c
a
b
c
d
b
y
Chapter 6: Line Codes

Exercise 6.11: Bipolar codes #3
a. Given the bit sequence "11111111", draw the corresponding waveforms for the two bipolar codes (NRZ,
RZ) shown in Figure 6.5.
b. For each waveform, calculate the DC (average) voltage.
c. For each waveform, calculate the density of transitions.
d. Compare the results to those from the previous two exercises. Which bit sequences cause the minimum
and maximum number of transitions and the minimum and maximum DC levels?
Solution
a. The waveforms are shown in the figure below.
b. NRZ 0 (=0 always), RZ 0 (=0 always).
c. Considering that the data vector repeats itself indefinitely, the following amounts of transitions (signal
edges) occur: NRZ 100%, RZ 200%.
d. The DC level is 0V for any data sequence. The density of transitions is maximized (100%) for NRZ
when the data sequence is either "010101" or "111", while for RZ it is maximized (200%) only when
the data is "111".
clock
data
NRZ
Bipolar
RZ (AMI)
Exercise 6.23: 2D-PAM5 code

The questions below refer to a communications channel constructed with two twisted pairs of wires,
employing a 2D-PAM5 (also called PAM5 5) encoder-decoder pair at each end operating in fullduplex
mode (simultaneous communication in both directions).
a. How many information bits are conveyed by each encoder (channel) symbol?
b. If the information bits are fed to the encoder at the rate of 200 Mbps, with what symbol rate must the
encoder operate? In other words, after how many information bits must one 2D symbol be transmitted?
Solution
a. The general idea is depicted in the figure below. Since 2D-PAM5 operates with 5 voltage levels and two
pair of wires, up to 5x5=25 different values can be encoded by every channel symbol. Rounding to an
integer number of bits, it means that log225 = 4 information bits are conveyed by every channel symbol.
b. If the information rate is 200 Mbps, then every pair of wires must operate at 50 Mbaud. In other words,
for every 4 information bits the channel must transmit one 2D-PAM5 symbol.
c. See figure below.
50 MBaud
50 MBaud
50 MBaud
50 MBaud
1 symbol (4 bits)
Chapter 7: Error-Detecting/Correcting Codes

Exercise 7.15: Convolutional encoder #2
A circuit for a convolutional encoder with K = 7 was shown in Figure 7.10(b), and another with K = 3 was
shown in Figure 7.11(a). Draw another convolutional encoder, with K = 4 (k = 1, n = 2), given that its
coefficients are h1 = (h11, h12, h13, h14) = (1, 0, 1, 1) and h2 = (h21, h22, h23, h24) = (1, 1, 0, 1). Make
two sketches:
a. For K stages in the shift register.
b. For K1 stages in the shift register.
Solution
y1
(a)
x 1
x 2
x 3
x 4
y1
y
y2
(b)
x 1
x 2
x 3
y
y2
Exercise 7.19: LDPC code #2

Consider a code represented by the parity-check matrix in figure (a) below (this is obviously not an actual
low-density matrix, but it is simple enough to allow the decoding procedure to be performed by hand).
a. What are this codes n, m, k, wrow, and wcol parameters?

b. Draw the corresponding Tanner graph.
c. Show that this graph contains a 4-pass cycle.
d. Check whether the codewords "00111100" and "00111000" belong to this code.
1
TN
H=
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
BN
(a)
(b)
c1
c2
c3
c4
c5
c6
c6
c8
Solution
a. n=8, m=4 (so k=4), wrow=4, and wcol=2.
b. See figure (b) above.
c. See, for example, TN1 BN3 TN4 BN6 TN1 (TN = test-node, BN = bit-node) in the figure
above.
d. The expression HcT produces a zero only for the 1st codeword, so the 2nd codeword does not belong to
this code.
Chapter 8: Bipolar Transistor
Exercise 8.5: DC response #2
The questions below pertain to the circuit of Figure E8.4.
a. Plot VY as a function of VX.
b. Plot IB as a function of VX.
c. Plot IC as a function of VX.
d. Plot VZ as a function of VX.
e. For which values of VX is the transistor (i) cut off, (ii) in the active region, and (iii) saturated?
f. Draw the load line for this circuit and mark on it (i) the cutoff point, (ii) the point where the transistor
enters the saturation region, and (iii) the point where the transistor rests while saturated.
VCC
Figure E8.4.
I1
RC
IB
VY
VX
R1
R2
I2
IC
VZ
VCC=10V
VBB= 10V
=130
VJ=0.7V
VCEsat=0.2V
R1=50k
R2=150k
RC=1k
VBB
Solution
a. to d. See part (a) in the figure below.
e. Cut off for VX<4.27V, in the active region for 4.27VVX8.04V, and saturated for VX>8.04V.
f. See part (b) in the figure below.
150
114.7
VY
(V)
12.5
IB
(uA)
0.7
0
IC
(mA)
4.27
10
(ii)
9.8
9.3
0
0
(iii)
10
4.27
VX (V)
7.5
10
VX (V)
12.5
10
Active region
9.8
IC
(mA)
VZ
(V)
2.5
(i)
0
0.2
0
0
0
4.27
8.04
10
VX (V)
4.27
8.04
2
Vj =0.7V
VCE sat=0.2V
10
VX (V)
(a)
10
VCE (V)
(b)
Exercise 8.13: Transient response

Make a sketch for the transient response relative to the circuit of Figure E8.4. Assume that vX is a 0V/10V
pulse with frequency 100 MHz and that the transistor switching delays are td = tr = 1 ns and ts = tf = 2 ns.
Using vX as reference, present three plots: for vY (with no delays), for iC (with the delays above), and finally
one for vZ (derived from iC).
Solution
10V
vX
0V
iC
0mA
9.8mA
10V
td tr
vZ
ts
tf
0.2V
Chapter 9: MOS Transistor

Exercise 9.7: DC response #2
Redo example 9.1 for =1mA/V2 and RD=1.8k. The circuit was repeated in figure (a) below.
ID (mA) x VG (V)
VDD
VDD=5V
VT=1V
=1mA/V2
RD=1.8k
VG
RG
RD
+
VGS
ID
+
VDS
2.41
2.0
4
1.75
1.5
1.0
0.5
1
2.87
0
0
(a)
VDS (V) x VG (V)
2.5
(b)
Cutoff Saturation
1.85
Triode
(c)
0.66
2.87
0
1
Cutoff Saturation
Triode
Solution
a. According to equation (9.1), the transistor remains OFF while VGS<VT, that is, for VG<1V.
b. According to equation (9.2), the transistor remains in the saturation region while VDSVGSVT. Therefore,
using ID=(/2)(VGSVT)2, combined with VDS=VDDRSID plus the condition VDS=VGSVT, we obtain
VGS=2.87V. Hence the transistor operates in the saturation region while VG is in the range 1VVG2.87V.
For VG=2.87V, ID=1.75mA and VDS=1.85V.
c. According to equation (9.3), the transistor operates in the triode (or linear) region when VDS<VGSVT,
which occurs for any VG>2.87V. For VG=5V, we obtain ID=2.41mA and VDS=0.66V.
d. The plot of ID is shown in figure (b) above. From 0V to 1V the transistor is OFF, so ID=0. From 1V to
2.87V it is in the saturation region, so equation (9.2) was employed to sketch the current. Finally, above
2.87V it operates in triode mode, so equation (9.3) was used for ID.
e. The plot of VDS is shown in figure (c) above, determined by VDS=VDDRDID.
Exercise 9.15: CMOS inverter #2
Consider the CMOS inverter shown in figure E9.15. Say that Mn was designed with minimum size, that is,
(W/L)n=3/2, and that the pMOS transistor was designed with minimum length, Lp=2.
(a) Assuming that the mobility of electrons in the channel is about 3 times that of holes, what must the
width of the pMOS transistor (Wp) be for the two transistors to exhibit the same transconductance factors
(that is, n=p)?
(b) Intuitively, without inspecting equation (9.7), would you expect the transition voltage to change towards
0V or VDD when (W/L)n is increased with respect to (W/L)p? Explain.
(c) If n>p, assuming that VTn=VTp, do you expect the transition voltage to higher or lower than VDD/2?
Mp
vI
vO
Mn
Figure E9.15.
Solution
a. Since =Cox(W/L), (W/L)p=9/2 is required to obtain for n=p.
b. and c. Assuming that n=p and VTn=VTp, the same drain current (Equation 9.2) is produced by Mn and
Mp if VGSn= |VGSn|, that is, when VI =VDD/2, and the transistors are exactly on the transition point, in which
VOVI. If n is increased, with VI kept at VDD/2, then the drain current of Mn would grow, while that of Mp
would remain the same. This is obviously an impossible situation, because the transistors are connected in
series, so they can only operate with the same ID. The only operating point that satisfies this condition is
with Mn in triode mode (Equation 9.3), because then its VDS voltage will decrease enough to limit its drain
current, such that the drain current defined by Mp will prevail. In summary, to still remain in the transition
region, a lower gate voltage should be applied to Mn and a higher one (magnitude) should be provided for
Mp. Consequently, if Mn is stronger than Mp, it pulls VTR toward GND, while a stronger Mp would pull it
toward VDD.
Chapter 10: Logic Families and I/Os
Exercise 10.13: 2.5V LVCMOS I/O standard
(a) Draw a diagram similar to that in figure 10.7 for the 2.5V LVCMOS I/O standard. Assume that VDD is
exactly 2.5V and that IO=|1mA|.
(b) Calculate this familys noise margin when low and when high.
Solution
The corresponding parameters are given in Figure 10.23, that is, VOH=2.2V (notice that in the test condition
VDD is specified as minimum, that is, VDD=2.3V, with the resulting value of VOH 0.3V below VDD),
VOL=0.4V, VIH=1.7V, and VIL=0.7V. The construction of the diagram is now straightforward, and the
resulting noise margins are NMH=2.21.7V=0.5V and NML=0.70.4V=0.3V. These results are summarized
in the diagram below.
2.5V LVCMOS
A
Output
VDD=2.5V
1
VOH=2.2V
NMH
VOL=0.4V
NML
Input
2.5V LVCMOS
VOL (max)
0.4V
VOH (min)
2.2V
VIL (max)
0.7V
VIH (min)
1.7V
VIH=1.7V
Noise margin
VIL=0.7V
0
NML
0.5V
NMH
0.3V
GND
Exercise 10.21: XOR gate

Draw the MOS-based circuit for a 2-input XOR gates using:
a. CMOS logic.
b. Pseudo-nMOS logic.
c. Dynamic footed logic.
Solution
a. See Figure 4.15(a).
b. Just replace the upper part of Figure 4.15(a) with a permanently ON pMOS transistor, as shown on the
left of the figure below.
c. Just replace the upper part of Figure 4.15(a) with a clocked pMOS transistor, and insert also a clocked
nMOS transistor to connect the lower end of Figure 4.15(a) to the ground, as shown on the right of the
figure below.
clock
y
(weak)
y
a
b
clock
Chapter 11: Combinational Logic Circuits

Exercise 11.17: Address-decoder timing analysis
Redo the plots of example 11.3 (circuit was repeated in figure (a) below), for the circuit operating in high
frequency and with the following gate delays: tp_inv=2ns, tp_AND=3ns.
Solution
Shown in figure (b) below, where the time slots are 1ns wide.
x1
y3
x0
y2
x1
y1
x0
y0
y3
y2
x1
x0
y1
(a)
(b)
y0
Exercise 11.23: Multiplexer with more inputs

Using only 4 1 multiplexers, construct the 8 1 multiplexer shown in Figure E11.23 (repeated in figure
(a) below).
Solution
See figure (b) below.
x0
x1
x2
x0
x1
x2
x3
0
1
2
3
x3
x4
x5
x6
x7
x7
0
1
sel(2:0)
(a)
(b)
2
0
1
2
3
sel0 sel1 sel2
Chapter 12: Combinational Arithmetic Circuits

Exercise 12.3. Carry-ripple adder #2
Figure E12.3 shows a 4-bit carry-ripple adder with a = "0101", b = "1101", and cin = '1' applied to its
inputs. Based on the FAs truth table (Figure 12.1), write down the values produced for the sum and
carry bits. Check whether the result matches the expected value (that is, 5 + 13 + 1 = 19).
Solution
As shown in the figure below, the outputs are s0 = '1', s1 = '1', s2 = '0', s3 = '0', and c4 = '1', thus forming the
vector c4s3s2s1s0 = "10011" (=19).
1
FA
FA
FA
Figure E12.3.
Exercise 12.13: Incrementer
FA
a. Write the Boolean expressions (in SOP format) for the incrementer seen in Figure 12.14(b) (repeated in
the figure below).
b. Suppose that a = "10110" (= 22). Apply it to the circuit and check whether it produces the expected
result (that is, b = 23).
c. Repeat part (b) above for a = "11111" (= 31). What is the expected result in this case?
a1
a0
b1
b0
a2
b2
a3
b3
a4
b4
Solution
a. The circuits equations are listed below.
b0 = a0
b1 = a1 a0 = a1.a0 + a1.a0
b2 = a2 (a1.a0) = a2.a1.a0 + a2.a1 + a2.a0
b3 = a3 (a2.a1.a0) = a3.a2.a1.a0 + a3.a2 + a3.a1 + a3.a0
b4 = a4 (a3.a2.a1.a0) = a4.a3.a2.a1.a0 + a4.a3 + a4.a2 + a4.a1 + a4.a0
b. The expected result indeed occurs (you can confirm this by using either the circuit or the expressions
above).
c. Due to overflow, "00000" (= 0) is expected and indeed occurs.
Chapter 13: Registers
Exercise 13.9: DFF timing analysis
Figure (a) below shows a positive-edge D-type flip-flop (DFF) that receives the signals clk, rst, and d
displayed in figure (b). Assuming that the DFFs propagation delay from clk to q is tpCQ=5ns and from rst to
q is also tpRQ=5ns, draw the resulting waveform for q. Consider that the clock period is 50ns and that the
DFFs initial state is q=0.
Solution
See q figure (b) below. As usual, gray shades are employed to highlight the propagation delays.
clk
d
clk
(a)
rst
rst
rst
(b)
Exercise 13.14: Dual-edge DFF with multiplexers

The dual-edge D-type flip-flop (DE-DFF) of Figure 13.20(a) was implemented with two D-type latches
(DLs) plus a multiplexer. How can it be constructed using only multiplexers? Draw the corresponding
circuit. What is the minimum number of multiplexers needed?
Solution
As seen in Section 13.3 (Figure 13.8(a)), a DL can be constructed with a single multiplexer, so three muxes
suffice to construct a DE-DFF. The resulting circuit is shown below, where the clock acts as the inputselect signal.
1
0
clk
q
1
clk
0
clk
Chapter 14: Sequential Circuits

Exercise 14.21: Programmable 4-bit counter #1
Design a programmable 0-to-M counter, where 0M15. The value of M should be set by a programmable
4-bit input, illustrated with 1100 (=12) in the figure below. The counter must be synchronous and with
serial enable.
1
1
0
0
q3
q2
q1
q0
Programmable
counter
clk
Solution
One solution is shown in the figure below, which contains an equality comparator (see Figure 12.15(a)) at
the input. When the counter output coincides with the (programmable) value chosen for M, clear=0 is
generated, causing the counter to be synchronously zeroed at the next clock edge. The counter can be that
of Figure 14.11(b).
clk
Counter
q3
1
clr
q2
Programmable
input (M)
1
q1
clear
0
q0
0
Exercise 14.49: Dual-modulus prescaler #1

Prescalers were studied in Section
Figure (a) below shows a basic divide-by-M/(M + 1) prescaler.
a. Determine the value of M for MC = '0' and for MC = '1'.
b. Draw a timing diagram (similar to that in Figure 14.27(b)) for MC = '0'.
c. Repeat part (b) for MC = '1'.
Solution
a. M=2 for MC = '0' and M=3 for MC = '1'.
b. See figure (b) below.
c. See figure (c) below.
q3
q2
q1
q0
Counter
output
clk/M
For MC=1
MC
x
d0
q0
d1
q1
q0
q1
For MC=0
clk
q0
clk
q0
q1
q1
clk
(a)
T=3T0
T=2T0
(b)
(c)
Chapter 15: Finite State Machines

Exercise 15.3: Synchronous 3-to-9 counter with three flip-flops
a. Using the FSM approach, design a 3-to-9 counter with the minimum number of fl ip-fl ops (that is, 3,
because this machine has 7 states). Remember, however, that the actual output (y) must be 4 bits wide to
represent all decimal numbers from 3 to 9. To reduce the amount of combinational logic in the conversion
from 3 to 4 bits, try to find a suitable (3-bit) representation for the FSM states.
b. Compare the resulting circuit with that designed in Example 14.6 (Figure 14.13). Note, however, that
sequential 0-to-6 encoding was employed there, while a different encoding is likely to be chosen here.
Solution
a. The formal 5-step design procedure described in Section 15.2 is again adopted here.
Steps 1: The state transition diagram is shown in figure (a) below.
four
five
six
(0100)
(0101)
(0110)
y3
three
(0011)
nine
eight
seven
(1001)
(1000)
(0111)
(a)
Truth table for nx_state
Truth table for y
pr_state
q2 q1 q0
nx_state
d2 d1 d0
pr_state
q2 q1 q0
output
y3 y2 y1 y0
011
100
101
110
111
000
001
100
101
110
111
000
001
011
011
100
101
110
111
000
001
0011
0100
0101
0110
0111
1000
1001
(b)
y2
q2
d2
q2
y1
q1
d1
q1
y0
(c)
q0
q0
d0
clk
Step 2: The corresponding truth tables, extracted from the state transition diagram, are shown in figure (b).
Note that 3 bits (so 3 DFFs) are needed to encode the 7 machine states. Any encoding can be chosen, so to
avoid a large amount of combinational logic to convert the 3-bit machine output into the actual 4-bit circuit
output the last 3 output bits were employed (see the truth table for y) to represent the machine states.
Consequently, the values for y can be easily determined as y0=q0, y1=q1, and y2=q2, with y3 as the only
output that indeed requires some additional computation.
Step 3: From the truth table, with the help of Karnaugh maps, the following irreducible SOP expressions
result for nx_state (d2 , d1 , d0) and y:

d2 = q2.q1 + q2.q0 + q2.q1
d1 = q1.q0 + q1.q0
d0 = q0 + q2.q1
y3 = q2.q1
Recall that y2=q2, y1=q1, and y0=q0
Step 4: The circuit is shown in figure (c).
Step 5: If a glitch-free output is required, then Step 5 must be considered. In this particular exercise, y0, y1,
and y2 are glitch-free because they come directly from flip-flops. However, that is not so for y3.
The reader is invited to discuss the following: (i) When/why can a glitch occur in y3? (ii) If a flip-flop is
used to clean y3, how will that decision affect the other bits of y (think of the time domain).
b. It is left to the reader to compare the results (expressions) above with those obtained in Example 14.6.
Respond: Did the use of an encoding different from the regular (sequential, 0 to 6) binary encoding help
reduce the circuit size?
Exercise 15.19: Switch debouncer
When we press or change the position of a mechanical switch (like that in the figure below), bounces are
expected to occur before the switch finally settles in the desired position. For that reason, any mechanical
switch must be debounced in an actual design. This can be done by simply counting a minimum number of
clock cycles to guarantee that the switch has been in the same state for at least a certain amount of time (for
example, 5 milliseconds). In this exercise, the following debouncing criteria should be adopted:
Switch closed (y = '0'): x must stay low for at least 5 ms without (any visible) interruption.
Switch open (y = '1'): x must stay high for at least 5 ms without (any visible) interruption.
a. Assuming that a clock with frequency 1 kHz is available, design an FSM capable of debouncing the
switch shown in the figure. However, before starting, estimate the number of DFFs that will be needed.
b. How many DFFs would be needed if the clock frequency were 1 MHz?
VDD=3.3V
Debouncer
clk
Solution
a. The formal 5-step design procedure described in Section 15.2 can again be employed. The results are
summarized in the next figure. First, the circuits state transition diagram is presented; since this machine
has 4 states, a minimum of 2 DFFs are necessary. Next, the corresponding truth tables for nx_state and y are
shown, in which sequential binary encoding (Chapter 2) was employed. From the truth tables, with the help
of Karnaugh maps, the following equations result for nx_state (that is, d1 and d0) and y:
d1 = q1.q0 + q1.t + q0.x.t
d0 = q1.q0.x + q1. q0 .x + q1.x .t + q1.x.t
y = q1
were t (=time) represents the status of the counter, that is, t is 1 when time=max or 0 otherwise (note that
the counter, by counting from 0 to max, has max+1 states, so the clock frequency gets divided by max+1).
time max
x=0
up
(y=0)
x=1
x=0
x=1
x=1 AND
time=max
one
(y=1)
zero
(y=0)
x=0 AND
time=max
x=0
x=1
down
(y=1)
time max
Truth table for nx_state
pr_state
time
nx_state
zero
0
1
0
1
1
0
1
0
0
1
------ max
= max
---- max
= max
---
zero
up
zero
up
one
down
one
down
zero
one
up
one
down
Truth table for y
pr_state
q1 q0
time
(zero) 0 0
0
1
0
1
1
0
1
0
0
1
X
X
X
0
1
X
X
0
1
X
(up)
0 1
(one)
1 0
(down) 1 1
pr_state
q1 q0
(zero) 0 0
(up) 0 1
0
0
(one)
1 0
(down) 1 1
pr_state
zero
y
0
up
one
down
nx_state
d1 d0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
A circuit that implements this FSM is depicted below, where, as usual, the lower section contains only
sequential logic (DFFs), while the upper section contains only the combinational part. The former stores
pr_state, while the latter is responsible for generating nx_state and the actual output, y.
The generation of t (=time) is also depicted in the figure. It consists of a counter that is synchronously
cleared at the next upward clock edge (recall that in our context reset is asynchronous, while clear is
synchronous) when its output value is max, thus resulting for t a waveform that stays low during max clock
pulses and high during one clock period. The counter can be any of those seen in Sections 14.2 and 14.3,
while the comparator can be that seen in Figure 12.15(a) of Section 12.7.
Finally, observe that this FSM resembles the general architecture described in Section 15.4 (see Figure
15.21(c)), which is proper of large state machines. However, for the case of 1kHz clock, it can be modeled
as a small state machine, as described in Section 15.2. Regarding the latter, please see the discussion
proposed at the end of this exercise.
y
clk
counter
comparator
clear
max
pr_state
q1
t
nx_state
d1
q1
q0
q0
d0
clk
b. Estimate for the number of DFFs:

For the counter: If the clock frequency is F, to obtain a delay D the total count must span F.D clock
cycles. A zero-to-(F.D1) counter can be used, so F.D1=max, which is the counters final state. The
minimum number of DFFs then is log2(F.D) or, equivalently, log2(max+1). Consequently, to achieve
D=5ms, log25=3 DFFs are needed when F=1kHz or log25,000=23 when F=1MHz.
For the FSM: As seen above, the machine has 4 states, hence for the chosen encoding scheme (sequential
binary) the number of DFFs is log24=2.
Total minimum number of DFFs: 3+2=5 for F=1kHz or 13+2=15 F=1MHz.
Note: In Chapter 23 (Exercise 23.3) you will be asked to solve this problem using VHDL. Check then if
your predictions for the number of flip-flops were correct.
Discussion: In the case of F=1kHz, only 5 clock cycles are needed to debounce the switch, which is not a
good implementation, because the circuits resolution is too poor (that is, events can easily go unnoticed).
Even so, that case was included in this exercise to allow the following state-machine analysis: With such a
small number of states, a separate circuit for generating t can be avoided, because it is now viable to draw a
state transition diagram with all situations explicitly included. Draw it and then solve the problem without
involving t in your solution. Why is that alternative not viable for F=1MHz?

Samples of Exercise Solutions From Part I Chapters 1-18

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Digital Electronics and Design with VHDL, Volnei A.

Pedroni, ElsevierMorgan Kaufmann, 2008

Digital Electronics and Design with VHDL

Samples of Exercise Solutions for Part I (Chapters 1-18)

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