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American International University- Bangladesh

Faculty of Engineering (EEE)


VLSI CIRCUIT DESIGN Laboratory
EEE-4217

Experiment# 1: Introduction to Circuit Simulation Using SpiceCMOS Inverter


INTRODUCTION:
SPICE (Simulation Program with Integrated Circuit Emphasis) is a very powerful and
one of the most widely used simulator for electrical and electronic circuits at transistorlevel (circuit-level in VLSI terms), especially for analogue and mixed-signal circuits.
This experiment aims at introducing students to some of modeling and simulation
capabilities of SPICE as applied to CMOS VLSI circuit design.
SPICE can perform nonlinear dc, nonlinear transient, linear ac analysis and other type of
simulations. The circuit may contain resistances, capacitors, inductors, mutual inductors,
independent voltage and current sources, four types of dependent sources, transmission
lines, and four most common semiconductor devices: diodes, BJTs, JFETs and
MOSFETs. This experiment will use SPICEs dc and transient analysis capabilities to
analyze circuits based on CMOS n-type and p-type enhancement mode MOSFETs and
illustrate the importance of such a simulator in VLSI Design.
HISTORY OF SPICE:
CANCER:
In early 1970s, Ron Rohrer intended to develop a simulation program at the University of
California Berkley. Rohrer's students, including Larry Nagel, created the CANCER
simulatorComputer Analysis of Non-Linear Circuits Excluding Radiation. It performed
DC, AC and Transient Analysis; components include diodes (Shockley equations) and
bipolar transistors (Ebers-Moll equations). Other simulation programs of the day included
IBM's ECAP and Autonetics TRAC.
SPICE1:
In 1972, Nagel and Pederson released PICE1 (Simulation Program with IC Emphasis)
into the public domain. SPICE becomes industry standard simulation tool. In addition to
Bipolar transistorsBJTs, JFET and MOSFET devices were added. The program (and
simulation) was based on Nodal Analysis. It was written in FORTRAN code running on
large main frame computers. The cover page of the original SPICE paper written in 1972
is shown on page2, available now at University of California at Berkeley at the web
address:
http://www.eecs.berkeley.edu/Pubs/TechRpts/1973/22871.html
Shahriyar M. Rizvi, 2011, 2013, 2014

1/23

SPICE2:
In Nagel's 1975 release offers significant improvements. It included Modified Nodal
Analysis (MNA), replacing the old analysis, now supports voltage sources and inductors.
Memory was dynamically allocated to accommodate growing circuit size and
complexity. It has adjustable time-step control speeds simulation. MOSFET and bipolar
models were overhauled and extended. Version SPICE2G.6 (1983) is the last FORTRAN
version (still available today from Berkeley). Many commercial simulators today are
based on SPICE2G.6.
SPICE3:
In 1985, SPICE code was rewritten in the C programming language. It now featured a
graphical interface for viewing results. It includes polynomial capacitors, inductors and
voltage controlled sources. This new version eliminated many convergence problems.
New added models included MESFET, lossy transmission line and non-ideal switch.
Improved semiconductor models accommodated smaller transistor geometries. It was not
backward compatible with SPICE2.
1980's AND BEYOND
In the 1980s commercial versions of SICE that were released included HSPICE,
IS_SPICE and MICROCAP. MicroSim releases PSPICE, the first PC version of SPICE.
MicroSim was later bought by Cadence Design Systems (http://www.cadence.com).
SPICE started to attract many more users in industry and academia than before.

Companies started to integrate SPICE versions to their schematic entry and layout
packages.

SPICE Availability:
The free student version of SPICEORCAD PSPICE Studentfrom Cadence Design
Systems used to be available at their website. They do not seem to offer it at this point.
However, they do offer an evaluation version that includes PSPICE, which is called
Cadence ORCAD Demo Software that includes only Schematic and PSPICE, at
http://www.cadence.com/products/orcad/pages/downloads.aspx#pspice. One needs to
create an account there to download this evaluation software. The PSPICE Student
(version 9.1) software, however, is still legally available at many academic sites such as
at
University
of
Kentuckys
College
of
Engineering
http://www.engr.uky.edu/~cathey/pspice061301.html.
THEORY AND METHODOLOGY:
The CMOS inverter:
Consider the circuit of the CMOS inverter below. When the input is high the pull-down
device (Mpd) is ON but Vgs of the p-channel device is zero and hence the pull-up device
(Mpu) is OFF such that the output pulls all the way to ground. When the input is low,
Vgs of the p-channel device is Vdd and hence it is ON. The pull-down device is OFF and
the output rises to Vdd.
Schematic of CMOS Inverter:
1. Logic-Level (Logic-Level refers to Gate-Level):
Vout = Vin

Vin

Vout

Inverter Truth-Table for Logic-Level


Inverter Input
Vin
0

Inverter Output
Vout
1

Vout = Vin

Vin

2. Switch-Level (Switch-level refers to simplified Transistor-level):

PMOS

NMOS

VSS
(GROUND)

3. Circuit-Level
VDD

(Circuit-Level refers to Transistor-level):

PMOS

Pull-up Transistor (Mpu)


Vout

GATE

Mpu

Vin

Pull-down Transistor (Mpd)

CL (LOAD CAPACITOR)
1
Mpd
OUTPUT LOAD
GATE

NMOS
VSS
(GROUND)

Inverter Truth-Table for Switch/Circuit-Level:


Inverter Logic- State State Output Output Inverter Logic- State
of
Input
Level of
of
of
of
Output Level Output
Vin
of Vin Mpu Mpu Mpu
Mpd
Vout
of
Voltage
Vout
Transition
(after
Input
Voltage
Transition)
Vss < 0
ON
OFF Vdd
Z
Vdd
1
Low-toVin <=
(open
High
Vdd/2
circuit)
Transition
Vdd/2 < 1
Vin <=
Vdd

OFF

ON

Z
(open
circuit)

Vss

Vss

High-toLow
Transition

State of State
of
Inverter Inverter
from
Loads
viewpoint

Output
pulled
up (to
Vdd)
Output
pulled
down
(Vss)

Output
capacitor
fully
charged
Output
capacitor
fully
discharged

Note: Here, it has been assumed that Gate Threshold of Inverter VI = VDD/2 volts, with
NMOS and PMOS having equal MOS threshold voltage (V T) and equal transistor gain
factor ().
Sizing Transistors of CMOS Inverters for Performance

VDD
SOURCE

It is generally desirable to have identical pull-up and pull-down behavior in many VLSI
circuits, in other words, identical pull-up and pull-down delay. The delay in a CMOS
inverter are functions of inverter current and output capacitance (capacitance of the load
capacitor (CL)), which are both functions of the load voltage (voltage at the load
capacitor). For simplicity, delay of CMOS inverter is considered to be only the function
of the inverter current. In pull-up, current flows through the PMOS and in pull-down,
current flows through the NMOS. The Analytical delay model of a symmetrical CMOS
inverter (an inverter with identical pull-up and pull-down delay and identical MOS
threshold voltages) tells us that

BODY/SUBSTRATE

Inverter Delay tPD = K. CL/ . VDD, where K is a constant.


DRAIN

The pull-down delay =Vout


tPDN = K. CL/ N . VDD
The pull-down delay = tPDP = K. CL/ P . VDD
3

DRAIN

So, pull-down delay is a function of NMOS gain factor N and pull-up delay is a function
of PMOS gain factor P.

BODY/SUBSTRATE
The

MOS drain current equation is the following:

IDS = (VGS VT VDS/2) VDS


SOURCE

CL

IDS is Drain Current, is transistor gain factor, VGS is Gate Voltage, VT is MOS
Threshold Voltage and VDS is Drain Voltage.
For NMOS, drain current IDSN = N (VGSN VTN VDSN/2) VDSN
For PMOS, drain current IDSP = - P (VGSP |VTP| VDSP/2) VDSP
PMOS drain current can be written as ISDP = P (VSGP |VTP| VSDP/2) VSDP
Lets revisit MOS drain current IDS = (VGS VT VDS/2) VDS
Now, Gain Factor = COX W/L
Here,
= Mobility of charge carrier (for NMOS the charge carriers are free electrons and for
PMOS they are free holes)
COX = Gate Oxide thickness
W = Width of the channel (conductive layer), which is generally equal to the Width of
the Gate
L = Length of the channel (conductive layer), which is generally equal to the Length of
the Gate

. COX is termed as K (not the K of inverter delay equation) and is called process transconductance or intrinsic trans-conductance. W/L ratio is called aspect ratio or shape
ratio. As can be easily seen from the expression K is process (fabrication)-dependent and
W/L is geometry-dependent. One of the main tasks of VLSI engineers is to select W/L
ratio for all the transistors in his designs. He cannot change K as it is fixed for a CMOS
process; determined by features of the CMOS process selected by the fabrication plant.
Now, the mobility of the electrons is 2 to 3 times higher than mobility of electrons; this is
a fact of nature. That means an inverter with an NMOS and PMOS of equal size, that is
of same W and L (the process parameters such as COX are same for all transistor in
fabrication) will result in higher NMOS drain current and lower PMOS drain current and
consequently would result in lower pull-down delay or fall-delay and higher pull-up
delay or rise delay. To design a symmetrical inverter with identical rise time and fall time
(identical pull-up and pull-down delay), one must increase the W/L ratio of the PMOS so
that delays are identical. Since N is 2 to 3 times larger than P, WP/LP has to be 2 to 3
times larger than WN/LN.
IDSN = N COX WN/LN (VGSN VTN VDSN/2) VDSN
ISDP = P COX WP/LP (VSGP |VTP| VSDP/2) VSDP

We will design our CMOS inverter with a PMOS gate width 3 times larger than NMOS
gate width to ensure a symmetrical inverter. So, WP = 3 . WN. Generally, in a CMOS
process (fabrication), L represents minimum manufacturable length and is kept constant.
In other words, lengths of most transistors in a design remain at minimum
manufacturable length and constant. One can easily change the W/L ratio by changing
just the W. We will use the following aspect ratios for our CMOS inverter:
WN/LN = 4/3
WP/LP = 13/3

Circuit-Level (Transistor-level) Diagram for CMOS Inverter with Transistor Sizes for
Symmetrical Fall-Time and Rise-Time:
VDD

PMOS
GATE

Mpu

Vin
1

Mpd

GATE

NMOS

VSS
(GROUND)

SPICE Simulation of Circuits:


To simulate the performance of the circuit, the various nodes are identified (e.g., 1,2,3)
and each device is given a unique name (e.g. Mpu, Cload, Mpd). The circuit can now be
simulated in SPICE by a set of program statement stored in a data file. A typical input file
consists of a title line, a set of element statements that describe the circuit, and a set of
control statements that instruct SPICE during program execution. The entire input file
must be terminated by an .END control statement. Input line in which the first character
is an asterisk (*) are interpreted as comment line. Detailed rules for circuit description
and control statements are described below.
Rules for circuit description

SOURCE

1. Node identifiers or numbers must be non-negative integers.


2. The ground node (0 Volts) must be numbered zero.
3. Device names can be up to 8 characters in length.
4. The first letter of a device name identifies the device type, e.g. R for resistance, C for
capacitor, M for MOSFET, V for independent voltage source and I for independent
current source.
5. Values can be expressed as integers or floating point numbers, the following
abbreviations may be employed:
t: 1e12
k: 1e3
n: 1e-9
g: 1e9
m: 1e-3
p: 1e-12
meg: 1e6
u: 1e-6
f: 1e-15
6. Comments can be inserted into the circuit description by beginning the statement with an
as = 13/3
W/L
the first character.

BODY/SUBSTRATE *
DRAIN

Vout
Writing your circuit description:
Use the following as a template to write a description:
3
(title)
DRAIN
Spice options:
To limit width of output to 80 characters- useful for ttys.
.width out = 80
BODY/SUBSTRATE W/L = 4/3
50and
pF printout of model parameters.
To suppress page ejects
.options nopage nomode
Circuit description (See Circuit Element Description):
CL
.
SOURCE
.
0
Model specification (see Circuit Element Description):
.
.
Input signals (see Signal Source Description):
.

Simulation modes:
.
.
Generating outputs
.
.
End of simulation:
.end

Circuit Element Description:


Resistor and Capacitors:
General Form: Devicename n1 n2 Value
where Devicename is rxxxxxxx for a resistance, cxxxxxx for a capacitor.
n1, n2 are the node numbers of the device terminals.
Value is the resistance in ohms or capacitance in Farads.
MOSFETs:
General Form: Devicename n1 n2 n3 n4 model name l w
where Devicename is mxxxxxx
The nodes in order are drain, gate, source and substrate
l and w are channel length and width (in meters) respectively.
e.g.
mpu 2 1 3 2 penh l=3u w=10u
mpd 3 1 0 0 nenh l=3u w=4u
Note that the substrate of the p-type enhancement device is connected to the positive
supply whereas that of the n-type enhancement device is connected to the ground node.
Model name:
The simulator needs detailed information on the technology being simulated. The
MOSFET model in SPICE 2G5 permits 37 different parameters to be set in order to
describe the target technology. These parameters are included in a model statement and
the model name refers to the required model. The models of the CMOS p and n type
enhancement mode transistors provided here following this introduction are values
derived by the fabricators for this particular CMOS technology and should be included in
the circuit description file.

APPARATUS:
1. A Windows-based (XP or 7) PC with standard word processors (i.e. Microsoft
Office) and PDF readers (i.e. Adobe Acrobat Reader/Writer, Foxit
Reader/Phantom) installed.
2. A PSPICE simulator, preferably ORCAD PSpice Student 9.1 Student from
Cadence
PRECAUTIONS:
1. A PC with a standard Anti-Virus program installed should be used.
EXPERIMENTAL PROCEDURE:

1.

The SPICE circuit description for a symmetric CMOS inverter is given below. Draw the
circuit carefully labeling all the nodes and naming the components. Simulate it in PSpice
9.1 Student A/D circuit simulator for the following design requirements.
DESIGN REQUIREMENTS: ASPECT RATIOS: WP = 13 WN =4,
LOAD: CL = 50 PF.
Run DC Analysis and determine Gate Threshold (VI). Is the Gate Threshold Voltage (VI)
equal to VDD/2? Note that at Gate Threshold Voltage, VOUT = VIN.
Run Transient Analysis and determine Fall Time (t f) and Rise Time (tr) from the VOUT vs.
VIN plot. Are Fall Time (tf) and Rise Time (tr) equal to each other?
Using Transient Analysis, generate I vs VIN plot and determine when maximum current
flows in the inverter?
A copy of the description file in SPICE can be found in VLSI_WORK_DRIVE. Ensure
that the SPICE files extension is .CIR for successful simulation.

SYMMETRIC INVERTER WP = 13 WN =4, CL = 50 PF


*SPICE Code for CMOS Inverter
*Wp : Wn = 13 : 4
*spice option:
.width out = 80
.options nopage nomod
*circuit description:
mpu 3 1 2 2 penh w=13u l=3u
mpd 3 1 0 0 nenh w=4u l=3u
vdd 2 0 5
vin 1 0 pulse ( 0 5 3ns 3ns 3ns 20ns 40ns)

*model specification:
*MCE 3 Micron CMOS processes parameters- process 2
*NMOS Model (MOS type is Enhancement-Mode)
.model nenh nmos level=2 vto=0.85
+kp=30e-6 tox=470e-10 nsub=38e14
+ld=0.6e-6 u0=624 uexp=0.055 vmax=20e4
+neff=9.8 delta=2.0
+cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33
+pb=0.81 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11
*PMOS Model (MOS type is Enhancement-Mode)
.model penh pmos level=2 vto=-0.85
+kp=12e-6 tox=470e-10 nsub=8.7e14
+ld=0.5e-6 u0=200 uexp=0.18 vmax=12e4
+neff=4.0 delta=2.0
+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33
+pb=0.7 cgdo=4.0e-11 cgso=4.0e-11 cgbo=2.0e-11

cl 3 0 50f
.tran 1ns 80ns

.dc vin 0 5 0.1


.probe
*end simulation file:
.end

2.

Simulate an asymmetric CMOS inverter in PSpice 9.1 Student A/D circuit simulator using
the following design requirements.
DESIGN REQUIREMENTS: ASPECT RATIOS: WP = 4 WN =4,
LOAD: CL = 50 PF.
From DC and Transient Analysis, determine Gate Threshold (V I), Fall Time (tf) and Rise
Time (tr). Why Fall Time (tf) is smaller than Rise Time (t r)? Why Gate Threshold (VI) is
smaller than VDD/2?
Now, simulate the CMOS inverter using another set of design requirements listed below.
DESIGN REQUIREMENTS: ASPECT RATIOS: WP = 20 WN =4,
LOAD: CL = 50 PF.
From DC and Transient Analysis, determine Gate Threshold (VI), Fall Time (tf) and Rise
Time (tr). Comment on Fall Time (tf), Rise Time (tr) and Gate Threshold (VI).

3.

Simulate a symmetric CMOS inverter in PSpice 9.1 Student A/D circuit simulator for a
larger load using the following design requirements.
DESIGN REQUIREMENTS: ASPECT RATIOS: WP = 13 WN =4,
LOAD: CL = 200 PF.
From DC and Transient Analysis, determine Gate Threshold (V I), Fall Time (tf) and Rise
Time (tr). Is Fall Time (tf) is equal to Rise Time (tr)? Is Gate Threshold (VI) equal to
VDD/2? Comment on the actual values of Fall Time (tf) and Rise Time (tr)are they same
as in procedure 1? If not, why so?

4.

Fill up the following table from the Appendix.

SPICE Symbol
vto
kp
tox
nsub
ld
u0
uexp
vmax
neff
delta
cj
cjsw
mj
mjsw
pb
cgdo
cgso
cgbo

Meaning

Unit

SIMULATION AND MEASUREMENT:


Add the PSPICE code and simulation (both DC and Transient analysis) in your lab
report. Expected DC and Transient simulation for procedure 1 are provided below.
DC ANALYSIS:
OUTPUT VOLTAGE VS INPUT VOLTAGE
5.0V

4.0V

3.0V

2.0V

1.0V

0V
0V

0.5V

1.0V

1.5V

2.0V

2.5V

3.0V

3.5V

4.0V

4.5V

V(1) V(3)
vin

GATE THRESHOLD VOLTAGE VI: VDD/2 = 2.55 V (APPROXIMATE)VI SHOULD


BE VDD/2 = 2.5VTRY CHANGING PMOS WIDTH TO GET THE PERFECT VI.

5.0V

TRANSIENT ANALYSIS:
OUTPUT VOLTAGE VS. TIME, INPUT VOLTAGE VS. TIME
5. 0V

4. 0V

3. 0V

2. 0V

1. 0V

0V
0s

5ns

10 ns

15ns

20ns

25 ns

30ns

35 ns

40 ns

45ns

50 ns

V(3 ) V(1 )
Time

RISE TIME = 8 NS (APPROX.), FALL TIME = 6 NS (APPROX.) tr AND tf SHOULD


BE EQUALIF YOU GET VI TO BE VDD/2 = 2.5V, THEY SHOULD NATURALLY
BE EQUAL.

55ns

OUTPUT CURRENT (ICL) VS. TIME


200uA

150uA

100uA

50uA

0A

-50uA

-100uA

-150uA

-200uA

-250uA
0s

5 ns

10ns

15ns

20 ns

25ns

30ns

35ns

40ns

45 ns

50ns

55ns

60ns

65ns

70 ns

I(cl)
Time

NMOS DRAIN CURRENT IDSN = 22 A AND PMOS DRAIN CURRENT IDSP = -18
A.
NMOS AND PMOS DRAIN CURRENTS SHOULD BE EQUAL (IN MAGNITUDE)
DURING SWITCHING. A VI OF 2.5 V SHOULD MAKE THEM EQUAL.

75ns

80ns

RESULT:
Document the Gate Threshold Voltage (VI), Fall Time (tf) and Rise Time (tr) for each
procedure.

DISCUSSION AND CONCLUSION:


Summarize what you have done in this experiment including a discussion of each circuit
and interpretation of the associated parameters determined from them (as mentioned
above).
Answer the questions posed in the procedure section.
If you have any recommendations to improve the experiment, mention them as well.

REFERENCE:
1.

http://www.cadence.com/products/orcad/pages/default.aspx

2.

Orcad PSpice A/D Users Guide

3.

http://www.eecs.berkeley.edu/Pubs/TechRpts/1973/22871.html

APPENDIX:
Abbreviated SPICE manual:
Circuit Element Description:
Resistor and Capacitors:
General Form: Devicename n1 n2 Value
where Devicename is rxxxxxxx for a resistance, cxxxxxx for a capacitor.
n1, n2 are the node numbers of the device terminals.
Value is the resistance in ohms or capacitance in Farads.
MOSFETs:
General Form: Devicename n1 n2 n3 n4 model name l w
where Devicename is mxxxxxx
The nodes in order are drain, gate, source and substrate
l and w are channel length and width (in meters) respectively.
e.g.
mpu 2 1 3 2 penh l=3u w=10u
mpd 3 1 0 0 nenh l=3u w=4u
Note that the substrate of the p-type enhancement device is connected to the positive
supply whereas that of the n-type enhancement device is connected to the ground node.
Model name:
The simulator needs detailed information on the technology being simulated. The
MOSFET model in SPICE 2G5 permits 37 different parameters to be set in order to
describe the target technology. These parameters are included in a model statement and
the model name refers to the required model. The models of the CMOS p and n type
enhancement mode transistors given in the questions following this introduction are
values derived by the fabricators for this particular CMOS technology and should be
included in the circuit description file.

Signal Source Description:


In addition to describing the circuit it is necessary to describe the supply voltages and the
various
waveforms you wish to apply to the circuit. The element statement for an independent
voltage or current source is written in the form: Sourcename positive-node negative-node
type specification
where Sourcename is the voltage source identifier. Type specifies the general nature of
the source which could be DC, AC, SIN, PULSE or PWL (Piecewise Linear) with details
included in the specification entry.

DC Source:
vdd 4 0 dc 5
vbias 15 0 dc 750mV
Voltage sources, in addition to being used for circuit excitation, are the ammeters for
SPICE, that is, zero valued voltage sources may be inserted into the circuit for the
purpose of measuring current. They will, of course, have no effect on circuit operation
since they represent short-circuits.
Pulsed Voltages:
General Form: Sourcename n+ n- pulse (v1, v2, td, tr, tf, pw, per)
where n+ and n- have the same meaning as for a dc source.
v1 is initial voltage, v2 is the pulsed voltage,
td is delay time, tr is rise time,
tf is fall time, pw is pulse width,
per is the pulse period.
eg. Vclock 1 0 pulse ( 0, 5, 1ns, 2ns, 2ns, 100ns, 200ns)

Piece-wise Linear Voltages.


General form: Sourcename n+ n- pwl (t1 v1 t2 v2 t3 v3 ..)
Where n+ and n- have the same meaning as before for a dc source, each pair of values of
t and v specifies that the value of the source is v at time t.
The value of the source at intermediate values of time is determined using linear
interpolation on the input values.

Simulation Modes
SPICE can perform various types of analysis; we are concerned just with two: the
transient analysis and the dc analysis modes.
Transient Analysis:
In this mode, SPICE can be used as an oscilloscope to observe variations in voltage and
current with time.
General form:
.tran tstep tstop tstart
where, tstep is the increment time (in seconds)
tstop is the finish time
tstart is the initial time (default value is zero)
e.g. . tran 1ns 100ns
Note: The smaller the value of tstep, the finer is the detail seen in the waveforms. The
price paid is computer time, so you must ask yourself what could be a reasonable value
given the circuit parameter and input waveforms.

DC Analysis:
In this mode SPICE gives the values of requested node voltage or current as a function of
an independent voltage and current source.
General form:
.dc sourcename vstart vstop vincr
where: sourcename is the name of the voltage source to be varied.
Vstart is the initial value
Vstop is the final value
Vincr is the increment or step value
e.g. .dc vin 0 5 0.1
Generating Output
For any analysis mode the user must select which nodes are to be monitored. The output
can then be displayed by either of the following two methods:
1. a print statement giving tabular listing of the results of one to eight output variables with
the independent variable (time or voltage) in the left hand column and other variables in
the other columns.
2. a plot statement defining the contents of one plot of from one to eight output variables
versus the independent variable.
The two options are as follows:
General form:
.plot Mode out1 out 2 out8
.print Mode out1 out2 ..out8
Here Mode specifies the analysis mode, and out1, out2 is the list of nodes to be
monitored and can have one of the following three forms:
V(n1) specifies the voltage at node n1 with respect to ground.
V(n1,n2) specifies the voltage difference between node n1 and n2.
i(vname) specifies the current flowing in the independent voltage source named vname.
Eg: .plot dc v(2) v(5) v(7) i(vname)
.plot tran v(1) v(2) (0,5)

The (0,5) forces all nodes to be plotted on the same scale of 0 to 5 volts.

This laboratory instruction sheet has been updated by


Shahriyar M. Rizvi, Assistant Professor, Faculty of Engineering, AIUB, 2011, 2013, 2014