The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

The Storage or Data Register

All sequential logic circuits in the computer CPU are based on the
latch or flip-flop.
A significant part of the ALU is the register complement. In the
MIPS R-2000 computer which we will study shortly, there are
thirty-two 32-bit registers, generally called storage registers.
A storage register is a set of D FFs (generally master-slave D
FFs) which work in unison to store the number of bits in a
computer data word. In the case of the R-2000, each register has
32 D FFs to store 32 bits of data simultaneously.
To more fully understand the concept of the data storage register,
we first need to discuss and understand the data bus.
1

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

The Data Bus

A data bus is a collection of wires (or copper lines on a
printed circuit board or metal conductors on a
semiconductor chip) which carry data (bits) in parallel
from one part of a computer to another.
The MIPS R-2000 has 32-bit data words, so that 32 data
bits are transferred in parallel in data transfers. That
is, the MIPS R-2000 has 32-bit data buses.
There are various buses in the CPU of most computers,
but those that carry data are called data buses.
Data on the buses are 1s and 0s (two voltage levels).
2

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Data Bus Illustration

Clock

Input Data
Bus (8 Lines)

CLK
D7 Q7
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0

8-bit Storage
Register

D7

Q7

D6

Q6

Etc.

Etc.

CLK

Output Data
Bus (8 Lines)

The storage register shown above is connected to two 8-bit buses.

The 8 data lines are connected to the 8 inputs of the storage register.
Similarly, register outputs are connected to the 8 output bus lines.
Data is input to the register in parallel. That is, 8 bits (0 or 1) are
placed on the lines and stored in the register on one clock pulse.
3

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

The Concept of Data Gating

The data bus is a conduit which links registers to the ALU.
Generally, an ALU has two input buses, to which all
register outputs are electrically connected.
A second bus from the ALU returns results of ALU
operation to all the register inputs.
Register addressing, choosing which register transmits to
or receives data from to the ALU, allows data transfer
from/to the ALU.
Addressing, sometimes called gating, uses decoders and
multiplexers, circuits with which we are familiar.
4

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Gating Data Into a Storage Register

Register
Address
Bus

8-bit Storage Register

Clock

Input Data Bus

CLK
D7 Q7
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0

Output Data Bus

An address bus carries the identification of the receiving register.

The register address is decoded and ANDed with CLOCK to
provide a strobe to the buffer above, causing the 8 bits on the
bus to be stored in the 8 D flip-flops.
The register address and data buses go to all registers in a
computer (32 in the case of MIPS), but only the register addressed
will be loaded with data.
5

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Typical Input Configuration for Register Block

Data is transmitted on the
bus to all register inputs.
An address is also
transmitted to the decoder.
Simultaneously, a strobe
signal is transmitted to all
register enable* inputs.
The register that accepts
data is determined by the
address.

Clock (Strobe) Signal

5/32 Decoder

5-Bit
Address Bus

0
1
2
.
.
.
.
.
30
31

32-Bit
* Note: the register inputs are the data (32 bits ) Data Bus
and the clock (C) line. This clock input is called,
variously, clock, enable, or strobe. It
corresponds to the clock input on a D FF.
6

C Reg. 0
D
C
D Reg. 1
C Reg. 2
D
C
D
C
D
C
D
C
D

R. 30
R. 31

CPU Register
Block

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Typical Output Configuration for Register Block

5-Bit Address Plus Strobe

The 32 register output bits (the
Q output of each of the 32
5-Bit Address Plus Strobe
register ffs), are directed to
C Reg. 0
D
each of two 32:1 multiplexers.
C
A 5-bit address plus the strobe
D Reg. 1
pulse goes to each multiplexer.
C Reg. 2
D
This signal (strobe plus address)
C
selects which of the registers is
D
connected to each of the two
C

busses.
D
C
In the MIPS computer that we
D R. 30
will study, there are two ALU
C R. 31
input buses, since the ALU often
D
uses two operands.
CPU Register Block
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

32-Bit
Data Bus
32:1 MUX
32-Bit
Data Bus
32:1 MUX

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Exercise 1

The 4-bit register shown has

data inputs a, b, c, and d.
Data is stored in the register
by decoding the register
address on the address lines
(w-z) and then AND-ing this
decoded address with
Clock.
The register has address 0x
b. Wire up the decoder so
that data will be stored in
register b whenever the
correct address is put on the
address lines. (You may not
need all the inverters.)

Data In
a
b
c
d
Reset
Address
w (MSB)
x

D Q

Data a

C R

D Q

Data b

C R

D Q

Data c

C R

D Q

Data d

C R

y
z
Clock

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Shift Registers
Shift registers are particularly important in modern computers
and computing systems.
Not only do they perform the shifting or rearrangement of
numbers in some cases (although modern computers usually
employ shifters much faster than the old-fashioned shift register),
but they are also very valuable in communication systems.
They can be employed to convert serial data streams to parallel
and vice-versa (as in internet communications).
Although technically there are a number of variations of shift
registers (see Tokheim, page 260), we are really only concerned
with two practical registers: the serial-to-parallel shift register,
and the parallel-to-serial shift register.
10

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

The Serial-to-Parallel Shift Register

Data In

MSB
Parallel
Data
Out

Clock

LSB

In the shift register shown, data is shifted into the first masterslave D FF on the left when the clock goes high.
After the first clock pulse goes low, the output of the first ff is
available as an input to the second.
On the second clock pulse, MSB is shifted into the second ff, and a
new bit goes into the left ff.
On the third clock pulse, the bits shift again, and are now available
at the parallel output.
11

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Serial/Parallel Register Timing

Data In

MSB
Parallel
Data
Out

Clock

LSB
FF #3

MSB

FF #2
FF #1

LSB

Serial Data
1
Clock
12

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

0
N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Parallel/Serial Shift Register

Conversely, in the parallel-to-serial shift register, data is loaded
into the register just as it would be strobed or clocked into any
storage register.
However, in the parallel/serial shift register, the data can then be
clocked out bit-by-bit in serial form.
In general, the MSB is clocked out first, but, depending on the
design, LSB out first is also possible.
This shift register is very similar to the serial-to-parallel register,
with the exception of having the ability to load data into the
register in parallel.

13

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Parallel-to-Serial Shift Register

Parallel
Data In
DL
DS Q
Ld
C
R

DL
DS Q
Ld
C
R

DL
DS Q
Ld
C
R

Serial
Data Out

Reset
Load Parallel Data
Serial Data Clock

The parallel-to-serial shift register above has data

loaded using the parallel data inputs and the Load
Parallel Data strobe.
After data is loaded, it is shifted out using the serial
data clock.
14

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Parallel/Serial Shift Register Timing

Parallel
Data In

1
0
1

DL
Load+
D

DL
DS Q
Ld
1
C
R

DL
DS Q
Ld
0
C
R

DL
DS Q
Serial
Ld
1 Data Out
C
R

Reset
Load Parallel Data
Serial Data Clock

Serial
Data Out
Serial Data Clock

CR Q

Reset-

Serial
Clock Out

Load Parallel
Data
Clear
15

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Exercise 2

The 5-stage shift register is clocked as shown. Assume it is set/reset at startup.

On the timing diagram, plot the logic levels at Out for the number of clock
pulses shown.

CR Q

CR Q

Out

CR Q

CR Q

CR Q

Clock
Set/Reset
Out
1
Clock
16

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

7
N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

A Simple Binary Counting Circuit

Computer events are timed and synchronized by a clock,
so keeping track of timing becomes important.
Computers do not execute an instruction per clock cycle.
Most computer instructions take several clock periods
All instructions do not take the same number of clock periods

Thus counting clock periods as events is important.

Counting pulses can be done by binary counters, all of
which are made from master-slave T FFs.
A ripple counter is based on the T FF frequency
divider seen earlier (next slide).
17

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

T FF Frequency Divider
1

Clock

T FF as a frequency divider, with decoded

f/8 state.
f/2

f/4

Pulse Out

Reset
Clock frequency = f
T FF #3
T FF #2
T FF #1
1

Clock
18

0
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Frequency Divider as Ripple Counter

1

f/2

f/4

Clock (at
frequency f)
Reset

19

f/8

Count
MSB

LSB

Consider a variation of the T FF frequency divider.

The three Q outputs become counter digits. The f/8 ff is the most
significant bit (MSB), f/2 the least significant bit (LSB).
The outputs of the ffs represent the binary value of the number of clock
pulses up to 7. Every eight pulses, the counter starts over.
This is a ripple counter, since each stage of the counter must first
change to its new state (which takes a small amount of time) before it can
be the clock for the next stage. It counts modulo-8 since it counts
eight counts, 0-7, over and over again.
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

T FF Counter
1

f/4

f/2

Count
MSB

f/8

Clock (at
frequency f)

LSB

Reset

T FF #3

000

001

010

011

100

101

110

111

MSB

T FF #2

LSB

T FF #1
Clock
20

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

1
0

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Problems with the Binary Ripple Counter

While the so-called ripple counter works well and dependably in
many situations, it has some problems associated with its name.
The chief problem is that the Q output of each T FF acts as the
clock for the next stage of the counter.
This means that there is some delay due to the circuit parameters
after the clock has set and reset the LSB before the output will
change and clock the next stage.
Each stage adds another set of delays to the process.
For a very large counter (with many stages), the delays could get
so serious that the final stage was not clocked until after the clock
to the LSB had started the next clock cycle.
21

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Actual Counting Cycle with Ripple Counter

T FF #3

000

001

010

011

100

101

110 111

MSB

T FF #2
LSB

T FF #1
1
Clock

The real-time cycle of a ripple counter is shown above.

Each succeeding stage is further delayed from the input clock.
By the time the counting pulses get to the third T FF, the delay
may be 1/2 of the original clock cycle!
We will see a solution to this ripple problem in the next lecture.
22

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Counter Circuits
The ripple counter has problems, as we have
seen.
The parallel or synchronous binary counter
synchronizes all stages (flip-flops) so that they
change, or toggle, in parallel.
The parallel counter assures that the counter
output will always be correct, and that the wrong
count will not be accidentally decoded or
recognized.
23

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Synchronous Binary Counter

Counter stage 0
T
CR

Counter stage 1
T

Counter stage 2

CR

CR

Clock

Synchronous or parallel counter characteristics:

Uses T flip-flops
All stages (outputs) change in unison
Unlike the ripple counter, each stage is not triggered by the previous
stage. All stages are triggered by the clock
T input is activated (=1) when a stage should toggle.

In the 3-bit binary counter prototype above:

The clock is connected to all three counter inputs
How do we determine when a T input should 1?
24

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Synchronous Binary Counter (2)

Counter stage 0
T
CR

Counter stage 1
T

Counter stage 2

CR

CR

Clock

Consider stage 0. This stage counts 1s (or it performs counts for the
20 column in this three-bit number being counted, hence the name
stage 0).
This stage toggles every time the clock ticks. Its input should always
be a 1, since the ff only toggles on a 1 input to T, and we want it to
always toggle on a clock pulse (similar to the exercise in Lecture 7).
Then tie T0 (i.e., stage 0 T-input) to 1 (as before, we recognize that
1 would be a plus voltage such as +5 V. in a real digital circuit).
25

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Synchronous Binary Counter (3)

We now have T0 accounted for. What about T1?

Stage 1 counts the 21 (or the twos) column. It should toggle on
every second count, i.e., counts 2, 4, 6, and 8/0. We could reason
this stage out as in the Lecture 7 problem, but stage 2 will be even
more complex, so lets go ahead and look at a truth table for the T1
input in terms of count and next count.
26

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Synchronous Binary Counter (4)

The first two columns at
Count
T1
Q1
right are the T1 truth table
2 1 0 stage
(the right two columns
0 000
0
0
clarify the conditions that
1 001
1
0
determine T1 on each count). 2 0 1 0
0
1
1
1
The center column is Q1. It 3 0 1 1
4 100
0
0
alternates 0, 0, 1, 1 , etc.
5 101
1
0
Clearly, T1 must be 1 after
6 110
0
1
counts 1, 3, 5, 7, since Q1 will 7 1 1 1 Etc. 1
1
0 000
Counter starts over
toggle on the NEXT count.

27

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

Q1NEXT
0
1
1
0
0
1
1
0

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Synchronous Binary Counter (5)

We now need the Boolean expression for T1.

From the truth table, then:

T1 = Q2 Q1Q0 + Q2Q1Q0 + Q2 Q1Q0 + Q2Q1Q0

This is a fairly complicated relation, and it looks as

though many gates and connections will be required to
create the T input that we desire. However, lets first
plot the Booleans terms on a Karnaugh map:
00
01 Q1Q0 11
10
1
1
0

Q2

28

We see that the expression for T1 can be simplified to:

T1 = Q0

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

Count

T1

000

001

010

011

100

101

110

111

000

0
N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Synchronous Binary Counter (6)

Since input T1 is fulfilled by simply the output from stage 0, we

simply connect Q0 to T1 input, thus completing two stages of our
counter.
What about stage 2? This third stage will only toggle on every
fourth count, so it is a little harder figuring out input T2 simply by
reasoning it out. Again, the truth table and Karnaugh map easily
allow defining input T2.
29

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Synchronous Binary Counter (7)

Stage 2 only toggles on counts
4 (to 1) and 8 (to 0).
The Boolean expression for
T2 is:

=
T2 Q2Q1Q0 + Q2Q1Q0
The expression is plotted on
the K-map below the truth
table.
From the K-map, we can
simplify the stage 2 T input
to:
T2 = Q1Q0
30

Count
210

T2

Q2

Q2NEXT

stage

000
001
010
011
100
101
110
111

0
0
0
1
0
0
0
1

0
0
0
0
1
1
1
1

000

Counter starts over

0
0
0
1
1
1
1
0

Q1Q0

00

01

Q2 0

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

11 10
1
1
N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Synchronous Binary Counter (8)

The synchronous (parallel) binary counter is now complete.

Bringing output signals to the right as shown, these values will cycle
through counts 0-7 as the counter counts, so it is a modulo 8 counter.
Since all stages count in parallel, and since the delays through the AND
gate are small, the stages all toggle instantaneously in parallel.
This technique can be applied not only to a modulo 2n counter, but to
any other modulo-m counter, m not a power of 2 (example shortly).
31

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Exercise 3
Bit y

Less
Significant
Digit

Bit x

Clock

More
Significant
Digit

Reset

We have seen that there is a fairly straightforward method to

construct a parallel or synchronous counter using combinational
logic to modify the T-input of each FF in the counter.
Wire up this counter so that it counts modulo-4 in parallel. Use the
T inputs as shown on the preceding slides to accomplish the
toggling of the two flip-flops as the counter counts. Assume Reset
is only invoked at startup.
32

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Generalized Mod-2n Counter

Noting the schematic on the previous page, the following relationship
has probably occurred to some students.
Nevertheless, it is stated here as a ground-rule to illustrate that mod2n parallel counters are very simple to build.
For ANY mod-2n counter (2, 4, 8, 16, 32, etc.):

34

Use n toggle flip-flops.

Connect the clock to the clock inputs of all stages (i.e., to all T FFs).
Connect LSB T-input to 1 (where we know that 1 is a voltage).
Connect LSB Q-output to the T input of 2nd LSB.
For subsequent counter stages, AND all previous outputs and input to T
of the next stage. This makes use of the principle that in a mod-2n
counter, a stage only toggles when all previous stages = 1.
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Exercise 4
Wire the 5 T FFs below according to the general rules given to
build a 5-bit, modulo-32 counter. Assume that the clock is slow
enough that a few gate delays are trivial.

35

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Counting When the Cycle is Not a Power of Two

The 3-bit ripple and parallel counters we have seen
previously go through a cycle of 8 (that is, 0-7) and then
automatically reset to 0 and begin the count over.
Suppose we want to count in some other cycle than 8.
For instance, suppose we want to count on a cycle of 6?
In this case, we would want the counter to count 0-5,
and then reset to 0 on the sixth count.
Using the synchronous counter and the properties of
the decoder circuit, we can devise a circuit such as this,
based on the cycle-8 synchronous counter shown on the
previous slide.
38

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

A Modulo-6 Counter
Counter stage 0
"1"

T
CR

Counter stage 1
T
CR

Counter stage 2
T

MSB

CR

Clock

LSB

Consider the parallel counter above (which we just designed):

To count mod-6, we want it to count to 5 and then go to 0 on count 6.
At count 5, the counter will read (MSB-to-LSB): 101.
We want the next count to be zero (000) and not six (110).

Now consider what we want each individual stage to do after 5:

We want LSB to go from 1 to 0, i.e., reset.
We want the middle bit to stay zero (it is zero on count 5: 101).
We want MSB to go from 1 to 0 also.
39

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Modulo-6 Counter (2)

Counter stage 0
"1"

T
CR

Counter stage 1
T
CR

Counter stage 2
T

MSB

CR

Clock

LSB

Since the stage 0 bit always toggles, after count 5 (101) it will go to
zero (the next count would be 110, for which that bit goes to 0).
Stage 0 behaves correctly; we do not have to modify this stage.
The middle bit will toggle to 1 if we do not stop it because Q0 is 1.
We have to negate this input -- but only for the 5 condition.
The MSB does not toggle either the T2 input is Q0Q1 (= 0, since
Q1= 0), so the T2 input is 0. Thus we must force stage 2 to 0.
How do we fix these last two conditions?
40

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Modulo-6 Counter (3)

Consider the truth table for the Q output of the middle counter bit (Q1):
Each clock tick, Q1 will change if T1 =1; Q1 will remain the same if T1 =0.
What we require is that when T1 (Q0)=1, Q1 will change states, except when
T1 =1, and count = 5 (binary 101).
If T1 (=Q0) = 1, and the counter output is exactly 5, we want the output of
the middle counter bit to stay 0.

Then the truth table for T1 is:

Count

T1

Q1

Q1NEXT

000
0
0
0
001
1
0
1
010
0
1
1
011
1
1
0
100
0
0
0
101
0
0
0
110 & 111 Dont cares. Will never happen!

41

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Modulo-6 Counter (4)

Proceeding as before for T1 :

Q1Q0

00
Q2 0

42

01
1

11 10
1

Count
000
001
010
011
100
1 0 1 Etc.

T1

Q1

0
1
0
1
0
0

0
0
1
1
0
0

Q1 NEXT
0
1
1
0
0
0

Then the Boolean expression for T1 is:

=
T1 Q2 Q1Q0 + Q2Q1Q0 .
Plotting this on a 3-variable K-map above gives T1 = Q2Q0.
Therefore the signal created by inverted MSB (stage 2) ANDed with LSB
(stage 0) will, when input into the counter stage 1 T-input, cause that
middle bit to count correctly ALWAYS for a modulo-6 counter.

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Modulo-6 Counter (5)

43

Now consider the Q2 of the counter.

The truth table for T2 is:
Count
T2
Q2
Q2 NEXT
Q1Q0
000
0
0
0
00 01 11 10
001
0
0
0
1
010
0
0
0
Q2 0
1
1 X X
011
1
0
1
100
0
1
1
Etc.
101
1
1
0
=
T2 Q2Q1Q0 + Q2 Q1Q0 . At first glance, this cannot be simplified.
Thus,
However, note the Xs in the K-map. These are the dont care counts.
Since counts 6 and 7 never occur (the Xs on the K-map), we can make
them 1s as we learned for combinational logic. We can then simplify the
=
T2 Q1Q0 + Q2Q0 .
expression for T2 to get:
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Modulo-6 Counter (6)

Counter stage 0
"1"

T
CR

Counter stage 1
T
CR

Counter stage 2
T

LSB

T1 = Q2Q0

44

MSB

CR

Clock

=
T2 Q1Q0 + Q2Q0

Our resulting modulo-6 counter is shown above.

Note that when the MSB (Q2) becomes 1 (for count 100), the T input to the
middle stage is disabled until the count is reset, fulfilling the truth table
requirement for the middle bit T input being 0 for count 5 (101).
For the MSB, T2 would only be 1 for count 011 (3) (count 111 [7] does
not occur). Now the T input will also be 1 after count 5 (101) as well,
due to the OR gate, so that Q2 will return to 0 after count 5.
Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Mod-6 Counter Cycle and Timing

Counter stage 0
"1"

Counter stage 1

CR

Counter stage 2

CR

MSB

CR

Clock

LSB

Q2
Q1
Q0

Clock
45

000

001

010

011

100

101

000

001 MSB
LSB

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

1
N. B. Dodge 9/15

1
0

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Simplified Method to Build Non-2n Counter

The method just described for building a counter will always
produce the correct results with the minimum circuitry.
The method will also produce the correct results, but will not
always use the minimal number of gates:
To count any number m, m not a power of 2, determine the smallest
mod 2n counter such that 2n >m.
Build the parallel 2n counter (use the short cut if you wish).
Determine stages that must toggle to 0 on count m but do not, and
those that toggle to 1 but should not. Some stages may not need any
help they may behave properly without any modification.
Using an n-input AND gate, decode clock count (m-1).
For a counter stage that needs to go to 0, but has a 0 T-input on count
(m-1), OR the current T-input with decoded (m-1).
For each stage that should not toggle to 1, AND inverted (m-1) with
that current T-input.

The resulting counter will count mod-m.

46

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Example of Simpler Method Mod-6 Counter

Counter stage 0
"1"

Counter stage 1

CR

Counter stage 2

CR

MSB

CR

Clock

LSB

Inverted (m-1)
Decoded "5" (m-1)

Note that this version of the circuit uses slightly more logic, but
that the counter is equally valid. Also, it is conceptually easier
(and yes, it would be an acceptable answer on a test)!
47

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and

Computer Science

Summary
Like their simple combinational-logic relatives, the D,
J-K, and T flip-flops find many uses in modern
computing.
These include storage registers, counters, and shift
registers.
In our next lecture, we will design additional sequential
circuits.
In future lectures on computer architecture and design,
we will see just how sequential logic is employed in a
modern computer CPU.
48

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15

Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Take-Home Exercise

We now understand how to make any mod-2n or mod-m counter (m not a

power of 2) that counts forward. What about a counter that counts
backward? Assume you want the counter below to count mod-6 backward.
That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on start-up, and
design the wiring to make the counter count properly.
Hint: Remember the K-map method will work for ANY counter. Note: in
the arrangement below for the counter bits, x is the most significant bit, z
the least significant.
First 10 answers to my office during office hours gets +3 on next test!

49

Lecture #8: Registers, Counters, and Other Latch-Based Circuits

N. B. Dodge 9/15