Leveraging Emerging Technologies

in Computing
Giovanni De Micheli

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

Computing today

(c) Giovanni De Micheli

Computing today

(c) Giovanni De Micheli

Computing today

(c) Giovanni De Micheli

Walls
High-performance, energy-proportional servers
High speed computation and data retrieval

Ultra-low power computing and communication

Connect myriad of devices for Internet of Things

(c) Giovanni De Micheli

Walls and game changers

New computing paradigms

Quantum computing (superposition, entanglement)

Analog computing (memristors, dynamical systems)
Neuromoprhic computing
In-memory computing

New materials and devices

Enhanced CMOS devices
Exploit heterogeneous integration

Parallelism in algorithms and software

Exploit new computational methods

Use new design methods and tools

Revisit hardware synthesis and design techniques
(c) Giovanni De Micheli

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

Semiconductor technologies
Most manufacturing technologies have geometries
in the nanometer range
Recently-established nano-electronic technologies
Tri-Gate (FinFET) transistors
Fully-depleted Silicon on Insulator (FDSOI)

Downscaling geometries is still effective

Emerging nano-electronic technologies
New materials and devices for processing and memory

(c) Giovanni De Micheli

22 nm Tri-Gate Transistors

[Courtesy: M. Bohr]
(c) Giovanni De Micheli

10

Tri-Gate vs. planar transistors

Smaller current for same gate voltage (when offf)

Same gate delay for smaller operational voltage
[Source: Intel]
11

Fully Depleted SoI Transistors

UTBB FD-SOI

FinFET
G1

G1

G2
=G1
Tox

T
Tsi/2si/2
G2
=G1

G1

BOX

Tsi

G2=
BOD
Y

TriGate and FDSoI look similar modulo a rotation

Fine power-consumption control through body bias
[Courtesy: STM]
12

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

13

Emerging nano-technologies
Enhanced silicon CMOS is likely to remain the main
manufacturing process in the medium term
The 7nm and 5nm technology nodes are on the way
IMEC VIEW OF LOGICbeyond
TECHNOLOGYthe
ROADMAP
What are the candidate technologies
5nm node?
Early production

Silicon Nanowires (SiNW)

Carbon Nanotubes (CNT)
2D devices (Flatronics)
and many others

2014
iN14

2016
iN10

2017-2018
iN7

2018-2019
iN5

>2020
iN3

FinFET

FinFET

FinFET

Lateral nanowire (HGAA)

Lateral nanowire (HGAA)

0.8

0.8-0.7

0.7-0.6

0.7-0.5

0.6-0.5

70-90, 193i

52-64, 193i

36-46, 193i

26-36, EUV, 193i

18-28, EUV, 193i

Vertical nanowire (VGAA)

Vdd (V)
Gate Pitch (nm)
Device

FinFET

FinFET

FinFET {HGAA}

HGAA

HGAA {VGAA}

Channel nfet/pfet

Si / Si

Si / Si {SiGe}

Si / SiGe

Si/ SiGe

High mobility

FinFet scaling

What are the differentiators and common

denominators from a design standpoint?

Novel device architectures & high mobility channels

h/vGAA=horizontal/vertical Gate-all-Around nanowire

(c) Giovanni De Micheli

14

Silicon Nanowire Transistor

Fully compatible with CMOS process

Gate all around
High Ion / Ioff ratio
(c) Giovanni De Micheli

15

Vertically-aligned SInW

(c) Giovanni De Micheli

16

FinFET to Nanowire FET

FinFET

NW FET
17

Vertical silicon nanowire transistors

Fully compatible with CMOS process

Higher device density
More complex fabrication process
[Guerfi, Nanoscale 16]
(c) Giovanni De Micheli

18

Carbon Nanotube Transistors

CNTs benefit from higher mobility and thus higher currents

CNTs grown separately but can be ported to Si wafers
Handling CNT imperfection is major design and fabrication issue
(c) Giovanni De Micheli

19

CNT nanocomputer
First CNT computing engine
Runs 20 MIPS instructions
Multitasking

[Shulaker, Wong, Mitra et al, Nature 13]

(c) Giovanni De Micheli

20

2D electronic technologies

[Kis, Nature 2011]

Graphene, MoS2 and other materials

Single or few atomic layers
High Ion / Ioff ratio for MoS2 (108) but n-type mainly
(c) Giovanni De Micheli

21

Double gate SiNW FET

S
CG
S
CG
PG

p-FET

S
CG
n-FET

Electrostatic doping
Electrically program the transistor to either p-type or n-type

22

Fabricated device view

100 nm gate segments

350-nm long nanowires
20-40 nm wire diameter
23

Device cross sections

NW
stack

Gate
Oxide

NW
stack
d<20nm

PolySi

100nm
2
4

M. De Marchi et al., IEDM 2012, TNANO 2013.

100nm
24

Device working principle

PG = 1 n-type
CG = 0

OFF

PG = 1 n-type
CG = 1

ON

PG = 0 p-type
CG = 1

OFF

PG = 0 p-type
CG = 0

ON
25

Device Id/Vcg
Vds=2V
Vcg

Log( Id [A] )

Vpg

Vpg = 0V
Vpg = 2V
Vpg = 4V

2
Vcg [V]

[Courtesy: De Marchi, IEDM 12]

26

Similar devices
Controlled devices can be realized with various
materials and shapes (e.g., FINFET)
SiNW controlled-polarity devices can be made with
one polarity gate on one side [Heinzig]
Polarity-gate bias can enable:
Steep Subthreshold
Multiple threshold voltages

(c) Giovanni De Micheli

27

Three-independent-gate SiNWFET
vElectrostatic control

vStructure

S D PGS

0 1

Vertically stacked nanowires

3 independent gate regions
Schottky barrier contacts at S/D

Polarity and Vt controllability

CG

PGD

State

ON (P-type)

ON (N-type)

OFF (LVT)

OFF (LVT)

OFF (HVT)

OFF (HVT)

PGS
PGS CG PGD
'0'
'0'
'0' '0'
S='0'
S='0'

p-type

D='1'

(a)

ON

CG
'1'

PGD
'0'

PGS CG PGD
'0' '0'
'1'

S='0'

D='1' (c)

(b)

OFF

D='1'

OFF-Low Leakage

2
8

28

Controllable polarity in 2D
2D Controllable-polarity transistor ( WSe2 )
Source

VDS = 1V
WSe2

Drain

ION n-type = 4 A

PG

PG

CG

ION p-type = 250 nA

VCG

IOFF = 100 fA

Leakage current, Icg

[Resta, Scientific Reports 2016]

(c) Giovanni De Micheli

29

Modeling various emerging nanogates

CNFETs

SiNWFETs

Graphene FETs

4T Nanorelays

6T Nanorelays

(c) Giovanni De Micheli

c1"

c1"

c2"

c2"

cn"

cn"

t"

(c1"c2""cn)""""t"

Reversible Logic

30

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

31

Logic level abstraction

Three terminal transistors are switches
A loaded transistor is an inverter

Controllable-polarity transistors compare two values

A loaded transistor is an exclusive or (EXOR)

The intrinsic higher computational expressiveness

leads to more efficient data-path design
The larger number of terminals must be
compensated by smart wiring
Fine-grained programmability

(c) Giovanni De Micheli

32

Logic cell design

CMOS complementary logic is efficient only for negative-unate
functions (INV, NAND, NORetc)
Controllable-polarity logic is efficient for all functions
Best for XOR-dominated circuits (binate functions)
Negative Unate functions
INV

NAND2

Gnd

XOR2

Gnd

Gnd

Binate functions

B
Vdd

Vdd

A
Vdd

Similar to regular CMOS

Only 4 transistors when compared to 8

transistors with a regular CMOS
(c) Giovanni De Micheli

[Courtesy: H. Ben Jamaa, 08] 33

Layout abstraction and regularity

n1

n6

G1
g1

G1
n2

G2

g2

n5

G2
n3

Two transistor pairs

grouped together

n4

XOR2

NAND2

(c) Giovanni De Micheli

[Courtesy: Bobba, DAC 12] 34

Logic Design Abstraction:

Biconditional Binary Decision Diagrams

Native canonical data structure for logic design
Biconditional expansion:

f (v, w,.., z) = (v w) f (w', w,.., z) + (vw) f (w, w,.., z)

f(v,w,..,z)

Each BBDD node:

Has two branching variables

PV=SV
f(w,w,..,z)

PV=v

Implements the biconditional expansion

SV=w

Reduces to Shannons expansion for

single-input functions

PV=SV
f(w,w,..,z)
35

BBDDs are Compact (Adder Function)

Sum#

" ="

Cout#
"

0"

1"

"

S1#

="
0"

S3#

S2#
"

="

0"

1"
1"

"

S0#

1"

="

"

="

1"

="

0"

1"

1"
1"

Number of nodes
of adder(n):

3n +1

"

="
1"

"

="

Standard"Edge"
0"

1"
1"

Compl."Edge"

36

BBDDs are Compact (Majority Function)

MAJ7(a,b,c,d,e,f,g)/
/

MAJ5(a,b,c,d,e)-

=/
/

=/

MAJ3(a,b,c)MAJ3(a,b,c)-

=/
0/ 1/

0/ 1/ 1/
1/

=/
0/ 1/

1 2 1
11
n + n+
8
2
8

=/

MAJ5(a,b,c,d,e)/

Number of nodes
of MAJ(n):

=/
0/ 1
1/
MAJ5(a,b,c,d,d)-

1/
Standard/Edge/

MAJ(3): 4
MAJ(5): 7
MAJ(7): 11
.

Compl./Edge/
Input/Inv./Edge/

37

New logic models and data structures

Design with emerging devices requires exploring new

logic models combining:
XOR primitives (programmable complementation)
MAJority functions (programmable AND/OR)

The resulting models and algorithms have wide

applicability to logic design (including CMOS)

(c) Giovanni De Micheli

38

Majority logic: a new/old paradigm?

In fact <x,y,z> is probably the most important ternary operation
in the entire universe, because it has amazing properties that
are continuously being discovered and rediscovered.
Donald Knuth, The Art of Computer Programming, Vol. 4A
Majority Inverter graphs as data structure for logic synthesis
Reachable design space
Surprising experimental results
MAJ

MAJ

MAJ

(c) Giovanni De Micheli

MAJ

MAJ

[Courtesy: Amaru, DAC 14]

39

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

40

that SPE is still efficient for thin films and leads to high
dopant activation levels.

one of N+ doped polysilicon i.e. 5.1eV). It demonstrates that

the threshold voltage of top FETs can be dynamically tuned
by biasing the bottom FET. This characteristic presents strong
interest for the stabilization of SRAM cells [13, 14].

Unique low temperature features

We have already shown that the reduced thermal budget
(overall temperature kept below 600C) used for the top layer Conclusion
leads to highly controlled short channel effects [8]. It also
yields thinner EOT than its Rapid Thermal Annealing In this 3D sequential integration, we demonstrate our ability
counterpart. Capacitance measurements were performed on N to integrate salicided access in the bottom layer. (110) PFETs
and PFETs of top and bottom layers, fig.10. With a 5nm HfO2 are processed on (100) NFETs and low temperature RSD are
gate dielectric for both types of devices we observed a 4 developed for the top layers. In addition, the use of low
EOT reduction: 1.5nm (resp. 1.6nm) for top NFET (resp. thermal budget process leads to a reduced interfacial oxide
PFET) compared to 1.9nm (resp. 2nm) for bottom NFET layer together with very low gate current. For the first time
(resp. PFET). The EOT decrease is due to the reduction of the electrostatic coupling between the layers is demonstrated
interfacial
oxide growthof
as shown
on the cross
TEM as a function of ILD thickness (an up to 130mV VT shift was
Fusion
sensing
andsectional
computing
images of the two gate stacks (fig.11). Gate current was observed).
plotted as a function of EOT (fig.12). This figure of merit
3D integration
sensors
clearlyunderlines
the advantage of with
low thermal
process: JG is Acknowledgments
around 5 decades lower than the SiO2 reference curve.
This work was partly supported by the French National
3D specificities
Research Agency (ANR) through Carnot funding and by the
We performed
a complete optimized
3D integration ((110) ST-IBM-LETI Alliance program.
Sequential
integration
was used for top PFETs). ID(VG) are shown on fig.13. They
exhibit noVOL.
degradation
of bottom characteristics due to top
IEEE TRANSACTIONS ON NANOTECHNOLOGY,
11, NO. 1, JANUARY 2011computing
9
ReRAM
integration
process. Theand
observed shift of the threshold
voltage between top and bottom layers is attributed to the

What is next ?

Technology hybridization

ILD

(a)

Salicide
Si
20nm

(b)

HfO2 anneal
Poly deposition
Spacers deposition
dopant activation

BOX

515C (5 min)
515 (40min)
480C
600C (2min)

Sheet resistance (Ohms/sq)

Heterogeneous integration

100
90
80
70
60
50
40
30
20
10
0

NiSi +F
Blanket reference
NiSi reference Anneal at 600C
NiSi +F Measured on bottom active

after top FET processing

Max TB =600C 2 min

3
4
5
Time (min)

Fig. 4: Influence of F implantation in NiSi in

[Sacchetto,
Nanoscale12]
[Batude,
IEDM 14]
Fig.3: De
a - SEM
cross-section
of bottom FET source
(c) Giovanni
Micheli
term of electrical stabilization when submitted to
Fig. 2: TEM cross section of two stacked

41
Fig. 2. (a) after
Equivalent
electrical
schematic
thedewetting
TSV with ReRAM memory
top FET
process
without of
any
600C
anneal (blanket wafers) and comparison
transistors featuring a 110nm thick ILD. Topelements
and
(denoted by the switch and the ideal memory element M).
(b) Reevidenced. b- Summary of the thermal budget seen
The die
measured results on bottom FET active
bottom active thickness are around 30nm.constructed 3-D photograph of the TSVCu/TiO 2 /Pt device stack. with
by the
FETs.
is cleaved to reveal the TSV
and bottom
the ReRAM
stack deposited on top.(VanderPaw structures) after top FET processing.

ARTICLES

ReRAMs for artificial neurons

NATURE NANOTECHNOLOGY

DOI: 10.1038/NNANO.2016.70

Spike event backpropagation

Input spike trains

w1
w2
...

Neuron soma

Dendrites

w0

Postsynaptic
potential
(PSP)

Neuronal
input

Axon

Neuronal
membrane
Spike event
generation

Output spike
train

wN
Plastic
synapses
Biology

Lipid bilayer

Technology

Top electrode (TE)

Phase-change
cell

+ + + + + + + + +
BE

Figure 1 | Articial neuron based on a phase-change device, with an array of plastic synapses at its input. Schematic of an articial neuron that consists of
the input (dendrites), the soma (which comprises the neuronal membrane and the spike event generation mechanism) and the output (axon). The dendrites
may be connected to plastic synapses interfacing the neuron with other neurons in a network. The key computational element is the neuronal membrane,
which stores the membrane potential in the phase conguration
of a nanoscale
(c) Giovanni
De phase-change
Micheli device. Owing to their inherent nanosecond-timescale
42
dynamics, nanometre-length-scale dimensions and native stochasticity, these devices enable the emulation of large and dense populations of neurons for
bioinspired signal representation and computation.

[Tuma et al, NatureNano 16]

SiNWs: ideal biosensing support

Reprinted from Curreli et al., IEEE TNANO 7, 2008

0.1

10

100

Cell

Virus

Nanowire

Protein

Nucleic Acid

QuantumDot

SENSITIVITY

Molecule

Atom

Best interface to proteins

Carbon Nanotube

1. Nano size

1000

10

nm

2. Surface-to-volume ratio
Larger interaction area
Charge confinement

3. Silicon biomodification
4. Compatibility

SPECIFICITY

INTEGRATION
43

SiNW biosensors
Puppo et al. BioCAS 2014

Bare NWs

Log(Ids[A])

NWs functionalized with Ab

Bare NW
NW+anti-VEGF

The VoG parameter

0

Vds [V]
44

Example of sensor integration

Muti-sensor for lab animals

Chip implant in mouse

Chip layers

Step injection response

[Baj-Rossi, 15]

45

Outline
Introduction and motivation
Technological innovations
Emerging nanotechnologies and devices

Design with emerging technologies

Physical and logic synthesis

New technologies for broader computing systems

Device fusion

Conclusions

(c) Giovanni De Micheli

46

Conclusions
Computing is evolving in various directions and permeates
everyday life and activities
Computing is still mainly based on von Neuman architectures,
switching theory and silicon devices
New materials and devices can change the physical substrate
of computation, making it more efficient and broader in scope
Progress will require a strong coordination of technology,
architecture and software as well as design methods and tools

47

47

Thank you
Yusuf Leblebici (EPFL)
Pierre Emmanuel Gaillardon (U. Utah)
Davide Sacchetto (CSEM)
Michele de Marchi (ESPROS Photonics)

(c) Giovanni De Micheli

48

Thank you

(c) Giovanni De Micheli

49