In FPGA design some reason can cause the setup problems.

i think the first task

is to find out what caused the problem through reads yout sta report. when you f
ind it you can try to fix it as the following way.
1. too many logic levels, this is always caused by deep nested "if else" in hdl
code,
or big adder tree with no pipelining,big comparator or some other arithmetic cir
cuits synthesized into combinatorial logic.
when the logic levels increase the setuoptime increase, by certain degree,setup
time problems comes up.
method to decrease logic leves is to use "case" to take instead of "if else".
add pipelining into big arithmetic circuits that may be synthesized into combina
torial logic.
2 long route delay or big fanout
long route delay can cause a big propagation delay on signal,this delay will be
add up to setup time. when the place and route is not proper in fpga,this proble
ms will come up.
method to combat this problem is that you can try to use the highest p&r level
items which can be chosed in ise tool menu,and you can choose timing driven ,one
hot code of state machine in synthesis attribute and place attribute of your de
sign tool,cancle resource share attribute.
if the tool cann't solve this problem with its high effort level,then you have t
o do something yourself to gain the desired performance of design. you alse can
used high speed net to replace the long delay net through write UCF constraint i
n ucf editor. make proper location constraints.
another way to resolve long delay in net is that you can insert sevel ffs on tha
t long delay net to divide it into sevels short ones.
big fanout can cause a long transition time on the signal edge ,the big transiti
on time can be add to setup time too.
two method can be used to resolve this problem,the first one: you can use your t
ool to fix this problem automatically, you can restict the fanout number listed
in the synthesis tool property menu. change it inti a much small one if you had
find out that the setup problem is caused by large fanout. the second one :you c
an duplicate the ff whit have a big fanout. use two or more ffs two drive the si
gnal that had been driven by a single ff before.
3. unproperly designed asynchronism circuits,it can bring in setup problems too
,
try your best to avoid asynchronism design ,if it cann't be avoid ,use proper sy
nchronizer circuit to make robust transition betweent asynchronism clock domains
4 add input and output registers to your design to hold the input data into fpga
and output data out of fpga,then pack these registers into iob to mimimum the i
nput delay and output delay at the boundary of your fpga
5 some advance techs can be used to promote your design performance too,
such as multicycle ,latch and so on