Microprocessor Architecture and Assembly Language

Chapter 2
Microprocessor Architecture
Processors & Assembly Language
Dr. Bassel Soudan &

Dr. Ali El-Moursy
Where in history are we?

Processor
Data Bus
Address Bus
4004
1st Microprocessor chip 1971
8008
16K Memory 1972
8088
64K Memory 1974
8086
16
20
1 MB Memory 1st IBM PC
80286
16
24
IBM PC/AT
80386DX
32
32
Introduced Protected Mode
80486
32
32
1st processor with built in floating point unit
Pentium
64
32
232 = 4 GB of Memory
Pentium II
64
Pentium III
64
Pentium IV
64
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The
8086
and
8088
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The 8086/8088 Architecture
The 8086 uses three busses to perform its

operations
The address bus.
The data bus.
The control bus.
When the 8086 wants to access a memory

location, it places the address on the address
bus, sends the appropriate control signals and
waits for information to come back on the data
bus.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The Address Bus
20 bits wide (A0 A1A19)

Therefore, the 8086 can access locations with
addresses from 00000H to FFFFFH.
Or, the 8086 has a memory address space of 1 Mega
locations.
Unidirectional.
Information flows out of the microprocessor and
into the memory or peripherals.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The Data Bus
16 bits wide (D0 D1D15) for the 8086 and 8 bits

(D0 D1D7) wide for the 8088.
Bi-directional.
Information flows both ways between the
microprocessor and memory or I/O.
Since the data bus is 16-bits wide, then the 8086

can manipulate data 16 bits at-a-time.
The 8088 can only manipulate 8 bits a time.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The Control Bus
There is no real control bus. Instead, the control

bus is made up of a number of single bit control
signals.
INTR
NMI
MN / MX
RD
WR
HOLD
HLDA
M / IO
OEN
ALE
INTA
TEST
READY
RESET
Dr. Bassel Soudan &

Dr. Ali El-Moursy
I/O Devices
The 8086/8088 can generate a 16-bit I/O device

address.
This means that the 8086/8088 can have a total of
65,536 I/O devices connected to it the same
time!!!
The 8086/8088 have an I/O address space of 64K
devices.
Communication with each I/O device uses the

same data bus as communication with memory
locations.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
Software Model of the 8088/8086 MPU
8088/8086 have thirteen 16-Bit Registers:

Instruction Pointer (IP)
Always contains the address of the next instruction to be
fetched from memory.
Four Data Registers (AX, BX, CX, DX)

General purpose registers.
Two Pointer Register (BP, SP)

Pointer registers for implementing things like linked lists.
Two Index Register (SI, DI)

Allow indexing through an array.
Four Segment Register (CS, DS, SS, ES)

Identify four different memory segments.
8088/8086 have one 9-bit Register:

Status Register (SR)
Contain flags that identify different situations in the processor.
It is actually 16 bits, but only 9 are used.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
The 8086/8088 registers

15
Instruction Pointer
IP
CS
DS
Segment Registers
SS
ES
Data Registers
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
SP
Index & Pointer

Registers
BP
SI
DI
Status Register
Code Segment
Data Segment
Stack Segment
Extra Segment
Accumulator
Base Register
Counter
Data Register
Stack Pointer
Base Pointer
Source Index
Destination Index
SR
Dr. Bassel Soudan &

Dr. Ali El-Moursy
10
The 8086/8088 and Memory
The 8086/8088 have a memory address space of

1 Mega locations,
However, these locations are not all accessible at
the same time.
The 8086/8088 has a segmented view of

memory.
A program can only access a total of 256 Kilo
locations of memory at the same time
These 256K locations are further broken into four
segments of 64 Kilo locations each.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
11
Segmented Memory
Each Segment Register
points to the starting
address of a particular
segment of memory
FFFFFH
Code Segment
(64Kbytes)
CS
DS
SS
Data Segment
(64Kbytes)
ES
Segment order within memory

is not important.
But, good programming
requires that code and data
segments should not overlap
Stack Segment
(64Kbytes)
Extra Segment
(64Kbytes)
00000H
Dr. Bassel Soudan &

Dr. Ali El-Moursy
12
Segment Registers & Memory Segments
The 8086/8088 has 1 Mega byte address Space.

The memory is partitioned into 64 Kbyte
segments.
Each segment is assigned a base address that
identifies its starting point.
The registers associated with the segments:
Code Segment CS
Stack Segment SS
Data Segment DS
Extra Segment ES
Dr. Bassel Soudan &

Dr. Ali El-Moursy
13
Segment Registers & Memory Segments
The CS, SS, DS, ES registers contain a 16 bit

base address that points to the lowest addressed
byte of the segment memory
The segment registers are user accessible.
4 segments gives a total of 256 Kbytes of active

memory.
64 Kbytes for Code Segment (Program Storage)
64 Kbytes for Stack Segment (Stacked Data)
128 Kbytes for Data Segment & Extra Segment
(DS, ES)
Dr. Bassel Soudan &

Dr. Ali El-Moursy
14
Mapping of Logical and Physical Addresses
Internally, the 8086/8088 have a logical view of

addresses
An address is a 16-bit offset from the beginning of
some segment.
The beginning of the segment is considered to be
a 16-bit value stored in some S register.
The operation to translate the logical address

(16-bit segment base:16-bit offset) to a 20-bit
physical address is called mapping and is done
automatically in the processor.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
15
Offset Register is extended 4-bits to the left

Segment Register is extended 4-bits to the right
Add operation is performed between the modified
4 Bits 16 bits (BP, BX, SI, DI, IP)
registers
0000
Offset Register
16 Bits (CS,DS, SS, ES) 4 Bits
Segment Register
0000
20 bit adder
20 bit address
Dr. Bassel Soudan &

Dr. Ali El-Moursy
16
Segment registers contain the starting addresses

of the segments ( CS, DS, SS, ES)
CS
DS
Segment Registers
SS
ES
Code Segment
Data Segment
Stack Segment
Extra Segment
Index & pointer registers are offset registers so

the addresses they carry are relative address to
the segment start in segment registers
SP
Index & Pointer

Registers
BP
SI
DI
Stack Pointer
Base Pointer
Source Index
Destination Index
Dr. Bassel Soudan &

Dr. Ali El-Moursy
17
Examples
If the segment Base = 1234H and Offset is 0022H,
what is the physical address?
What would be the offset required to map to
physical address location 002C3H if the contents
of the corresponding Segment register are
002AH?
Dr. Bassel Soudan &

Dr. Ali El-Moursy
18
The Processor and the Memory
The 8086 has a 16 bit data bus, while memory

width is typically 8-bits.
The processor word is 16-bits while the memory
word is 8-bits.
How can the two interact??
When the processor sends an address to

memory, the memory returns the contents of the
location at that address AND the contents of the
location immediately following that address.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
19
The Processor and the Memory
Assume the table to the right is a

section of memory.
00726H
A0H
00725H
55H
00724H
02H
If the 8086 asks for the contents of
address 00724H, what will it get
00723H
F2H
back from memory?
Memory will return the value 5502H on the data
bus.
02H comes from memory location 00724H and 55H

comes from location 00725H.
This is called little endian because the lower order bits
are taken from the location with the lower address and the
higher order bits are taken from the location with the higher
address.
The wires of the data bus will carry the following

combination: 0101 0101 0000 0010
Dr. Bassel Soudan &

Dr. Ali El-Moursy
20
Memory Address Space and Data Organization
Each two locations

in memory form
one word.
The processor reads
and writes one word
at a time.
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
} word 1
} word 0
If the word begins at an even address, it is called

an aligned word.
If the word begins
at an odd address,
it is called misaligned.
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
} word 3
} word 2
Dr. Bassel Soudan &

Dr. Ali El-Moursy
21
Aligned vs. Misaligned Word
How can we get aligned vs. misaligned words?

Compilers always treat char type variables as an
8-bit value.
Therefore, they will only reserve one 8-bit memory
location for each variable declared as char.
Older compilers treat int type variables as a 16bit value.

Therefore, they will reserve two 8-bit memory locations
for each variable declared as int.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
22
Aligned vs. Misaligned Word

main ()
{
int
char
00105H
i, j;
c;
00104H
Byte 0
00103H
Byte 1
00102H
Byte 0
00101H
Byte 1
00100H
Byte 0
c
j
i and j are aligned
}
main ()
{
char
int
c;
i, j;
00105H
00104H
Byte 1
00103H
Byte 0
00102H
Byte 1
00101H
Byte 0
00100H
Byte 0
i and j are misaligned

i
c
Dr. Bassel Soudan &

Dr. Ali El-Moursy
23
The x86 architecture also defines a double word.

A double word are 32 bits treated as one data
item.
Double words are used as pointers to other data in
memory.
A double word occupies 4 consecutive memory

locations.
The processor generates the address of the
lowest address memory location.
The memory system sends back:
M[Address] M[Address+1] M[Address+2] M[Address+3]
Dr. Bassel Soudan &

Dr. Ali El-Moursy
24
Aligned Double
If the double word starts at a memory address that
is a multiple of 4, it is called an aligned double.
00008H
00007H
Byte 7
00006H
Byte 6
00005H
Byte 5
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
}
}
Double word 1
Double word 0
Dr. Bassel Soudan &

Dr. Ali El-Moursy
25
Misaligned double
0000BH
Byte 11
0000AH
Byte 10
00009H
Byte 9
00008H
Byte 8
00007H
Byte 7
00006H
Byte 6
00005H
Byte 5
00004H
Byte 4
00003H
Byte 3
00002H
Byte 2
00001H
Byte 1
00000H
Byte 0
Double word 1
Double word 0
Dr. Bassel Soudan &

Dr. Ali El-Moursy
26
Aligned vs. Misaligned Double Word
Given the x86 segmented view of memory, a

pointer needs to specify two items:
The segment starting address (16 bits)
The location pointed to within the segment (16
bits)
Together, these form the 32 bits of the double
word.
The higher order two bytes are the starting address of
the segment (Base Address) and the lower order two
bytes are the index within the segment (Offset).
Dr. Bassel Soudan &

Dr. Ali El-Moursy
27
Aligned vs. Misaligned Double Word

main ()
{
int
int
char
00103H
*i;
j;
c;
}
main ()
{
char
int
int
00102H
Byte 0
00101H
Byte 1
00100H
Byte 0
000FFH
Byte 3
000FEH
Byte 2
000FDH
Byte 1
000FCH
Byte 0
c
j
Double word i and

word j are aligned
00103H
c;
*i;
j;
00102H
Byte 1
00101H
Byte 0
00100H
Byte 3
000FFH
Byte 2
000FEH
Byte 1
000FDH
Byte 0
000FCH
Byte 0
Double word i and

word j are misaligned
Dr. Bassel Soudan &

Dr. Ali El-Moursy
28
Data Types
The 8086 defines several data types:
Nibble
Byte
Word
Double word
4 bits
8 bits
16 bits
32 bits
It also defines a couple of integer data types:

Signed Integer
Unsigned Integer
Binary Coded Decimal
Dr. Bassel Soudan &

Dr. Ali El-Moursy
29
Integer Data Types
Unsigned Integer
All of the bits represent significant value.
The number is considered an absolute value.
Signed Integer
The most significant bit represents the sign of the
number.
If the MSB is 0, the number is positive and the rest of the
bits represent the bits of the number.
If the MSB is 1, the number is negative and the rest of
the bits represent the 2s complement of the actual
number.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
30
Range of Representation
The range of representation for an unsigned

integer is:
0 2n-1
where n is the number of bits
An 8-bit unsigned integer can represent numbers in the
range 0 28-1 (0 256-1 or 0 255)
The range of representation for a signed integer

is:
-2n-1 2n-1-1
Where n is the number of
bits
An 8-bit signed number can represent numbers in the
range -27 27-1 (-128 127)
Dr. Bassel Soudan &

Dr. Ali El-Moursy
31
Integer Data Types
Binary Coded Decimal (BCD)

The individual digits of the decimal number are represented
by 4 bits each.
For example:
1234 is represented as 0001 0010 0011 0100
If each digit is stored separately, the number is called

unpacked.
If all the digits are stored together, the number is called
packed.
Given that each BCD digit represents a decimal digit,

then BCD digits are limited to the range of 0 9.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
32
BCD Representation
The value in location 10001 may

be an unpacked BCD
representation for the value 8d and
the value in location 10002 may be
an unpacked BCD representation
for the value 9d.
10004
89
10003
10002
09
10001
08
10000
The value in location 10004 may be a packed

BCD representation for the value 89d.
We say may because the meaning of any data depends on how

it is used. It depends on the meaning the user assigns to it.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
33
Meanings of Data
10004
89H
10003
B3H
10002
29H
10001
08H
10000
It cannot be BCD as the 2nd digit is > 9.
It might be the value 31 (unsigned) or +31 (signed).
1FH
What are the possible meanings

for the value found in memory
location 10000?
What about the other values?
Dr. Bassel Soudan &

Dr. Ali El-Moursy
34
Information types in Computer system
According to the discussion we can identify three

types of information presented in the computer
storage (Main memory or MPU registers) all
stored in binary (bytes): Instructions: to be decoded and executed by the
ALU of the MPU
Addresses: Main Memory addresses for both data
and instructions
Data/numbers: to be processed by the MPU
according to the operation of each instruction
Dr. Bassel Soudan &

Dr. Ali El-Moursy
35
Dedicated, Reserved, and General use Memory
Some ranges of memory

locations are reserved for
specific uses by the
processor and other areas
are dedicated to specific
uses by the operating
system.
The rest of memory is open
to the general use of the
programmer.
FFFFFH
FFFFCH
FFFFBH
FFFEFH
Reserved
Dedicated
General Use
Memory Space
0007FH
Reserved
00014H
00013H
00000H
Dedicated
Dr. Bassel Soudan &

Dr. Ali El-Moursy
36
Instruction Pointer (IP)
The IP register is 16 bits long.

The job of the IP is to always point to the memory location
where the next instruction to be executed is.
Memory
Another way of looking at it is:

the processor will fetch the instruction at the memory location
whose address is in IP next.
In reality it contains the offset of

the next instruction within the
current code segment.
Processor
IP
Next Instruction
The physical address of the next

instruction is CS:IP.
Current Code
Segment
CS
IP is typically incremented by 2
after reading the current instruction.
Why?
Another name for this register is Program Counter (PC).
Dr. Bassel Soudan &

Dr. Ali El-Moursy
37
The Data Registers
Four 16-bit general purpose registers

Or, eight 8-bit GPRs.
Used for temporary storage of data while in use.

Each register also has a secondary Special
Use.
Will look at the special uses later.
AX
AH
AL
BX
BH
BL
CX
CH
CL
DX
DH
DL
}
}
}
}
Accumulator
Base Register
Count Register
Data Register
Dr. Bassel Soudan &

Dr. Ali El-Moursy
38
Pointer and Index Registers
The 8088/8086 has two pointer registers (SP and

BP) and two index registers (SI and DI).
Each of them is 16-bits wide.
SP (Stack Pointer) and BP (Base Pointer) store

an offset relative to the SS (Stack Segment)
register.
SI (Source Index) and DI (Destination Index)

store an offset relative to the DS (Data Segment)
and ES (Extra Segment) registers.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
39
Stack Pointer and Base Pointer
Stores the offset of the current value of stack

segment during the execution of instruction that
involves the Stack Segment of memory.
Combine with the stack segment register (SS) to
produce the memory address.
(SS:SP) results in a 20 bit address that points to
the top of the stack (TOS).
BP also represents an offset relative to SS
register.
BP may reference parameters that were passed
to a subroutine using stack.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
40
The Stack
An area of memory used for storing information

in a LIFO manner.
Memory
User definable by setting the value in the SS

register.
Stack Segment
SP
Stack
Grows backwards into memory.
Growth
The stack length in 8088/8086

cannot exceed 64K.
Processor
Top
SS
Starts from the highest address

in the segment and grows
backwards.
End
SS:SP Top of the stack

Should start by setting SP to FFFFH to point to
the bottom of the stack.
SS:FFFFH is the bottom of the stack.
SS:0000H is the end of the stack.
Bottom
Dr. Bassel Soudan &

Dr. Ali El-Moursy
41
The Stack
Can be used to temporarily store a registers

contents if the register is needed for something
else.
Should only be accessed using special
instructions that store and retrieve information
from it in a LIFO manner.
PUSH SI stores the contents of register SI at the top of
the stack.
POP SI retrieves the value at the top of the stack to
register SI.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
42
Stack Instructions
PUSH AX
Decrement SP by 2
This moves the top of the stack (TOS) pointer 2 memory
location higher than the current location.
Store the contents of AX at TOS

AX is 16 bits. Therefore, it will need 2 memory locations.
POP AX
Copy the contents of TOS to AX.
AX is 16 bits. Therefore, the contents of 2 memory
locations will be copied.
Increment SP by 2.
Move the TOS pointer below the value that has just been
poped.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
43
Stack Instructions PUSH AX
AX
00
BA
50
06
32
1050B
01H
1050A
12H
10509
3BH
10508
B5H
10507
A2H
10506
29H
10506
10505
FEH
10505
10504
32H
10504
10503
4DH
10503
10502
00H
10501
12H
10501
10500
56H
10500
Before
SS
1050B
1050A
Stack
SP
10
SP
10509
10508
AX
Junk
SS
10507
10502
After
By the way the stack segment in this example is close to filling up.
Dr. Bassel Soudan &
Dr. Ali El-Moursy
44
Stack Instructions POP AX
AX
00
BA
50
06
32
1050B
01H
1050A
12H
10509
3BH
10508
B5H
10507
A2H
10506
29H
10506
10505
FEH
10505
10504
32H
10504
10503
4DH
10503
10502
00H
10501
12H
10501
10500
56H
10500
Before
SS
1050B
1050A
Stack
SP
10
SP
10509
10508
AX
Junk
SS
10507
10502
After
Dr. Bassel Soudan &
Dr. Ali El-Moursy
45
The Stack and Function Calls
The stack will be used automatically during

function calls.
A function call will automatically store the contents
of the CS and IP registers on the stack.
The return instruction at the end of the function will
retrieve the values from the top of the stack and
place them back into CS and IP.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
46
Source and Destination Index Registers
Used to hold offset addresses for instructions

that access data stored in the DS & ES by
combining SI and DS & ES
SI hold the offset address of the source.
DI hold the offset address of the destination.
Allow quick access to two indexed structures in

memory.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
47
The Status Register
A 16 bit register to hold indicator bits. Not all bits are used.
11
10
OF
DF
IF
TF
SF
ZF
AF
PF
CF
Carry Flag
Parity Flag
Auxiliary Carry
Zero
Sign Flag
Trap Flag
Interrupt Enable
Direction Flag
Overflow Flag
Dr. Bassel Soudan &

Dr. Ali El-Moursy
48
The Status Register
Carry Flag
The bit is set to 1 if the previous operation resulted in a carry out or
borrow in.
Parity Flag
The bit is set to 1 if the previous operation resulted in a value that
has even Parity
Auxiliary Carry
The bit is set to 1 if the previous operation resulted in a carry out
from low nibble to high nibble
Zero Flag
Set to 1 if the previous operation resulted in a zero result.
Otherwise the bit is set to 0.
Sign Flag
Set to 1 if the previous operation resulted in a negative numbers.
Overflow
Set to 1 if the previous operation resulted in a signed value that is
out of range.
Dr. Bassel Soudan &

Dr. Ali El-Moursy
49
Review
Each Segment Register
points to the starting
address of a particular
segment of memory
FFFFFH
Code Segment
(64Kbytes)
CS
DS
SS
Data Segment
(64Kbytes)
ES
Stack Segment
(64Kbytes)
Extra Segment
(64Kbytes)
00000H
Dr. Bassel Soudan &

Dr. Ali El-Moursy
50
The 8086/8088 registers

15
Instruction Pointer
IP
CS
DS
Segment Registers
SS
ES
Data Registers
AH
AL
AX
BH
BL
BX
CH
CL
CX
DH
DL
DX
SP
Index & Pointer

Registers
BP
SI
DI
Status Register
Code Segment
Data Segment
Stack Segment
Extra Segment
Accumulator
Base Register
Counter
Data Register
Stack Pointer
Base Pointer
Source Index
Destination Index
SR
Dr. Bassel Soudan &

Dr. Ali El-Moursy
51

4 Bits 16 bits (BP, BX, SI, DI, IP)
0000
Offset Register
16 Bits (CS,DS, SS, ES) 4 Bits
Segment Register
0000
20 bit adder
20 bit address
Dr. Bassel Soudan &

Dr. Ali El-Moursy
52

Microprocessor Architecture and Assembly Language

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Chapter 2

Processors & Assembly Language

Dr. Bassel Soudan &

Where in history are we?

1st Microprocessor chip 1971

16K Memory 1972

64K Memory 1974

1 MB Memory 1st IBM PC

Introduced Protected Mode

1st processor with built in floating point unit

Processors & Assembly Language

Dr. Bassel Soudan &

Processors & Assembly Language

Dr. Bassel Soudan &

The 8086/8088 Architecture

The 8086 uses three busses to perform its

When the 8086 wants to access a memory

Processors & Assembly Language

Dr. Bassel Soudan &

The Address Bus

20 bits wide (A0 A1A19)

Processors & Assembly Language

Dr. Bassel Soudan &

The Data Bus

16 bits wide (D0 D1D15) for the 8086 and 8 bits

Since the data bus is 16-bits wide, then the 8086

Processors & Assembly Language

Dr. Bassel Soudan &

The Control Bus

There is no real control bus. Instead, the control

Processors & Assembly Language

Dr. Bassel Soudan &

The 8086/8088 can generate a 16-bit I/O device

Communication with each I/O device uses the

Processors & Assembly Language

Dr. Bassel Soudan &

Software Model of the 8088/8086 MPU

8088/8086 have thirteen 16-Bit Registers:

Four Data Registers (AX, BX, CX, DX)

Two Pointer Register (BP, SP)

Two Index Register (SI, DI)

Four Segment Register (CS, DS, SS, ES)

8088/8086 have one 9-bit Register:

Processors & Assembly Language

Dr. Bassel Soudan &

The 8086/8088 registers

Index & Pointer

Dr. Bassel Soudan &

The 8086/8088 and Memory

The 8086/8088 have a memory address space of

The 8086/8088 has a segmented view of

Processors & Assembly Language

Dr. Bassel Soudan &

Segment order within memory

Processors & Assembly Language

Dr. Bassel Soudan &

Segment Registers & Memory Segments

The 8086/8088 has 1 Mega byte address Space.

Processors & Assembly Language

Dr. Bassel Soudan &

Segment Registers & Memory Segments

The CS, SS, DS, ES registers contain a 16 bit

4 segments gives a total of 256 Kbytes of active