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Design
ECEN4827/5827 Analog IC Design
October 19, 2007
Art Zirger, National Semiconductor
303-845-4024
art.zirger@nsc.com
Where to start?
How do we choose what transistor sizes to
use in a design?
One topic not often discussed in classes is
random offset and how transistor sizing
affects this phenomenon.
Introduction
2 devices (MOSFETs, resistors,
capacitors) of the same size, laid out next
to each other, are not identical.
How they differ is generally the function of
random offsets during processing.
These offsets vary from chip to chip and
set a limit on precision attainable which is
typically reflected as data sheet
specifications.
Misc. Definitions/Notation
The following I-V equation for a MOSFET
in saturation is used:
W
I = (V V ) where = C
2
L
2
GS
ox
Agenda
Systematic vs. random offset
Sources & profiles of random offset
Current Mirror/Diff Pair offset derivation &
insights
Propagation of uncertainties math
Current Mirror/Diff Pair exercises
Random
Mismatch in the circuit because of wafer processing
Different chips will have different values, but the value will mostly
remain the same (subject to temperature shifts, drift, etc.)
Each copy of the circuit should share this; calculable based on
the statistical values of element parameters
Viewable using DCmatch and Monte Carlo simulations
This is what is usually thought of as matching
Mismatch parameters
Commonly investigated mismatch
parameters:
MOSFET
(resistivity)
Capacitors
mean:
standard deviation: a
variance: 2a
Mismatch is defined as occurring between
elements; a single element does not have
mismatch, but a self mismatch can be
defined.
V =
t
AVt
WL
A fab will create test structures and measure Vt multiple times per wafer for
various sizes of transistors and collect ongoing statistics to monitor the process
over time.
From W. Sansen showing how the mismatch constant, AVT, varies roughly linearly with
process size (doping concentration affects linearity of the relationship). Also, for p
substrates, the PMOS will have AVT ~ 1.5*AVT NMOS.
WL
Offset Derivation
Given the behavior of sufficiently
uncorrelated parameters, want to know the
effect of those parameters on 2 common
circuits:
Current mirror
Differential pair
f = x + y + z + ...
z
x
y
I D =
(V
VT )
gs
g m = 2 I D
I D
=
ID
, V gs , VT variables
1
(Vgs VT )2 VT 2(Vgs VT ) + Vgs 2(Vgs VT )
2
2
2
1
(Vgs VT )2 VT 2(Vgs VT )
2
2
(Vgs VT )2
(Vgs VT )2
2
2
2I D
or
V gs VT
I D
VT 2
=
ID
(V gs VT )
I D g m
=
VT
ID
ID
(V
VT )
gs
g m = 2 I D
2I D
or
V gs VT
1
(Vgs VT )2 VT 2(Vgs VT ) + Vgs 2(Vgs VT )
2
2
2
Constant current so I D = 0
, V gs , VT
I D =
Divide by
0=
2(Vgs VT )
1
(Vgs VT )2
2
VT + Vgs
2(Vgs VT )
2
Vgs =
(Vgs VT )
+ VT
Vgs =
I D
+ VT
gm
Vgs =
I D
+ VT
gm
Current Mirror:
I D g m
=
VT
ID
ID
I D
Vgs =
+ VT
gm
I D g m
=
VT
ID
ID
(I D )
ID
( )
gm
+ (VT )
ID
( ) I D
+ ( (VT ))2
(Vgs ) =
gm
2
Statistics Math
You need to know how to propagate
uncertainties to get the most out of this
material.
General form to propagate uncertainties
for uncorrelated variables:
f
=
i =1 v i
2
z
2
vi
z = f(x,y,z)
( n = # of variables )
2
f
f
= x + y + ...
x y
2
z
= x +
f
x y
2
Vt = Vt1 Vt 2
V =
t
2
Vt 1
= 2
2
Vt
AVt
WL
or
t 1, 2
AVt
2 WL
2
2
y
2
z2 = ( xy ) x +
x y
2
x y
+ 2
y
2
2
x x y
2
z = +
y x y
x
=
y
2
z
1x
1x
50x
Ratios: 1:1:1:50
Problem: Design 1:1 to required accuracy (1%), for Id=1A
Procedure: Calculate self-mismatch and utilize statistics.
PMOS: pCox=23A/m, Id = 1A
(I D )
ID
( ) g m
+ (VT )
=
ID
(I D )
Id
ID
gm
(VT )
ID
1% .01
=
2
2
AVt
2 p Cox W
gm
2
Vt1&
=
=
=
,2
2 WL
Id
Id
Id
L
(I d )self
AVt
AV p Cox 23mV
2 p Cox W
=
= t
=
Id
Id
L 2 WL
L
Id
L
(I d )self
23A
1A
.110
Note: no dependence on W, only L!!
Id
L
.01 .110
=
L = 15.6
Use W/L=2u/16u
L
2
=
1x
1x
50x
AVt
WL
16mVm
= 5.06mV
20 m * 0.5m
gs
= 5.07mV
.02 m
( ) g m
+ (VT ) =
=
ID
2 m * 4 m
2
7.32 A
V
+
2.5A
Vgs =
23mVm
= .025
2 m * 4 m
(5.07mV )2 + (1.12mV )2
input pair
= 5.19mV
current mirror
Summary Points
Current mirror accuracy is improved with low W/L ratios
costly:
WL
CAD tool analyses such as DCmatch and Monte Carlo are
a useful tools for getting insight into sources of mismatch
(expected and unexpected)
References
Layout:
The Art of Analog Layout, Alan Hastings
General Information:
Analog Design Essentials, W. C. Sansen
1x
1x
50x
y
= + =
f
x y
x
(.001)2 + (.00707)2
= .00714 = .7%
Answers:
(1): Any error in the mean is not statistical; the source of the
difference in the means is coming from the design and it turns out to
be channel length modulation since the input to the mirrors drain is
near Vdd and the output to the mirrors drains are near Ground.
(2): Even though the 50x mirror transistors all share the same
length, they dont share the same self-mismatch fractional error. If
) portion (
.001)the
+ (.00707
you look (at
r.s.s
), you can see how the
largest error dominates the sum. The fractional error of the 50x is
actually quite low, so the combination approaches the self-mismatch
fractional error of the input transistor or 1%/sqrt(2) = .71%.
Remember that for any fractional error combinations
2
= 3.3e 3
!!
Which doesnt match up well to the 12.3mV reported in the listing. But, we havent
considered W and L to modify the width/length of the transistor. This transistor is
a minimum length transistor, so it turns out that has quite an effect. After using
Leff = L 2Lint, and recomputing we find: 3 (V ) = 12.3e 3
You can also see the gain reflection to the input for M3/M4.
th self
(.35%)2 + (.95%)2
1.01%
(I
(I
)
)
+
=
+
=
f
x
x
d _ self _ 50 x
I d _ 50 x
d _ self _ 1 x
I d _1x
AVt
Vt _1x
W
Vt _ 50 x =
g m = 2Cox I d g m _ 50 x = 50 g m _1x Vt =
2 WL
50
L
(I D _ self _ 50 x )
I D _ 50 x
g m _ 50 x
I D _ 50 x
2
(Vt _ self _ 50 x ) =
2
1 1% 1%
=
+
=
f
50 2 2
(.001)2 + (.00714)2
50
I d _ 50 x = 50 I d _ 1x
(I D _ self _1x )
50 I D _1x