A HANDS-ON-TRAINING EXPERIENCE

IN
VLSI DESIGN
26th 30th December 2011

USER GUIDE FOR XILINX

A Complete Process Flow for a Full Adder Using
VHDL and Dumping It into A Sparten 3E Board

A Hands-on-training Experience in VLSI Design

Getting Started with Xilinx software and writing a VHDL code for Full adder
checking its syntax, simulation and viewing RTL Schematic
Close the previous project if anything is open earlier

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Open a new project

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Give the project name and project location

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The parameters (Family, Device, package and speed) are to be set here depending on the
parameters of the FPGA kit to which you want to burn the program. If you dont want to
burn any FPGA kit you can leave it as it is.

Press next button

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Click on new source

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Select VHDL module and give File name.

Press next

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Give the port names. Specify whether it is a in or out port. Click on bus if a port is a
multi-bit one. Give the MSB & LSB. For Ex. If we take a 4 bit input, select on the bus &
give MSB =3 & LSB = 0

Press next

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Check here about the pins you added are correct or not else back it and reassign the pins

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After clicking finish button in the last step one fa.vhd file will be created. Open the
fa.vhd tab

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Write the program in between the begin & end Behavioral block

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Click on the plus sign near Synthesize XST (red circled)

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Double click on check syntax

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The syntax was checked successfully, if it fails then check for syntax

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To see the RTL click on View RTL Schematics

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Double click inside the module (green box) to see what are there inside it. Double click
outside the box to come to upper level

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Now for simulation we have to add a test bench files as bellow

Open the source tab. Because in the previous step the Design tab was opened.

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Select the combinational clock as bellow

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Give the values of a, b and c which are to be added

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Change to behavioral simulation

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Click on the plus sign near fatest inside the red circle

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Select the fatest.tbw file

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Click on the process tab

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Double click on Simulate Behavioral Model

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See the output result and check it correctness

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Steps to dump the code into a FPGA kit

Right-click on the fa.vhd file click on new source

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Select Implementation Constraint File

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Give the name of the Implementation Constraint File. This will come in the .ucf format

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Finish it.

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Change to Synthesis Implementation.

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You should confirm that the .ucf file is coming under the .vhd file. If it has not come just
refresh it by pressing F5 key. Otherwise add the .ucf file once again.

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Click on the .ucf file

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Select the process tab

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Open the user constraints. And double click on Edit constraint(Text)

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You have to write the .ucf file in here.

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The program written above indicates that the port a is mapped to P71 location of the kit.
(p71 location of the kit means the address of one input switch. This address you can get
from the manual given with the kit.) similarly the other ports are linked to the other
location of the kit.

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Right click on the top module & changes its property to the property of the kit

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The properties are given the manual.

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Click on the .vhd file. Then double click on the implementation Design

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Double click on Generate Programming File

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Cancel the massage window

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Connect the FPGA kit to the PC.

Double click on Configure device

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Finish it.

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Select the fa.bit file and press open button

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Cancel it

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Right click on the fa.bit file & program it

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Press ok

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Programming is going on

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Programming is done successfully

Check the output now in the FPGA kit

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1. Vhdl code for counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end Behavioral;
2. Vhdl Code For Prbs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
--library UNISIM;
--use UNISIM.VComponents.all;
entity prbs is
Port ( CLK : in std_logic;
RSTn : in std_logic;
data_out : out std_logic_vector(15 downto 0));
end prbs;
architecture Behavioral of prbs is
component dff
Port ( CLK : in std_logic;
RSTn : in std_logic;

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D : in std_logic;
Q : out std_logic);
end component;
signal data_reg : std_logic_vector(15 downto 0);
signal tap_data : std_logic;
begin
process(CLK)
begin
tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor data_reg(15));
end process;
stage0: dff port map(CLK, RSTn, tap_data, data_reg(0));
g0:for i in 0 to 14 generate
stageN: dff port map(CLK, RSTn, data_reg(i), data_reg(i+1));
end generate;
data_out <= data_reg after 3 ns;
end Behavioral;
3. Vhdl Code For D-Flip Flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
--library UNISIM;
--use UNISIM.VComponents.all;
entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;

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4. Vhdl Code For Accumulaor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity accu is
generic (accuWidth : natural := 4);
Port (clk : in STD_LOGIC;
rst : in STD_LOGIC;
accuEn : in STD_LOGIC;-- enable
accu_in : in STD_LOGIC_VECTOR (accuWidth-1 downto 0);
accu_out : out STD_LOGIC_VECTOR (accuWidth-1 downto 0));
end accu;
architecture Behavioral of accu is
begin
process (rst, clk)
-- note that we can have a bit vector for a variable
variable accu_v : STD_LOGIC_VECTOR (accuWidth-1 downto 0);
begin
-- async reset
if rst = '1' then
-- initialize the output and the variable to "0..."
accu_out <= (others=>'0');
accu_v := (others=>'0');
elsif clk'event and clk = '1' then
if accuEn = '1' then
accu_v := accu_v + accu_in;
end if;
end if;
accu_out <= accu_v;
end process;
end Behavioral;

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