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A.
-re
204
-1
For VDD = 5 V the ideal noise margins are 2.5 V;that is, NM, = NM, = VDDf2..
Example 11.2
WI
w2
B.=$P=KP,,-=KP
LI
PL2
KP, = 3KP,, the width of the pchannel transistor must be three times the
of the n-chanael, assuming equal-length MOSPETs. For V, = 2.5 V , this
wz = 3w,
tching Characteristics
inverter can be genecdized by examining the parasitic
sociated with the inverter. Consider the invertw.shown
1tP equivalent digital model. Although the model is shown with both
in practice one of the switches is closed, lieepinp the output conoectsd to
Notice that the effective input capacitance of the inverter is
Flpre 11A Transfer chara*cristics of the inverter showing the s ~ i
cfa= 3
+cod = chn + cn
ip
(11.5)
11 The Inverter
207
the
Input
gtbdnin
pulse rseding
c
athrough
~
a
I.
tpg~
=
.,I,
'
3-
I.
(11.10)
208
Example 11.6
Estimate and simulate the propagation delay of a minimum-size inverter dri
a 100 fF capacitor.
11 The Inverter
The schematic of the minimum-size inverter driving a 100 fF load and the l
d
symbol of the inverter are shown in Rg. 11.8. The sizes adjacent to the in1
correspond to the ratio of the pchannel width to the n-channel width, assu
the lengths of the MOSFETs are the.same size. Usually, the lengths m
minimum size available, which for CN20 is 2 pun. The total capacitance,
on the output of the inverter is the sum of C,, the load capacitance am
interconnecting capacitance. In this case C, = 109.6 fF, assumin
=B
interconnecting capacitance. The propagation delay time8 arc then tPHL
and tpM= 2.63 ns. This can be compared to the simulation results of fig. 111
ered. If R,, = R,, ,the delay time8 are equal. This is equivalent to making W, =
ch was the same requirement used in the previous section for making V, =
The Ring O~ollfator
number of inverters of the circuit shown in Fig. 11.10 fams a closed loop with
feedback and is called a ring oscillator. The willation fnquency is given by
1
fm=
(11.11)
n . (tm+~PLH)
the inveTters are identical and n is the number (odd) of inverters in the ring
. Since the ring oscillator is self-starting, it is often added to a test portion of a
cw
Cm, = 2C,
=2pn.3pm.C&,sothat
Figure 11.8 Inverter driving a 100 t
T load capacitsllcein Ex. 11.6.
6.OV.
c,
+ 3C,
= 5Cm
Ca.2 = 3C,1
4.0V.
cam
2.0v.
C, = 4C,
(11.14)
c.
+ 6c,
= lOC,
0v.-
-2.ov.
. .
ens 1on
~(voutf V(2)
1ms
16na
14-
1811s
Time
11 The Inverter
211
haracterize the speed of a digital process, a tenn called the power delay
P) is often used The PDP, measured in joules, is detined by
PDP= P ,
.(tm+t m )
(11.19)
terms can be detamined from the ring oscillator circuit of the previous section.
frequently used to compare different tectechogica or device sizss, for
have a lower propagation delay, the pow= dissipation may be larger
.--dynamic
capacitance on the output of any inverter is the sum of its own output
ce and the input capacitance of the next (Identical) stage. This is given
C,=C.,+C*=80E
11 The Inverter
213
5ns
0s
v(2)
1Ons
15ns
2011s
25
Time
Figure 11.12 SPICE simulation of the five-stage ring oscillator of Ex. 11.7.
1 and RW2 represent the effects of the resistance of the n-well, and
1 and RS2 represent the resistance of the substrate. The capacitors C1 and
t the drain implant depletion capacitance, that is, the capacitance between
of the transistors and the source and substrate. The parasitic circuit resulting
inverter layout is shown in Fig. 11.15.
output of the inverter switches fast enough, the pulse fed through C2 (for
g inputs) can cause the base-ernitter junction of 4 2 to become forward
s then causes the current through RW2 and RW1 to increase, causing Q1 to
en Q1 is turned on, the current through RS1 and RS2 increases, causing
n harder. This positive feedback will eventually cause Q2 and Q1 to turn
and remain that way until the power is removed and reapplied. A similar
can be made for negativegoing inputs feeding through C1.
a1 techniques reduce the latch-up problem. The first technique is to slow
falltimes of the logic gates, reducing the amount of signal fed through C1
=@educing the areas of M1 find M2's drains lowers the size of the depletion
d the amount of signal fed through. Probably the best meiod of
up effects is to reduce the parasitic resistances RW1 and RS2. If these
zero, Q1 and 4 2 never turn on. The value of these resistances, as seen
216
when driving off-chip loads. Consider the inverter string driving a load
labeled C,, and shown in Fig. 11.17. If a single inverter were to drive Cw ,
times would be
~PHL
If, moving toward the load, cascading N inverters are used, each inverter
previous by a factor A (that is, the width of each MOSFET is multip
minimum delay can be obtained as long as A and N are picked
inverter's input capacitance is also larger than the previous inverter's
by a factor of A. If the load capacitance is q u d to the input capacitance of
inverter multiplied' by A, then
Input C of final in-
where C,,, is the input capacitance of the fmt inverter. Rearranging Eq.(11.20
.(ACwI +AZ
acuaMwdd.y
where R,, and R,, are the effective resistances of the first inverter and
capacitance of the first inverter. As the inverters are increased in 8
capacitances, both input and output, increase by A while their resistances
factor A. The equation ( 1 1.23) can be written as
N
( t p +~~PLH)~,,,,
~
=
(Rnl+RP~)(Cwrl
+ A c i d ) E N(R-I +Rpt)(Coutl+ A C d
b l
'
Consider this as if the load capacitance were simulating the input capacitance of
inverter (if there was another invertn).
term in this equation is the intrinsic delay of the fust inverter in our cascade of
If we assume that this delay is small, solving thjs equation for Ngives
N=ln- clod
chl
( 1 1.27)
Designing a buffer begins with determining C,,. For the present case
28.8 fE The number of inverter6 using Bq. (1 1.27) is
ple 11.9
w
u
mdelay was 10.4 ns in Ex. 113.)
tm t m = 3(16k)(19.2 81+8.86.28.8
tT)= 13.2 ns
b e and efi
btly
it takes to lay out the large MOSFETs used in an output buffer can
using cell hienuthy. As a simple example, let's lay out a 25Qn
77n
++-hzopp
n
Input
The Inverter
Output
Flwn
- 11.U) Buffer design of Ex. 11.9.
. . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. . .
..................
...................
...................
...........
...........
Dt . . . . . . . . .
. . . . . . . . . . .
...........
...........
.............
. . . . . . . . . . .
.............
...........
...........
...........
. . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
........
........
........
........
...........
...........
...........
...........
...........
...........
...........
...........
. . . . . . . . . .
...........
...........
...........
. . . . . . . . . . .
...........
. . . . . . . . . . .
..................
.............
.............
. . . . , . . . . . . . . .,
.............
.............
.......
.........
.............
.............
.............
. . . . . . . . . . . . .
.............
.............
.............
.............
.............
.............
...................
MOSR
rank of
(1 1.28)
the circuit shown in Fig. 11.24b with 13 invuters. Again, assuming all
same size, the delay from the input to the output is
CMOS
-
J U U L LCi
using a
224
11 The Invmer
225
VDD-
put drivers
sic "NMOS
mdM3are
the
=....
-- h~rffer
V,,,,,, assuming the inp~.
It
--
--"-.
-..--- --- -.DC voltage of nominally VDD + 2 V . This allows the out~utsienal to reachP
".-".a.
- out
(*)
@)
I=
FbPre 11.28
VDD
*
S
Figure 11.29 Circuits and lc@c symbol f
a the the-state inwter.
W o n nsults are shown in fig. 11.32. Notice how the output doesn't go
ay to ground ot VDD. We can decrease the size (WIL)of M2 (increase
229
eat Ex. 11.6 for MOSFETs with W = 10 pn and a load capacitance of 1pF.
nimum-size inverters.
out the standard-cell frame of Fig. 11.16. Explain how the added implants
t Ex. 11.9, using a minimum delay of 20 ns, where the first inverter in the
Chapter
Logic Gates
er we discuss the DC characteristics, dynamic behavior, and layout of
logic gates. Static logic means that the output of the gate is always a
tion of thc inputs and always available on the outputs of the gate regardless
e begin with the NAND and NOR gates.
. Let's begin our analysis by determining the voltage transfer curve of a gate
'determine the gate switching point voltage, V, ,we must remember that two
in parallel behave like a single MOSFET with a width equal to the sum of
widths. For the two parallel pchannel MOSFETs in Kg. 12.1, we can
w3+w,=2wp
(12.1)
83+84=2pp
(12.2)
233
Transeonductancc ratio of NAND gate =
B.
-
4 8 ~
(12.5)
switching point voltage, with the help of 4.(11.4). of the two-input NAND gate is
it should be remembered that we have neglected the body effect (an increase in
hold voltage with increasing V A . Voltage transfer curves using one input,
othas tied to VDD, will give slightly diffacnt results becauseof this effect.
VSP=
The SPICE simulation results are shown in Fig. 12.3. The simulatio
Vspof approximately 3.1 V. W
Yin
11
.O
0.5
1.0
1.S
2.0
2.5
3.0
ug
12.18 D C C h a r a c t s r l ~ d t h . N O R ~
3.8
4.0
237
+0.35.R.Ch(N-1)2
(1213)
part n ~
238
O Digital
S
itance is much greater than the output capacitance of the gate,the low to high
n time can be estimated by
?~LH'
RP
-. cld
(12.16)
In
Rp=24LnaodCow=4.8fF
a low-to-high propagation time. using Eq. (12.15). with C, = 0, of
Flpm 12.7 Serb d
of 100 fP, the propagation delays become, t,, = 928 ps and t,,, =
PICE simulation results are shown in Fig. 12.9 followed by the
Helping with convergmce. the .OFTIONS statement was used,
at 0.1 ns instead of the UlllCaliStic conditions of 1 ps.
m n CMOS Digital
240
10
$0
N Ra. C w
(12.19)
when the output of the NAND gate changes from a low to a high is
nt then the high-to-low case. Refening to Fig. 12.6, we see that if one
s turns on, it can pull the output to VDD independent of the number of
in parallel. Under these circumstarres, Eq. (12.16) can be used with N = 1
the low-to-high delay-time, or for a parallel connection of N p-channel
tpm.
20
10
00
-1 0
I""
tm-R..Cw
(12.20)
MI
M2
M3
M4
M5
MB
v1
V2
501001
5120CMOSNBGhlW.SumPSJdpPWP8Q(U
2 1 4 0 CMOSNB M u w - 3 ~AD=sBp Ak36p P W UPS-24
41OOCMWBIBuW~ASP9BpPL)Sa4uP~
~ ~ V W V ~ ~ ~ B L = ~ U W ~ U A D J B P ~ P W C ~ ~
51VddVddCMOSPBG2uW*ADJBPA&38pmfi
5 1 V d d V d d C M O S P B L b U W 9 u ~ ~ ~
vddo DC5
10
DCO PULSE(O55n .In .In Ion)
mnSpioemodeloandmaeromdels"'"
MODEL CMOSNB NMOS LEV+VFBPB.T91)20EOl, LVFBc3.6745BEOl,WVF&4.7234aE-02
s e 8 m m i I i x A f w a ~ ~
oaing Eqs. (12.19) and (12.20). the propagation delays for the
R minimum-sizeNAND gate, with only m e input switching driving a
itancc. Compare your results to SPICE.
= 3.8k 1 0 W 2.4ns
~PHL
242
As the number of inputs. N,to a static NAND (or NOR) gate increases,
shown in F4g. 12.2 (Fig. 12.4) becomes difficult to realize. Consider a NO
100 inputs. This gate requires 100 p-chrnncl MOSFETs in series and a
MOSFETs (2N MOSFETs). The delay associated with the series pchanae
charging of a load capacitance is too long for most p a c t i d situations.
VDD
VDD
%4!
h ~ g i cimplement
,
the following logic functions:
r
ntrmbm &
Z. = ~ + B C and
Z=A+&+CD
245
the
The implementation of the first function is shown in Fig. 12.13a. Notice that
we
p-channel configuration is the dual of the n-channel circuit. The function
:r is
obtain is the complement of the desired function, and therefore an inverte
and
used to obtain Z. Using an inverter is, in general, undesirable if both true
a to
complements of the input variables are available. Applying Boolean algebr
the logic function, we obtain
=_.
z=;~+Bc*Z=A+BC=A.(E+Q
*Z=A.(E+G
the
The A01 implementation of the result is shown in Fig. 12.13b. Logically.
.13b
circuits of Figs. 12.13a and b are equivalent. However, the circuit of Fig. 12mce
is simpler and thus more desirable. Note that to reduce the output capacit;
Z=A+BC+CD=A+C(B+D)~Z=A+C(E+D)=A.(~+B~)
or
z=~.(?+E@
The logic implementation is given in Fig. 12.14.
VDD
VDD
Example 12.6
UcV
A01 logic, implement an exclusive OR gate (XOR).
lopic symbol and truth table for an XOR gate are shown in Fig, 12.15
Frnrn the truth table. the l p i c function for the XOR gate is given by
and finally
-
(12.23)
carry-in
247
.;"j.
+I.
Cany-out
Full adder
sn
Sumat
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1
1
0
1
0
0
0
I
0
I
1 1 0
I 1 1
0
1
1
1
The logic expression for the sum can be rewritten as a sum of products
s. = A.B,c.
+Z.B,?,
+A.B,F.+A,B.c,
nr since
VDD
Cxcode voltage switch logic (CVSL) or differential cascode voltage switch logic
IDVSL) is a differential output logic that uses positive feedback to speed up the
'";itching times (in some cases). Figure 12.19 shows the basic idea. A gate
CrW-connected load is used instead of using p-channel switches, as in the A01 logic, to
Pllll the output high. Consider the implementation of z = ~ + B c . (This logic function
"as "plemented in A 0 1 in Fig. 12.13.) N-channel MOSFETs are used to implement Z
as shown in Fig. 12.20. Figure 12.21a shows the implementation of a two-input
X o R m gate
~ ~ using
~
CSVL, while Fig. 12.21b shows a CSVL three-input
X O R I Xgate
~ ~useful
~ in adder design.
split-level logic (DSL logic) is a scheme wherein the load is used to reduce
swing and thus lower gate delays (at the cost of smaller noise margins).
'llc
hasic idea is shown in Fig. 12.22. The reference voltage V,,,is set to VDD12 + V , ,
T h l r ha< the effect of limiting the output voltage swing to a maximum of VDD and a
of VDDI2. The main drawback of this logic implementation is the increased
P[I!v,-~ djcalpation
.
resulting from the continuous power draw through the output leg at a
nf L'DD12. The output leg at VDD draws no DC power.
''"'pllt
'
248
249
VDD
0
Q
Output
Inputs
block
&
block
*
VDD
Output
250
25 1
252
253
PROBLEMS
A final example of a static logic gate, a tri-state buffer, is shown in Fig. 12.23. When
the Enable input is high, the NAND and NOR gates invert and pass A (VDD or ground)
to the gates of MI and M2. Under these circumstances, M1 and M2 behave as an
inverter. The combination of M1 and M2 with the inversion NANDMOR gate causes
the output to he the same polarity as A. When Enable is low, the gate of MI is held at
ground and the gate of M2 is held at VDD. This turns both M1 and M2 off. Under
these circumstances, the output is said to be in the high-impedance or Hi-Z state. This
circuit is preferable to the inverter circuits of Fig. 11.29 because only one switch is in
series with the output to VDD or ground. An inverting buffer configuration is shown in
Fig. 12.24.
:sign, lay out, and simulate the operation of a CMOS AND gate with a V, of
proximately 1.5 V. Use the standard-cell frame discussed in Ch. 4 for the
'Out.
12.2
De:sign and simulate the operation of a CMOS A01 half adder circuit using
static logic gates.
peat Ex. 12.3 for a three-input NOR gate.
peat Ex. 12.4 for a three-input NOR gate.
:tch the schematic of an OR gate with 20 inputs. Comment on your design.
VDD
12.6
Enable1 -
h g i c symbol
REFERENCES
rSBN
[I]
M. I Elmasry, Digital MOS Integrated Circuits 11, IEEE Press, 19920-87942-275-0, IEEE order number: PC0269-1.
[21
[3]
Qhnii P M O S
Chapter
e TG and Flip-Flops
ssion gate (TC3) is used in digital CMOS circuit design to pass or not pass a
schematic and logic symbol of the transmission gate (TG)are shown in Fig.
up of the parallel connection of a p and an nchannel MOSFET.
when S (for select) is high we observe that the transmission gate
input to the output. The resistance between the input and the
estimated as RJIR, . We begin this chapter with a description of the nass transistor.
.d
Pass Transistor
single nchannel MOSFET shown in Fig. 13.2a. Assume that the voltage
itor (the output of the pass transistor) is initially 5 V. When the
f the MOSFET is taken to VDD,the MOSFET turns on. In this
assume that the drain of the MOSFET is connected to the load
at the source (the input of the pass transistor) is connected to ground,
the drain and source are interchangeable. The delay-time of the
is simply
256
Now consider Fig. 13.2b where the capacitor is initially at 0 V. In this case,
connected to VDD and the source is connected to the load capacitance.
substrate, assumed at VSS = ground, is not at the same potential as the
body effect present causing the threshold voltage to increase. What b q
MOSFET is raised to VDD, the load capacitor charges to VDD - V , wbm
Appendix A, is in the neighborhood of 1.5 V. llIaef~re,the low-to-hlO$!
can be estimated by
. '>,
tpm = RnClwdfor a high voltage of VDD - V ,
ib
SET. The
In this derivation, we have neglected the parasitic capacitances of the
following example illustrates the switching behavior of the n-channel pass tF(mistor.
and
'
7aSS
me1
800
or
passes logic lows well and the pchannel passes logic highs well,
lementary MOSFETs in parallel, as was shown in Fig. 13.1,
es both logic levels well. lXe CMOS TO requires two control
13.4). llIe propagation delay-times of the CMOS TG are
- C w for alow
~ P U I=lip
of the MOSFl3Ts
258
SPICE for the select lines, which can supply infinite current to charge the
capacitance of the TG,gives the designer a false sense that the delay through the
limited by R, and R, . Often, when simulating logic of any kind, the SPICE-g
control signals are sent through a chain of inverters so that the control sign;,
closely match what will actually control the logic on die.
the number of inputs (outputs) to the MUX (DEMUX) and m is the number
lines. A 4 to 1 MUXiDEMUX I8 shown in Fig. 13.10. Note Uu the MUX is
nal; that is, it can be used as a MUX a a DEMUX. Thc logic quarjon
the operation of the MUX is given by
= ~t p~= N.
~ (Rn IIRp)(Cload)+ 0.35 . (Rn IIRp)(Ctm C@)(N)
The first term in this equation is simply the sum of the TG effective resis
the second tern in the equation describes the RC transmission line effects.
A1
A2
A3
A A A
-t+
I.PU~
...
S
Figure 13.8 Path selector.
Out
Z=AS+BS
When the selector signal S is high. A is passed to the output while a low
to the output.
This same idea can be used to implement multiplexetsl$j
(MUXIDEMUX). Consider the block diagrams of a MUX and DEMUX 8
13.9. The number of control lines is related to the number of input lines &
Truth tabk
~ R Q Z ~
0 0 1
10 1
0 1 0
1 l Q
1
0
1
G
Truth table
S R
O O Q
10 1
01 0
1 1 0
Q ~
G
0
1
0
268
FF,consider the data or D FF shown in Fig. 13.18 with associated logic symbol.
the clock signal is high, the D input can pass directly to the SR FF. If D i
CLK is high, the output, Q,is a 1, while if D is low the output is a low.
any time while the CLK input is high, the output will follow. When
goes low, the current logic level of D is latched into the SR FF.
an edge-sensitive FF because the output changes at other times
time.
Edge-Triggered Flip-Flops
The JK master-slave FF,shown in Fig. 13.19, is an example of an edge-a31
When the CLK signal goes high, the master JK FF is enabled. Since ms'
cannot change states when CLK is high. the clock pulse width does not have
than the propagation delay of the FF. When CLK goes low, the mu*
transferred to the slave. If both J and K are low, the output of the mum
unchanged, and therefon so does the output of the slave. If J = 1 and K= 0
CLK pulse goes low, the master output, Q,goes high. When the CLK gool
high output of the master is transfemd to the slave. The master-slave JK A
just like the JK FF of the previous section except for the fact that the di
available until CLK goes low and then is no restriction on the pulse width
(ic., the FF is falling edge triggered). Adding reset or set capability to the
accomplished by adding logic gates between the NAND and the SR FF of
The logic gates simply enswe that the SR FF are placed into a certain I
application of a reset or set signal.
271
is to buffer the clock input through several inverters. This has the effect of
up the leading and trailing edges of a slow input pulse and presenting a lower
ance on the clock input to whatever is driving the FF. The main
is the increase in delay times, tpmand tpw (defined by clock to output), of
nerd, the FFs of Fig 13.20b and c should not be laid out without buffering
imum pulse width of the clock, set, or clear inputs is labeled t, . The
is determined by the delay through (refemng to Fig. 13.20) two NAND
The last timing definition we will consider here is the recovery time,
time between removing the set or clear inputs and a valid clock input. This
CLK
/ \
Figure 13.23 Clocktd D flip-flop using the basic latch and TCis.
The input DC
connected to each TG. In
effective digital resistances of the invcrters shod
TG
and the driver mistance.
- - resistance
-of whatever gate is driving the TG.)In
be lame. The length of the &vim used in the inverters can
minimum length to reduce the input CUTTCU~.
REFERENCES
. Klu
[I]
[2]
[3]
PROBLEMS
Unless otherwise stated, use the CNU) process.
13.1
274
Chapter
In
Out
or clocked logic gates are used to decreape complexity, increase speed, and
wer dissipation. The basic idea behind dynamic logic is to use the capacitive
MOSFET to store a charge and thus remember a logic level for use later.
tart looking into the design of dynamic logic gates, let's discuss leakage
the design of clock circuits.
.,*.I
276
Consider the expanded view of the charge storage node shown in Fig. 14.2.
the only leakage path on this node is through the MOSmTs drain (or
drain and source are interchangeable) n+ Ipsubstratc diode. If we consi&
the drain of the MOSFET, the current is given by
ls(e-VdnVr 1)
ID = 11-e
--
where V,,is the voltage on the storage node to ground, assuming the
ground potential. From the BSIM model parameters, the scale current is.,
Is = A D . JS
In order to simplify hand calculations we will assume that the leakage c
to the scale current, or
I m r = I s = A D . JS
The rate at which the storage node discharges is given by
dV I*akyld AD-JS
-=-=
dt Cnok
Cn~d.
The node capacitance is the sum of the input capasitarm of the inve-,
to ground of the metal m p l y line connecting the inverter to the p l s
capacitance of the drain implant to substrate (the depletion capaciuasc).
applications, we assume that
C d , = Ch of the inverter
trate
hv
1 0 4 = 3 6 0 ~1OW2'A
278
279
I I , ~ ~ ,=
, , 5 pA = VDD . GMIN
(1
and
dV - 5 PA - VDD . GMIN
dt
Cno&
Cno&
(1,
For C,, = 50 fF, it takes approximately 10 ms for the voltage on the charge st()rage
node to fall 1 V, If 1 V is the most we will allow the node to fall before we :~ P P ~ Y
another clock signal, then the minimum clock frequency is 100 Hz. The following
example illustrates the dominance of GMM in the simulation of a dynamic circuit.
Example 14.2
Simulate the circuit of Ex. 14.1. Estimate the discharge rate of the capacitor due
to the default value of GMIN.
The discharge rate from Eq. (14.7) is 1 V per 10 ms for a GMIN of 10-12mhos.
The SPICE simulation results are shown in Fig. 14.3. Notice how the leakage
drain current is jagged. This is the result of the numerical iteration scheme used
by SPICE. The simulation currents will vary by an amount less than ABSTOL,
or 1 PA. In most simulations, we do not see the small current variations.
consider the string of pass transistorshverters shown in Fig. 14.4. This circuit is
a dynamic shift register. When @, goes high, the first and third stages of the
,@er are enabled. Data are passed from the input to point A0 and from point A1 to
,A>. If Q, is low while $, is high, the data cannot pass from A0 to A1 and from A2 to
, p ~ .If Q,goes low and @, goes high, data are passed from A0 to A1 and from A2 to A3.
~f both 4, and
are high at the same time, the input of the shift register and the output
are connected together, which is not desirable in a shift register application. The
p q o s e of the inverter between pass transistors is to restore logic levels, since the
n-channel pass transistor passes a high with a threshold voltage drop. Two inverters
would be used to eliminate the logic inversion between stages. The clocks used in this
dynamic circuit must be nonoverlapping, or logically
@,
There should be a period of dead time between transitions of the clock signals, labeled A
in Fig. 14.4. The rise- and falltimes of the clock signals should not occur at the same
time.
Since the design and layout of the dynamic shift register is straightforward let's
concentrate on the generation of clock signals, @, and @,. Note that a simple logic
inversion will not generate nonoverlapping clock signals.
time
..
Time
F i ~ u r14.4
e
Dynamic shift register with associated nonoverlapping clock signals.
nding on the size of the drain anas and the leaLage cmnts.
nehanad drainhubs d i o d s 4
Subsmtc cauKcaon
piw
1 4 CMOS
~
TO used in dynlmic losic
@,
PE Logic
This section discusses precharge-evaluate logic, or PE logic. Consider th
NAND gate shown in Fig. 14.8. The operation of this gate relies on a
input. When 4, is low, the output node capacitance is charged to VDD
During the evaluate phase, 0, is high. MI is on, and if AO, Al, and A2
output is pulled low. The logic output is available only when 4, is high.
logic one when 4, is low. One disadvantage of PE logic is that the gate lo
available part of the time and not all of the time as in the static gates.
Several important characteristics of the PE gate should be pointed
input capacitance of the PE gate is less than that of the static gate.
connected to a single MOSFET where the static gate inputs are tied to
Potentially the PE gate is then faster and dissipates less power.
ad
283
VDD
Precharge
+A1 -A2+A3 A4
3
4'1
The size of the MOSFETs used in a PE gate does not need d o i n g for
a1 switching point voltage. The absence of complementary devices and the
the output is pulled hiah during each half cycle makes the gate V,
ess. ~owevcr,we may need to size the devices to attain a certain speed f o f i
d capacitance. If the sizes of all NMOS transistors used in Fig. 14.8 are equal,
t,,, is approximately 3R& and the t,, is R,C,, where C,, is the total
n the output node. ?his may include the interconnecting capacitance and
acitance of the next stage. Hae we have neglected both the transmission
a series connection of MOSFETs and the intrinsic switching speeds.
gic function, F = AO+ A1 A2 +A3 A4, implemented in PE logic is
m.
285
One problem does exist with this scheme, however, referring to Fig. 14.11, note
during the precharge phase, node A is charged to VDD. If the NMOS logic results
logic high on node A during the evaluate phase, then that node is at a high
ce with no direct path to VDD or ground. The result is charge leakage off of
A when the PE output is a logic high. The circuit of Fig. 14.12 eliminates this
em. A "keeper" p-channel MOSFET is added to help keep node A at VDD when
OS logic is off. The WIL of this MOSFET is small, so that it provides enough
to compensate for the leakage but not so much that the NMOS logic can't drive
,
1
c adder just described performs one two-bit addition with carry during each
e. Adding two-four bit words requires the use of pipelining [4]; see Fig.
e bits of the word are delayed, both on the input and output of the adder, so
of the sum reach the output of the adder at the same time. Note, however,
words can be input to the adder at the beginning of each clock
where two numbers are not added continuously can result in longer
Aca
288
14.9
Chapter
14-10
Design (sketch the schematic o f ) a full adder circuit using PE logic.
-
VLSI Layout
The past chapters have concentrated on basic logic-gate design and layout. In this
chapter we discuss the implementation of logic functions on a chip where the size and
or~mizationof the layouts are of importance. The number of MOSFFTs on a chip,
tiepending on the application, can range from tens (an op-amp) to hundreds of millions
(a 2 0 MEG DRAM). Designs where thousands of MOSFETs or more are integrated
o n n single die are termed very-large-scale-integration
(VLSI) designs.
Figure P14.12
14.13 Show that the dynamic circuit shown in Fig. P14.13 is an edge-triggered
flip-flop 151. Note that a single-phase clock signal is used.
To help us understand why chip size is important, examine Fig. 15.1. The dark
( k i n d i c a t e a defect that will lead to a chip which doesn't function properly. Figure
I(.lr shows a wafer with nine full die. The partial die around the edge of the wafer are
\ v s t d Five of the nine die do not contain a defect and thus can be packaged and sold.
Next 'conrider a reduction in the die size (Fig. 15.lb). We are assuming each die.
point, we may ask the question, "How do we determine the size of the blocks in
,2?" The answer to this question leads us into the design and layout of the cells
implement each of the logic blocks in Fig. 15.2.
cells are layouts of logic elements including gates, flip-flops, and ALU
t are available in a cell library for use in the design of a chip. Custom
to the design of cells or standard cells using MOSFETs at the lowest level.
cell design refers to design using standard cells; that is, the designer comects
n standard cells to create a circuit or system. The difference between the
design can be illustrated using a printed circuit board-level analogy. A
11 design is analogous to designing with packaged parts. The design is
hed by connecting wires between the pins of the packaged parts. Custom
analogous to designing the "insides" of the packaged parts themselves.
e 15.3 shows an example of an inverter [2]. In addition to keeping the
as small as possible, an important consideration, when laying out a standard
routing of signals. Keeping this in mind, we can state the following general
for standard-cell design:
inputs and outputs should be available, at the same relative horizontal
ce. on the top and bottom of the cell.
ntal runs of metal are used to supply power and ground to the cell, a.k.a.
r and ground busses. Also, well and substrate tie downs should be under
height of the cells should be a constant, so that when the standard cells are
end to end the power and ground busses line up. The width of the cell
be as narrow as the layout will allow. However, the absolute width is not
t and can be increased as needed.
layout should be labeled to indicate power, ground, input, and output
ons. Also, an outline of the cell, useful in alignment, should be added to
Fun-aMa cells
>
I-I
'lack
'
outpUtlrrtchc8
m)
15.4 illustrates the connection of standard cells to a bus. Note that mlv.
vertically, can cross the metall lines, which run horizontally without
t. This fact is used to route signals and interconnect standard cells in a
Also, in this figure, note how the two inverter standard cells are placed
e result is that power and ground are automatically routed to each cell.
.r
IN
,,
7;.
OUT
GNI
Control 6
IN WT
IN WT
294
Q ' R
contacts adjacent to the gate ply. Also, the gate p l y has been 1
bends. The expanded view of a pchannel MOSFET used in the SR
in Fig. 15.7. Keeping in mind that whenever p l y crosses active (n+ or
is formed, we see that the .murceof the MOSFET is connected to
contacts, while the p+ implant forms a resistive connection to
remainder of the device. The layout size, in this case the width of the
, A 4 - 2
296
al. The capacitor is placed in the middle of a standard-cell row. Also, the AC
Fe drop effects discussed in Ch. 3 are greatly reduced by inclusion of this
or.
VDD
GND
15 VLSI Layout
the FF is shown in Fig. 15.12b. The layout size and the size of the
these examples are larger than what would be used in practice to
and viewing the layouts easier. , .
e layout of the static adder is shown in Fig. 15.13. This is the
on, using near miniplum-size MOSFETs, of the AOI' static adder of Fig.
e carry-out and sum-out logic functions are imp1emcnted in this cell.
I
I
lete layout of the adder is shown in Fig. 15.14. The two four-bit
d Word-B, are input to the adder on the input bus. These data are
input latch when CLK is high, while the results of the addition are
output latch when CLK is low. The inverter standard cell of Fig. 15.3
end of the output latches and is used to generate CLK for use in the
The inputs and outputs of the adder cells are run on p l y because of the
involved. The carry-in of the adders is co~ectedto ground, as shown in
Input
bus
ng steps start with paper and pencil. Colored pencils are useful for
ng one object from another. You can use gridded paper to help achieve a
roportion in the cell plan but don't get too bogged down in the details of
l i e widths at this point; we just want to come up with a general plan. A
" is a paper and pencil tool that you can use to plan the layout of a cell.
agram resembles the actual layout but uses "sticks" or lines to represent the
When used thoughtfully, it can reveal any special hook-up
ut, and you can then resolve them without wasting any time.
S1
S l n o t S 2 S2not
,I,
Suppose the device sizes of the inverter circuit in Figure 15.16a were
@ = 3612, n = 12/2). Furthemore, let's assume that the maximum rec
gate width is 20 pn (due to the sheet resistance of the poly) and th
VDD
Part II CMOS ~ g i t a
15 VLSI Layout
Take another look at the two circuits from a geometrical rather than
viewpoint. Compare the NAND gate layout to the NOR gate layout. Do
each can be created from the other by simply "flipping" the metal and p l y
about the x-axis?
305
VDD
k 7
CLK
CLK-
s the schematic of a dynamic register cell, while Figs. 15.21 a-c show
and layout for a dynamic register. Compare the schematic of Fig.
of Fig. 15.21a We have labeled this stick diagram
will soon become apparent. Notice that there is a break
ch will form our n-channel devices. Also note that the
"cnwsco~ccted"fromone side of the layout to
this through very far to notice that, with this
clock signals is going fo be very difficult. Now
in Fig 15.21b. Notice that we have rearranged the
continuous unbroken line. Normally. this "unbroken
p r e f d . It usually results in the most workable
We say "usually" because at times your layout has to fit in an area
ocks around it and you have no control over it. Also observe from
clock signal hook-up is more straightforward Compare this stick
the layout of Fig. 15.22~. Obviously, the device sizes used for this circuit
e is merely to illustrk a layout concept. We can also see
1s a useful tool throughout the layout process.
t is basically finished, it is time to step back and take a look at it from a
of view. Is it pleasing to the eye? Is the hook-up as
ble, or is it "busy" and hard to follow? Are the spaces between
7 What about the space between diffusions? Are there
Figwe 15-19 (a) NAND stick diagram, (b) l a m (c) NOR stick &&
--
---
3M
307
T
K
CLK
dard-cell approech to physical design usually dictates that cell height be fixed
width be variable when implementing the circuit. Furthermore, standard cells
ed to abut on two sides, usually left and tight, and that abutment scheme must
regular so that any cell can residc next to any other cell without creating a
e violation. The standarden appronch to layout is very useful and is always
place to start. However, in the nal world, area on a wafer translates
so
gure 15.22 shows a typical standardcell block that has been placed and routed
c tool. M a t of the individual cells have been omitted for clarity. Notice
ect channels between the rows of standard cells. Power, ground, and clock
run vertically to both sides of the block by means of a special cell called an
ell rows are connected to power and ground through horizontal busses that
cells thunselvcs. All remaining Connections are made via the
standard-cdl l a m are designed to acconnnadate metal2
run vertically through each cell. The autorouter makes use of this
ghs aswedadinoEdato~~nmctorpass
signalsfromone
muting channels and their associated intercomecting
forboththe~tysladcircuitperf~ofthistypeof
enough contacts? Did you share all of the some and drain
shared? Are there sufficient well and substrate ties? If
followed the plan described here, you shouldn't run into too
Part 11 CMOS
15 VLSI Layout
and electrical parameters (parasitic loading). Let us examine one method
high-density custom layout that will minimize interconnect burden and
res 15.24 a-c show a small section of the interpolation filter from Fig. 15.23.
.24a, we see an explodeQ view of four cells that form part of a data-path: an
register, a t-gate, a full adder, and an output data register. These are
(placed as a cell) twice, creating a view of eight cells. The two adder cells
different: the carry inputs and outputs are on opposite sides, so that the
ade to the carry-in of the next adder by abutting (placing next to one
. Unlike standard cells, the height and width constraints placed on
are contextual. In other words, a cell's aspect ratio depends on that of its
this case, the width of each cell depended on the maximum allowable
idest cell in the group: the data register. Notice the top, bottom, left, and
s of each cell in Fig. 15.24a Data enter the register cell from the top
t the bottom. Clocks, power, ground, and control signals route across
e adder receives its A and B inputs from the top and outputs their SUM
As already mentioned, carry-out and carry-in are available on the left
f the adder, respectively. Figure 15.24b shows a two-bit slice of this
connections made by cell abutment. Figure 15.24c illustrates how all
cell join together to complete the hook-up.
e seen how circuits can be implemented by means of standard cells or
The time needed to produce a standard-cell route is far less than that of
Rmg htmr
Part 11 CMOS Di
310
311
REFERENCES
[I]
[2]
[3]
[4]
[5]
Addison-Wesley, 1
PROBLEMS
15.1 The standard-cell height can be reduced to make standardsmaller (Fig. P15.1). Using this cell as an approximate height
a double inverter.
S-I
II
the high-hpakpce nodes for the schematic of Fig. 15.20. Discuss the
one must consider when laying out a circuit with high-impedance
s three reasons to have small layout size.
D FP shown in Fig. P15.14. Show the stick diagram for your layout.
312
Chapter
XNOR
Figure P15.9
Modern BiCMOS technology began in the early 1980s with high expectations [I]. 'I
name BiCMOS comes from the fact that the logic is made using CMOS and bipo
junction transistors (BJT). The BJTs are used for their high-current capability, wh
CMOS is used because of its small layout size and ease of implementing logic. With t
best of both worlds on a single substrate, high-speed, high-current-driving bipo
transistors and low-power, high-impedance CMOS devices, every major semiconduc~
foundry now possesses some form of BiCMOS process. Strategies for developi
BiCMOS have evolved from the bipolar and the CMOS directions, with advantages a
disadvantages associated with each. Bipolar device capabilities have been added
some CMOS processes to improve speed, while CMOS device capabilities have be
added to some bipolar processes to minimize power dissipation. A chart compari
CMOS, BiCMOS, and bipolar (with l2L) technologies can be seen in Fig. 16.1 [2,:
This chapter focuses on the CMOS process with bipolar capabilities. Although t
CN20 process is not a true BiCMOS process, it does contain some BJT options that w
allow demonstration of basic digital BiCMOS circuit design. It should be noted that t
CMO~14TBprocess contains no provisions for BJT devices.
Microprocessors are particularly well suited for BiCMOS technology. Typical
generic categories limit microprocessor performance [I]: (1) Instructions F
task3 (2) cycles per instruction, and (3) time per cycle. The third category can be greal
'mproved by increasing the speed critical blocks. A PC microprocessor [41
using a bipolar-based BiCMOS process. Operating at 533 MHz, t
micro~r~cessor
used high-density CMOS devices that were added to a bipolar proce
floor plan can be seen in Fig. 16.2 [S]in which the speed critical blocks such as t
Integerand floating point units utilized BJT transistors, while power-consuming cac
arrays and I/O cells (for system compatibility) were co&ucted using -CM(
rechno~~m.
The