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voltage. As a result, the dc transfer curve would be as shown in Fig. 1.1c. The key parameters in designing a
comparator include:
Vo
Vo
VOH
V1
offset voltage,
delay
VOH
Vos
power consumption,
power supply rejection ratio (PSRR)
common-mode rejection ratio (CMRR).
V2
Vo
V1-V2
V1-V2
VOL
VOL
Again, since a comparator is essentially a high-gain op amp, the offset voltage can be calculated exactly as
done for amplifiers. For references, here is a summary of the results. Please refer to the lecture notes offset.ps for
detailed derivation.
(a)
(b)
(c)
R I S
V OS = V T ------- -------IS
R
(1.1)
Typically, R/R = 1%, IS/IS = 5%, which corresponds to a offset voltage VOS of 1.5 mV.
Fig. 1.1 Comparator (a) symbol, (b) ideal transfer curves, (c) non-ideal transfer curve
(1.2)
Assume that Vt = 10 mV, VGS-Vt = 300 mV, R/R = 1%, (W/L)/(W/L) = 5%, the offset voltage VOS
becomes approximately 20 mV, which is much larger than that of an emitter-coupled pair.
gm
( V GS V t ) N ( W L ) N ( W L ) P
= V t + ( V t ) --------P- + ------------------------------ ------------------------- -----------------------N
P g
2
(W L )N
( W L )P
m
(1.3)
Assume that V t = 10 mV, V GS -V t = 300 mV, (W/L)/(W/L) = 5%, the offset voltage VOS becomes
approximately 35 mV, which is much larger than that of any other configuration!
1.2.1.4 A cascade of many gain stages:
In many applications, a cascade of many low-gain amplifiers is used to realize a comparator as opposed to a
single high-gain amplifier, as shown in Fig. 1.2. Assume that the gain and offset voltage of each amplifier are A1,
Vos1, A2, Vos2,..., An, and Vosn, respectively, the total input-referred offset voltage can be calculated as follows.
V OS
+
A2
Vos2
Vosn
An
+
A1
Vos1
V OS
V OS
V OS
n
3
=V
+ ------------2 + ---------------- + + ----------------------------A1 A( n 1 )
OS 1
A1
A1 A2
(1.4)
By making the gain of the first amplifier stage high, the offset voltages of subsequent stages can be neglected,
and the total offset voltage at the input is minimized. However, as will be shown later, to optimize the settling time
of the comparator, it is desirable to use amplifier stages with small gains, in which the above equation should be
used to estimate the total offset voltage!
1.2.1.5 Offset Cancellation Techniques:
Typically, dynamic latches can be used to reduce the comparators power consumption. The main problem
with these dynamic latches is that the offset voltage is much bigger than non-dynamic circuits.
To reduce the offset voltage of a comparator, there exist many offset cancellation techniques (auto-zero
techniques) that have been widely used. We will discuss these techniques in more details later, but the basic idea is
described briefly here.
First we would somehow measure and store the output voltage of the comparator with the input voltage being
set to zero. Due to the offset voltage, the stored output Vo1 would be:
Vo
= A V os
(1.5)
The next step is to measure the output voltage Vo2 with the real input voltage. Since this output voltage Vo2 is
equal to:
Vo
= A ( V os + V in )
(1.6)
V1-V2
V1
If we can subtract the stored output voltage Vo1 from this measured output Vo2, the difference is an amplified
version of the input voltage without the offset voltage being nulled. the offset voltage is effectively cancelled as
V2
shown below.
Vo Vo
2
= A ( V os + V in ) A V os = A V in
Vod
Vo
0
Vinit
latch
(1.7)
latch
td (ns)
In practice, a latch is normally realized and connected at the output of the comparator to provide a
regenerative (positive) feedback to shorten the comparison time. In order to ensure a 100% probability of getting
correct outputs, there is a minimum delay time td required between the assertion of the input and the latching of the
-1
-0.5
20
Vinit increases!
10
As a result, the total comparison time tT of a comparator consists of two parts: the delay time td and the
settling time ts. The delay time td is dependent on input parameters, namely the initial voltage vinit and the overdrive
voltage vod. As indicated in Fig. 1.3, the delay time gets smaller as the overdrive voltage vod is increased or the input
td
1
10
100
Vod (mV)
Vo
tr
In designing a fast-settling comparator, either a single high-gain amplifier or a cascade of many low-gain
amplifiers can be used. Consequently, the mostly asked questions are What is the optimized gain per stage? and
What is the optimized number of comparator stages needed to minimize the comparators settling time?
tT
Fig. 1.3 Transient responses of a latched-type comparator
To figure out the answers, lets look at a generic design where a cascade of n identical gain stages is used.
Shown in Fig. 1.4 is a typical block diagram of a fast-settling comparator, which is composed of a cascaded chain of
many source-coupled pairs (SCPs) followed by a latch at the end.
1
V o ( t ) = V in ( t ) = --------1
2
CT
1
1
V o ( t ) = V in ( t ) = --------2
3
CT
b) The initial voltage Vinit is zero and all the stages are nulled at t = 0
1
+ V o ( t = 0 ) = --------2
CT
io2 dt
0
1
V o ( t ) = --------n
CT
d) The overdrive voltage applied at the input of the first stage is Vod.
Now, we are ready to estimate the delay time of the comparator. From Fig. 1.4, the output voltages at the
output nodes as functions of time can be derived to be:
gm
= --------1- v od t
CT
(1.8)
gm g
2
1 m2
t
---= ------------------v
C T C od 2
(1.9)
gm1 vin1 dt
0
gm2 vin2 dt
0
ion dt
0
g m g g m
n
1 m2
n
t
----= ----------------------------------v
C T C C T od n!
1
T2
Vo2
T2
(1.10)
If all the stages are identical, that is gmi = gm and CTi = CT for all i, we get:
n
gm n
t
1 t n
V o ( t ) = ------- v od ----- = ----- -- v od
n
CT
n!
n!
Vo1
V2
1
+ V o ( t = 0 ) = --------1
CT
In general, the output voltage Von(t) of the nth stage is given by,
V1
io1 dt
(1.11)
Vo
Von
Latch
io
CT = Cgs + Cp
where
C gs
CT
C p + C gs
Cp
Cp
1
- = ---------------------- = -------- 1 + -------- = ------------ 1 + ------- = -----2f T
gm
gm
gm
C gs
C gs
(1.12)
From Eq. 1.12, it can be concluded that the delay time of the comparator can be minimized if the transition
frequency fT is maximized and the parasitic capacitance at the output node Cp is minimized.
The waveforms of the output voltages of the first three stages are plotted in Fig. 1.5, from which it can be seen
that the optimal number of stages to minimize the delay time depends on the voltage VL required for the latch. As
indicated in the figure, if the latch voltage required is VL1, VL2, or VL3, the delay will be minimal if the number of
stages n is chosen to be 1, 2, and 3, respectively.
nopt
In general, the delay time required to achieve an output voltage of VL can be obtained by solving Eq. 1.11:
vL
t d = n! ------v od
x
x
1n
(1.13)
x
x
It is desirable to have an analytical expression which can be used to predict the optimized number of stages
required to achieve the minimal delay time. Unfortunately, such an expression does not exist. However, it has been
found empirically [David Soo, Ph. D. Thesis, UC Berkeley, 1984] that the optimal number of stages nopt and the
16
32
64
128
ln (VL/Vod)
corresponding optimal delay time td as functions of the overall gain (VL/Vod) are as shown in Figs. 1.6 and 1.7.
Fig. 1.6 Optimal number of amplifier stages as a function of the required gain
From the two plots, the optimal number of stages nopt can be estimated as:
n=3
Von
td
n=2
VL3
n=1
VL2
VL1
ln (VL/Vod)
t
Fig. 1.7 Optimal delay of the cascaded comparator as a function of the required gain
vL
n opt 1.2 ln ------v od
If such an optimal number of stage is used, the optimal delay time td given by Eq. 1.13 can be approximated
to be:
vL
t d ln ------v od
(1.19)
gm vi
gm vi
2 2
2 2
= -------------= --------------------CT
C gs + C p
(1.20)
gm vi
gm vi
1 1
1 1
= -------------= --------------------CT
C gs + C p
(1.21)
dt
(1.16)
and
dv i
dt
(1.17)
where Cp is the parasitic capacitance at the output node and Cgs is the gate capacitance of the input devices.
vi vi = vi vi
1
3 ( V GS V T )
gm
W
C gs
C gs
C gs
C ox ----- ( V GS V T )
L
a source-coupled pair.
(1.15)
As an example, consider an CMOS comparator, where the effective length Leff = 1.0 m, the mobility = 500
cm2V-1s-1, VGS - VT = 1V, VL/Vod = 1000, and Cp = Cgs, the optimal number of stages nopt can be calculated to be:
vL
n opt 1.2 ln ------- = 1.2 ln ( 1000 ) 8
v od
Due to the regenerative feedback, a latch can be used to shorten the settling time for a comparator. Figure 1.8
shows an implementation of a comparator using a latch, which is realized by cross-coupling the two input devices of
d vi
(1.18)
dt
from which,
g m dv i
2
gm
= --------1 1 = ---------------------- v i
2
CT dt
C gs + C p
(1.22)
t
t
v i ( t ) = C 1 exp -- + C 2 exp --
2
C gs + C p
= ---------------------gm
(1.23)
(1.24)
If the latch is used as a comparator with an input voltage of vod and an output of vL, the first exponential term
can be neglected, and the delay time td can be found to be:
where:
vL
t d ln ------v od
(1.25)
which is exactly the same as derived in Eq. 1.15 for a chain of comparators!
t=0
t=0
Vi+
Vi1
Vi2
Vi-
n=3
Von
n=2
VL3
Vinit = 0
Vc
n=1
VL2
VL1
0
t
(a)
Von
Vinit = large!
n=1
n=3
n=2
-Vmax
(a)
(b)
Fig. 1.10 Comparison of transient responses of the comparator with (a) zero
(b)
Fig. 1.11 Design techniques to avoid overload recovery using (a) passive and (b) active clamps
Small-Load Implementation:
VB
M5
IB
M7
As we have estimated before, the offset voltages for a source-couple pair (SCP) and for an emitter-coupled
pair (ECP) are typically 10 mV and 1 mV, respectively. Whether an offset cancellation is required would depend on
the application (mainly the resolutions) and the technology (BJT, CMOS). Table 4.1 lists some general design
M1
M2
Note that for 8-11 bits, CMOS comparators tend to be slower than their BJT counterparts because they would
need offset nulling
VB
M10
Resolution Bits
< 7 bits
8-11 Bits
> 12 Bits
> 10 mV
~ 1 mV
< 0.1 mV
BJT Implementation
No Cancellation
No Cancellation
Cancellation
CMOS Implementation
No Cancellation
Cancellation
Cancellation
c) PMOS operating in triode region: small parasitic, can use replica biasing (Fig. 1.11)
M11
M3
M4
M8
M9
A
V C = V o = ------------- V os V os
1+A
Figure 1.13 shows a typical scheme in which an input nulling capacitor C is used with feedback to eliminate
the offset voltage. During the offset cancellation, the switches are closed as shown in Fig. 1.13a. As a result,
V C = V o = A ( V C V os )
(1.27)
During comparison, the switches are closed as shown in Fig. 1.13b, from which it can be easily found that:
V o = A ( V in + V C V os ) = A ( V in )
(1.26)
(1.28)
So, the output is independent on the offset voltage, ie. the offset voltage is indeed cancelled! This cancellation
technique is very simple. However, it inherently has two problems. First, the charge injection may cause error as the
and therefore,
switches turn off. A big capacitor C can be used to reduce this error, but the overall speed would be reduced.
Secondly, due to the nature of the operation, the comparator needs to be compensated for unity-gain stability.
Vin
C
+
Vc
Vos
Shown in Fig. 1.14 is an open-loop scheme in which interstage capacitors are used to null out the offset
voltage. During offset measurement phase, the switches are closed as shown in Fig. 1.14a, from which the offset is
stored on the capacitor C:
Vo
(a)
V C + ( t = 0- ) = A 1 ( V os )
(1.29)
V C - ( t = 0- ) = 0
(1.30)
Vin
C
+
Vc
_
A
Vos
During the comparison phase, the switches are closed as shown in Fig. 1.14b, from which the input voltage of
the second stage is given by:
Vo
V C + ( t = 0+ ) = A 1 ( V in V os )
(1.31)
V in = V C - ( t = 0+ ) = V C + ( t = 0+ ) + [ V C - ( t = 0- ) V C + ( t = 0- ) ] = A 1 V in
(1.32)
(b)
So, in fact, the offset voltage of the first stage Vos1 is eliminated and thus does not affect the input of the
second stage. Repeating the same for the subsequent stages, all the offset voltages Vos2,..., Vosn, will be effectively
removed.
+
Vin
Vos1
+
_
A1
Vc
Vos2
+ Vin2
+
A
_ 2
The output current from the second input io2 is given by:
Vo
+
(a)
+
Vin
Vos1
+
_
Vin
A1
Vc
Vos2
+ Vin2
Vos1
io1
gm1
Vo
io
io2
+
A
_ 2
Vo
Vos2
+
gm2
(b)
i 0 = i 0 = g m V os
2
(1.33)
During comparison, the switches are reversed. The output current of the auxiliary stage io2 remains the same
due to the capacitor C whereas the output current of the main stage io1 becomes:
i 0 = g m ( V in V os )
1
(1.34)
As a result,
V o = i 0 R L = ( i 0 + i 0 ) R L = g m R L ( V in V os + V os ) = g m R L V in
1
(1.35)
Again, it is clearly that the offset voltage of the first stage Vos1 has been removed and does not affect the
output voltage!
In practice, non-zero offset voltage of the auxiliary stage can contribute to the error. However, this error can
be minimized as long as this offset voltage of the auxiliary stage Vos2 when referred to the input is much smaller than
that of the main stage Vos1. This in turn can be achieved by making sure that the transconductance of the auxiliary
stage gm2 is much smaller than that of the main stage gm1, as can be seen from the following equation.
V OS
input
gm
i0
= -------2- = --------2 V os
2
gm
gm
1
(1.36)