FACAULTY OF APPLIED SCIENCES

COMPUTER SCIENCE DEPARTMENT

Computer Data Communication

NAME

UGWAK

SURNAME

UGWAK

STUDENT NUMBER :

N01521664R

DEPARTMENT

COMPUTER SCIENCE

COURSE CODE

SCS2101

DUE DATE

29/OCT/2016

LECTURER

MR. S. NLEYA

CLASS ASSIGNMENT-SCS2101 (ConV)

QUESTION 1
Given the following 8 bit pattern 01011100 and the generator polynomial
x3+x2+1,
(i) Compute the CRC bits.
(ii) Assuming a 1 bit error that transforms the 8 bit pattern from 01011100 to
11011100, show that the pattern protected by the above CRC can detect the
error.
QUESTION 2
Explain the following methods
(a)

(i)VRC

(ii)LRC
(iii)CRC
(b)How is a generator used in cyclic redundancy check
SOLUTIONS
1.
CRC generator poly: 1101
Performing poly long division, CRC bits: 0000. Note: The original 8 bit data pattern when
it is extended by 4 bits is directly divisible by the generator poly.
Data pattern with CRC: 010111000000
When the data pattern is corrupted from 01011100 to 11011100, the overall bitp pattern
including CRC bits is:
110111000000
Dividing the above by the CRC generator poly 1101, yields a non-zero remainder of 0111.
In the absence of an error the remainder should have been 0.

2(a)i) VRC
Vertical redundancy check (VRC) is an error-checking method used on an eight-bit ASCII
character. In VRC, a parity bit is attached to each byte of data, which is then tested to
determine whether the transmission is correct. VRC is considered an unreliable errordetection method because it only works if an even number of bits is distorted.
A vertical redundancy check is also called a transverse redundancy check when used in
combination with other error-controlling codes such as a longitudinal redundancy check.
If the network is set for the default odd parity, the parity bit would be a 1, as that would create
an eight-bit byte with the sequence 01101011, thereby creating an odd parity value.
Alternatively, the parity bit would be a 0 if the network is set for even parity, as that would
create an eight-bit byte with the sequence 01101010, thereby retaining an even parity value.
The receiving device executes the same mathematical process to verify that the correct total
bit value was received, hence the use of the terms redundancy and checking. Speaking in
terms of the logical manner in which humans add numbers physically positioned in columns,
the two devices sum the bit values vertically, as represented in the following table, hence the
use of the term vertical.VRC is easily and inexpensively implemented in computers
employing asynchronous transmission, but is highly unreliable, as two error bits in a
character yield an undetectable error. Further, VRC provides no inherent means of error
correction.VRC often is characterized as send and pray.
(ii)LRC
A longitudinal redundancy check (LRC) is an error-detection method for determining the
correctness of transmitted and stored data.
LRC verifies the accuracy of stored and transmitted data using parity bits. It is a redundancy
check applied to a parallel group of bit streams. The data to be transmitted is divided into
transmission blocks into which additional check data is inserted.
LRC is generated through the following steps:
1. Add all bytes in messages excluding the starting colon and the ending the carriage return
line feed
2. Add this to the eight-bit field and discard the carries
3. Subtract the final field value from FF hex, producing ones complement
4. Add one, producing twos complement
In a system environment where a data stream is accepted from a host during host-initiated
operations, LRC calculations are performed and appended to every received data block. The
resulting blocks are stored by the subsystems. As data passes through the subsystem, LRC
calculations are performed. If the host requests data later, a data block is sought along with
the previously calculated LRC. The same LRC exclusive or calculations are performed and
compared with stored LRC values as data is transferred to the host. If the stored value
matches the newly calculated values, the data is considered to be valid.

(iii)CRC
CRC is an approach to detect if the received frame contains valid data. This technique
involves binary division of the data bits being sent. The divisor is generated using
polynomials. The sender performs a division operation on the bits being sent and calculates
the remainder. Before sending the actual bits, the sender adds the remainder at the end of the
actual bits. Actual data bits plus the remainder is called a codeword. The sender transmits
data bits as codewords.
Sender

Receiver

11
Divis
or

101 11001
101
110
101
111
101
10

111
Dat
a
bits

CRC

Divis
or

101

1100110
101
110
101
111
101
101
101
000

Data bits +
CRC

No
ERROR

At the other end, the receiver performs division operation on codewords using the same CRC
divisor. If the remainder contains all zeros the data bits are accepted, otherwise it is
considered as there is some data corruption occurred in transit.
Advantages of Cyclic Codes
We have seen that cyclic codes have a very good performance in detecting single-bit
errors, double errors, an odd number of errors, and burst errors. They can easily be
implemented in hardware and software. They are especially fast when implemented in
hardware. This has made cyclic codes a good candidate for many networks.

(b)How is a generator used in cyclic redundancy check

The General CRC Generator block generates cyclic redundancy code (CRC) bits for each
input data frame and appends them to the frame. This block accepts a binary column vector
input signal.
You specify the generator polynomial for the CRC algorithm using the Generator polynomial
parameter. This block is general in the sense that the degree of the polynomial does not need
to be a power of two. You represent the polynomial in one of these ways:
As a polynomial character vector such as 'X3 + X2 + 1'.

As a binary row vector containing the coefficients in descending order of powers. For
example, [1 1 0 1] represents the polynomial X3 + X2 + 1.
As an integer row vector containing the powers of nonzero terms in the polynomial, in
descending order. For example, [3 2 0] represents the polynomial X3 + X2 + 1.
You specify the initial state of the internal shift register by the Initial states parameter. The
Initial states parameter is either a scalar or a binary row vector of length equal to the degree
of the generator polynomial. A scalar value is expanded to a row vector of length equal to the
degree of the generator polynomial. For example, the default initial state of [0]is expanded to
a row vector of all zeros.
You specify the number of checksums that the block calculates for each input frame by the
Checksums per frame parameter. The Checksums per frame value must evenly divide the size
of the input frame.
If the value of Checksums per frame is k, the block does the following:
1.
Divides each input frame into k subframes of equal size
2.
Prefixes the Initial states vector to each of the k subframes
3.
Applies the CRC algorithm to each augmented subframe
4.
Appends the resulting checksums at the end of each subframe
5.
Outputs concatenated subframes
If the size of the input frame is m and the degree of the generator polynomial is r, the output
frame has size m + k * r.
This block supports double and Boolean data types. The block inherits the output data type
from the input signal.

REFERENCES.
Tutorial Points (2014), Learn DCN, Data Communication and Computer Networks
Michael D. & Richard R (2003), Data Communication and Computer Networks for Computer
Scientists and Engineers Second edition.
Behrouz A. Forouzan (2007), Data Communications and Networking, Fourth Edition